CN106034377B

CN106034377B - Selective segment via plating process and structure

Info

Publication number: CN106034377B
Application number: CN201510121886.XA
Authority: CN
Inventors: 余玛莉; 潘关
Original assignee: Multek Technologies Ltd
Current assignee: Multek Technologies Ltd
Priority date: 2015-03-19
Filing date: 2015-03-19
Publication date: 2020-06-16
Anticipated expiration: 2035-03-19
Also published as: CN106034377A

Abstract

A selective section via plating process for manufacturing circuit boards that selectively interconnect internal conductive layers as separate sections within the same via. A plating resist is applied to the conductive layer of the core and then stripped off after the electroless plating process. This electroless plating stripping of the plating resist causes plating discontinuities on the via walls. During subsequent electroplating, the inner plug non-conductive layer cannot be electroplated due to this plating discontinuity. The resulting circuit board structure has a plurality of separate electrical interconnect segments within the via.

Description

Selective segment via plating process and structure

The invention belongs to the field of the following:

the present invention generally relates to printed circuit boards. More specifically, the present invention relates to printed circuit boards having selective section via plating.

Background of the invention:

a Printed Circuit Board (PCB) mechanically supports and electrically connects electronic components using conductive traces, pads, and other features etched from a conductive sheet (e.g., a copper sheet) laminated onto a non-conductive substrate. A multi-level printed circuit board is formed by stacking and laminating a plurality of such etched conductive sheet/non-conductive substrate laminates. The wires on the different layers are interconnected with plated through holes, called vias.

Fig. 1 shows a cut-out side view of a portion of a conventional printed circuit board. The printed circuit board 2 comprises a plurality of stacked layers made of a plurality of

non-conductive layers

4, 6 and a plurality of conductive layers 8. These non-conductive layers may be made of a prepreg or substrate that is part of the core structure or is the core only. Prepregs are fiber-reinforced materials that are impregnated or coated with a thermosetting resin binder and consolidated and cured into an intermediate-stage semi-solid product. The prepreg serves as an adhesive layer to bond a plurality of discrete layers of a multi-layer PCB structure, wherein the multi-layer PCB is composed of a plurality of conductive lines and alternating layers of a plurality of base materials bonded together, including at least one inner conductive layer. The substrate is an organic or inorganic material for supporting the pattern of conductor material. The core is a metal clad substrate wherein the substrate has integral metal wire material on one or both sides. A laminated stack is formed by stacking a plurality of core structures with prepregs interposed therebetween and then laminating the stack. The vias 10 are then formed by drilling holes through the laminated stack and plating the walls of the holes with a conductive material, such as copper. The resulting plating 12 interconnects these conductive layers 8.

In the exemplary application shown in fig. 1, the plating layer 12 extends uninterrupted through the entire thickness of the via 10, thereby providing a common interconnect with each conductive layer 8. In other applications, it may be desirable that only some of the conductive layers are commonly interconnected by plating within the vias. The common interconnect layer is referred to as a segment. Formation of the segments requires a break in the via wall plating, however, the electroplating process that forms the plating on the via walls is commonly applied to the entire wall surface. Thus, to form the desired plated breaks, the printed circuit board is formed as a stack of individual components that are laminated together. Each component laminate stack has the desired plated vias, but when laminated together, the plated vias from each component laminate stack are separated by a broken non-conductive material that forms the entire via wall plating. Fig. 2 shows a cut-out side view of a portion of two conventional component stacks to be subsequently used to form a printed circuit board. The component laminate stack 20 includes a plurality of non-conductive layers 24, 26 and a plurality of conductive layers 28. The non-conductive layers 24 and the conductive layers 28 form a plurality of core structures that are laminated together with the non-conductive layer 26 (e.g., prepreg) in between. The vias 22 are formed by drilling through the laminated stack and plating the walls of the holes with a conductive material. The resulting plating interconnects these conductive layers 28. The second component laminate stack 30 is formed in a similar manner and includes a laminate stack of a plurality of non-conductive layers 34, 36 and a plurality of conductive layers 38 and plated vias 32. To form a complete printed circuit board, the two

components

20 and 30 are stacked such that the

respective vias

22 and 32 are aligned and laminated together with the non-conductive layer 40 in between, as shown in fig. 3. The non-conductive layer 40 provides a break in the conductive plating of the via 22 and the conductive plating of the via 32, thereby forming two separate sections in the printed circuit board of fig. 3.

The process shown in fig. 2 and 3 is known as progressive pressing. The problem with progressive pressing is that it is difficult to properly align the vias of the stacked components. As shown in fig. 3, one via centerline 42 of a via 22 in component 20 is not properly aligned with one via centerline 44 of a via 32 in component 30. This is referred to as layer-to-layer misalignment and can lead to performance problems.

In some applications, one or more of the conductive layers closest to the top or bottom surface of the printed circuit board are not designed to interconnect with the via plating. In order to cut off this connection of the one or more conductive layers, a backdrilling process is performed, wherein holes are drilled into the printed circuit board at the vias. The hole diameter is wider than the via diameter such that the drilled hole clears the wall plating and thereby the interconnect plating between the plurality of conductive layers. Fig. 4 shows a cut-out side view of a portion of a conventional printed circuit board with a via back drilled. The printed circuit board 52 is similar to the printed circuit board 2 of fig. 1, except that the hole 64 has been back drilled into the printed circuit board 52. The backdrilled holes 64 clear the corresponding portions of the plating 62 in the vias 60 that are in the same location as the several bottom layers of the printed circuit board 52. The remaining plating 62 provides interconnection to the conductive layers 58, however, the best conductive underlayer 58' is no longer interconnected to the conductive layers 58 because the interconnect plating 62 is removed in the holes 64. Importantly, the backdrilling process leaves the conductive layers 58 intact, which results in a via stub (stub)66 extending from the last interconnected conductive layer 58. A via stub is a conductive portion of a via that is not connected in series with a circuit. The longer the via stub, the greater the signal reflection and degradation. As such, it is desirable to minimize the length of the via stub. However, conventional backdrilling processes have high variability and it is difficult to control the length of the via stub. Furthermore, backdrilling is time consuming and expensive.

Summary of the invention:

various embodiments relate to a selective section via plating process for manufacturing circuit boards having selective inner layer connections as separate sections within the same via. A plating resist is applied to the conductive layer of the core and then stripped off after the electroless plating process. This electroless plating stripping of the plating resist causes plating discontinuities on the via walls. During subsequent plating, the plug non-conductive layer cannot be plated due to this plating discontinuity. The resulting circuit board structure has a plurality of separate electrical interconnect segments within the via. The selective segment via plating process uses a single lamination step.

In one aspect, a circuit board is disclosed. The circuit board includes a laminated stack including a plurality of non-conductive layers and a plurality of conductive layers. The laminated stack further includes an interposer layer. The interposer layer includes one or more plating-resistant resist layers. A via is formed through the laminate stack wherein walls of the via are plated with a conductive material except where the via passes through the interposer layer, thereby forming a via wall plating discontinuity. In some embodiments, each of these conductive layers is etched with a pattern. In some embodiments, the via comprises a single bore through the entirety of the laminate stack. In some embodiments, the via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. In certain embodiments, the one or more plating resist layers are coupled to the conductive layer of the first segment and to the conductive layer of the second segment. In some embodiments, the one or more plating resist layers prevent the formation of a plating stub extending from the first segment. In some embodiments, the one or more plating resist layers prevent the formation of a plated stub extending from the second segment. In some embodiments, the circuit board further comprises one or more additional inner core layers within the laminate stack, wherein each additional inner core layer forms an additional via wall plating discontinuity. In some embodiments, each additional via wall plating discontinuity creates an additional electrically interconnected conductive layer segment. In some embodiments, the via wall plating discontinuity is aligned with the one or more plating resist layers. In some embodiments, the circuit board further includes a cavity extending from the via in the interposer layer. In some embodiments, the interposer layer includes a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer.

In another aspect, another circuit board is disclosed. The circuit board includes a laminate stack, a via formed through the laminate stack, and a cavity extending from the via. The laminated stack comprises a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminated stack further comprises an inner plug layer comprising one or more plating resist layers. The walls of the via are plated with a conductive material except where the via passes through the interposer layer. The cavity extends from the via of the interposer layer, wherein the cavity forms a via wall plating discontinuity. The via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. In some embodiments, each of these conductive layers is etched with a pattern. In some embodiments, the via comprises a single bore through the entirety of the laminate stack. In certain embodiments, the one or more plating resist layers are coupled to the conductive layer of the first segment and to the conductive layer of the second segment. In some embodiments, the one or more plating resist layers prevent the formation of a plating stub extending from the first segment. In some embodiments, the one or more plating resist layers prevent the formation of a plated stub extending from the second segment. In some embodiments, the circuit board further comprises one or more additional inner core layers within the laminate stack, wherein each additional inner core layer forms an additional via wall plating discontinuity. In some embodiments, each additional via wall plating discontinuity creates an additional electrically interconnected conductive layer segment. In some embodiments, the via wall plating discontinuity is aligned with the one or more plating resist layers. In some embodiments, the interposer layer includes a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer.

In yet another aspect, a multiple network architecture is disclosed. The multiple network structure includes a circuit board and a pin inserted in a via hole of the circuit board. The circuit board includes a laminate stack and the via. The laminated stack comprises a plurality of non-conductive layers and a plurality of conductive layers, wherein the laminated stack further comprises an inner plug layer comprising one or more plating resist layers. The via is formed through the laminated stack. The walls of the via are plated with a conductive material except where the via passes through the interposer layer, thereby forming a via wall plating discontinuity. The via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. The pin is electrically coupled to each of the first and second segments to provide independent electrical connections from each of the first and second segments to the pin.

In yet another aspect, a method of manufacturing a circuit board is disclosed. The method includes forming a laminate stack. The laminate stack includes a plurality of non-conductive layers, a plurality of conductive layers, and an inner plug layer, wherein the inner plug layer includes one or more plating resist layers. The method also includes forming a via through the laminate stack. The via passes through the one or more plating resist resistant layers such that portions of the via wall corresponding to the one or more plating resist resistant layers include plating resist. The method also includes stripping portions of the one or more plating resist layers exposed at the via. The method also includes performing a electroless plating process to plate the via walls such that portions of the plating layer are formed on those portions of the via walls that include plating resist. The method also includes stripping those portions of the plating layer that are formed on those portions of the via wall that include plating resist and stripping those portions of the one or more plating resist layers to form via wall plating discontinuities on the second via wall that coincide with the one or more plating resist layers within the laminate stack. The method also includes performing an electroplating process to further electroplate remaining portions of the plating on the via walls while maintaining the via wall plating discontinuities. In some embodiments, the interposer layer includes a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer. In some embodiments, the electroplating process is performed to dissolve a portion of the plating on the plug non-conductive layer, thereby forming a continuous via wall plating discontinuity across the entire interposer layer. In some embodiments, the portions of the plating layer are stripped and the portions of the first and second plating resist layers are stripped to form the via wall plating discontinuities from respective cavities extending from the via, wherein a first cavity is aligned with the first plating resist layer and a second cavity is aligned with the second plating resist layer in the laminate stack. In some embodiments, stripping portions of the one or more plating resist layers forms a cavity extending from the via.

In certain embodiments, forming the laminate stack includes forming a first component including a first non-conductive layer, a first conductive layer coupled to a first surface of the first non-conductive layer, a second conductive layer coupled to a second surface of the first non-conductive layer, and a first plating resist resistant layer coupled to the second conductive layer. Forming the laminate stack can also include forming a second component including a second non-conductive layer, a third conductive layer coupled to a first surface of the second non-conductive layer, a fourth conductive layer coupled to a second surface of the second non-conductive layer, and a second plating resist resistant layer coupled to the third conductive layer. Forming the laminate stack may further include stacking the first component onto the second component such that the first plating resist layer faces the second plating resist layer. Forming the laminated stack may also include stacking at least one additional non-conductive layer and one additional conductive layer onto the first conductive layer of the first component and onto the fourth conductive layer of the second component, thereby forming a stack. Forming the laminated stack may also include laminating the stack to form the laminated stack. In certain embodiments, stacking the first component onto the second component includes positioning a non-conductive layer therebetween.

In certain embodiments, the method further comprises etching a pattern into the conductive layers in the laminate stack. In some embodiments, the via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the plurality of second via wall plating discontinuities electrically insulate the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment. In certain embodiments, performing the electroplating process includes applying electricity to the first section and to the second section. In some embodiments, the first plating resist layer prevents the formation of a plated stub extending from the first segment. In some embodiments, the second plating resist layer prevents the formation of a plated stub extending from the second segment. In certain embodiments, forming the laminate stack further comprises including one or more additional inner core layers within the laminate stack, wherein each additional inner core layer forms a plurality of additional via wall plating discontinuities. In some embodiments, each additional inner core layer creates an additional electrical interconnect conductive layer segment. In some embodiments, forming the via includes drilling a single bore through the entirety of the laminate stack.

Brief description of the drawings

Several example embodiments are described with reference to the drawings, wherein like components are provided with like reference numerals. These example embodiments are intended to illustrate, but not to limit, the invention. These drawings include the following figures:

fig. 1 shows a cut-out side view of a portion of a conventional printed circuit board.

Fig. 2 shows a cut-out side view of a portion of two conventional component stacks to be subsequently used to form a printed circuit board.

Fig. 3 illustrates a progressive pressing of the two component stacks of fig. 2.

Fig. 4 shows a cut-out side view of a portion of a conventional printed circuit board with a via back drilled.

Fig. 5 illustrates a cut-out side view of a portion of a printed circuit board according to an embodiment.

Fig. 6-12 illustrate various steps in a selective segment via plating process for manufacturing the printed circuit board of fig. 5.

Fig. 13 illustrates a cut-out side view of a portion of a printed circuit board according to another embodiment.

Fig. 14 illustrates a cut-out side view of a portion of a printed circuit board according to yet another embodiment.

Fig. 15 shows an alternative lamination step.

Fig. 16 illustrates an exemplary printed circuit board resulting from the lamination step of fig. 15.

Detailed description of embodiments:

embodiments of the present application relate to a printed circuit board. Those skilled in the art will realize that the following detailed description of a printed circuit board is illustrative only and is not intended to be in any way limiting. Other embodiments of such printed circuit boards will readily suggest themselves to such skilled persons having the benefit of this disclosure.

Reference will now be made in detail to implementations of printed circuit boards as illustrated in the accompanying drawings. Throughout the drawings and the following detailed description, the same reference indicators will be used to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions must be made in order to achieve the developer's specific goals, such as compliance with application-and business-related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

Fig. 5 illustrates a cut-out side view of a portion of a printed circuit board according to an embodiment. The printed circuit board 102 is fabricated using a selective segment via plating process, an embodiment of which is described with respect to fig. 6-12. The printed circuit board 102 includes a plurality of stacked layers made of a plurality of

non-conductive layers

104, 106 and a plurality of conductive layers 108. These non-conductive layers may be made from a prepreg or substrate that is part of the core structure or plug assembly. The core structure includes a non-conductive layer (e.g., a substrate), a patterned conductive layer on one or both opposing surfaces of the non-conductive layer. The plug assembly is formed by applying a plating-resistant resist layer to the surface of the core structure. The inner plug layer 140 is formed by adjacently positioning two plug assemblies each having a plating resist layer 118. In the exemplary configuration shown in fig. 5, an intervening non-conductive layer 106 (e.g., prepreg) is positioned between two plating resist resistant layers 118. A laminated stack is formed by stacking a plurality of plug structures and core structures with a non-conductive material (e.g., prepreg) interposed therebetween and then laminating the stack. Any conventional lamination technique may be used. The exemplary laminate stack shown in fig. 5 has two plug assemblies. It should be understood that the laminated stack can be fabricated with more or less than two plug assemblies. The exemplary laminate stack shown in fig. 5 does not include a plurality of core structures that have not yet been formed within a plurality of plug assemblies. It should be understood that the laminated stack may be fabricated to include one or more core structures that have not yet been formed into a plurality of plug assemblies. The vias 110 are formed by drilling holes through the laminated stack and plating the walls of the holes with a conductive material, such as copper. The resulting plated layer 112 interconnects the plurality of selectively conductive layers 108. The interposer layer 140 is selectively positioned during the lamination stack formation process for separating the printed circuit board 102 into the

segments

120 and 130. The plug 140 includes a plating resist 118 that prevents the formation of the plating layer 112 in the cavity 115 and the region 114 during the plating process. As a result, the plating 112 in segment 120 is disconnected from the plating 112 in segment 130. This results in a via 110 having two electrically

isolated segments

120 and 130. A segment may also be referred to as a net, which is a sub-circuit. Each segment provides independent electrical connection to a pin inserted into the through hole. Thus, the printed circuit board having a plurality of segments is a multi-net structure.

In this embodiment, the selective positioning of the two plating resist layers 118 substantially eliminates the formation of plating stubs extending from the conductive layers 108 nearest the cavities 115. In some embodiments, a flash plating layer deposited on the exposed surfaces of the conductive layer 108 within the cavity 115 remains.

The number of layers in the PCB 102 and the location of the plugs 140 within the layer stack shown in fig. 5 are for exemplary purposes only. This selective segment via plating process allows freedom to interconnect each successive inner conductive layer as separate segments within the same via. In the exemplary configuration shown in fig. 5, the top three conductive layers are interconnected into one segment and the bottom three conductive layers are interconnected into another segment. It should be understood that not all segments need have the same number of interconnected conductive layers. It should also be understood that a segment may have more or less than three interconnected conductive segments. In the exemplary configuration shown in fig. 5, the individual plugs 140 are interspersed within the printed circuit board 102. Alternatively, a plurality of such plugs may be interspersed within the printed circuit board. The inclusion of a plurality of additional plugs results in the formation of a plurality of additional segments.

Fig. 6-12 illustrate various steps in a selective segment via plating process for manufacturing the printed circuit board 102 of fig. 5. Each of fig. 6-12 shows a cut-out side view of a printed circuit board with stubs according to various process steps. In fig. 6, a plug assembly 122 is formed. The plug assembly 122 includes a core structure and a plating resist layer 118 formed on a surface of the core structure. The core structure is a metal clad substrate comprising a non-conductive substrate layer 104 and a plurality of conductive layers 108 formed on two opposing surfaces. It should be understood that alternative core structures may be used that include a conductive layer on only one surface of the non-conductive layer. A plating resist resistant layer 118 (e.g., a liquid photo-sensitive plating resist) is applied over one of the conductive layers 108. It should be understood that other types of plating resist that are resistant to subsequent via wall plating steps may be used. One or more additional plug assemblies are fabricated in a similar manner. Each inner core layer is fabricated using two plug assemblies. As such, the number of plug assemblies manufactured depends on the number of inner core layers to be included in the laminate stack. In the exemplary embodiment of fig. 5, a single inner core layer is included in the laminated stack, and as such, two plug assemblies are fabricated. Optionally, where the printed circuit board is to include one or more core structures that have not yet been formed into the plurality of plug assemblies, the one or more core structures may be manufactured at this stage.

In fig. 7, a laminated stack is formed. The plug assembly 122 is laminated to another plug assembly 122' with the non-conductive layer 106 in between. The plug assembly 122 and the plug assembly 122' are oriented such that the respective plating resist resistant layers 118 of each assembly face each other, as shown in fig. 7. In the exemplary configuration shown in fig. 7, additional conductive layers 108 and intervening non-conductive layers 106 are added to the top and bottom of the stack. A single lamination step produces the laminated stack shown in fig. 7. These additional conductive layers 108 on the top and bottom of the laminate stack are etched with a pattern.

In fig. 8, holes are drilled through the laminate stack of fig. 7 to form vias 110. The formation of the via 110 exposes the plating resist 118 on the sidewalls of the via 110.

In fig. 9, a first plating resist stripping process is performed. During this first plating resist stripping process, a portion of the plating resist 118 is removed. Another portion of the plating resist 118 remains after the plating resist stripping step. The portion of the plating resist that is stripped forms a cavity 115 around the via 110 at each of these plating resist resistant layers 118.

In fig. 10, a desmear process is performed to clean the residue within the via 110. Next, an electroless plating process is performed to form a plating layer 112' on the sidewalls of the via hole 110. In certain embodiments, copper is used as the plating material. It should be understood that other plating materials may be used. Plating layer 112' forms an interconnect to each conductive layer 108. In the region of the plug 140, a plating layer 112' is formed on the plating resist 118 within the cavity 115 and the exposed plug non-conductive layer 106 between the two plating resist resistant layers 118.

In fig. 11, a second plating resist stripping process is performed. During this second plating resist stripping process, the two plating layers 112' attached to the plating resist layer 118 and another portion of the plating resist material 118 are removed, thereby further expanding these cavities 115. The plating layer 112 'deposited during the electroless plating process of fig. 10 does not deposit well onto the plating resist 118, and thus the plating resist 118 is not completely covered with the plating layer 112'. Also, the adhesion between plating layer 112 'and plating resist 118 is less strong than the adhesion between plating layer 112' and other layers exposed within the via. As such, during the plating resist stripping process, the stripping chemistry attacks the plating resist 118 at locations that lack coverage by the plating layer 112'. As the plating resist 118 dissolves, there is no support for the portion of the plating layer 112 'deposited on the plating resist 118, and this portion of the plating layer 112' is removed. The amount of the remaining plating resist 118 remains after the second plating resist stripping step.

In fig. 12, an electroplating process is performed to produce a thicker plating layer 112 on the sidewalls of the via 110. In certain embodiments, copper is used as the plating material. To perform the electroplating process, the

segments

120 and 130 are energized. However, due to the via wall plating discontinuity at the plating resist layers 118, the plating 112' attached to the plug non-conductive layer 106 between the two plating resist layers 118 is not electrically connected. Thus, the plating chemistry applied during the plating process causes the plating layer 112' to dissolve. The dissolution of this plating layer 112' relative to the plating layer 112 forms a cavity 114 that is formed in the via 110, thereby causing a via wall plating discontinuity across the entire interposer layer 140.

In certain embodiments, the plug is positioned at a location other than the middle of the laminated stack. Fig. 13 illustrates a cut-out side view of a portion of a printed circuit board according to another embodiment. The printed circuit board 202 includes a plurality of stacked layers made of a plurality of

non-conductive layers

204, 206 and a plurality of conductive layers 208 laminated to another interposer layer 240 to form a laminated stack with vias 210 having plated layers 212 in a manner similar to that previously described. The interposer layer 240 may be formed in a similar manner as the plug 140 in fig. 6-8. The resulting interposer layer 240 includes cavities 214 and 215 that form a continuous via wall plating discontinuity across the entire inner core layer 240.

Fig. 13 also demonstrates additional functionality in which the interposer layer is selectively positioned toward the "back side" of the circuit board, thereby effectively electrically isolating a selected number of conductive layers (e.g., segment 230) at the back side from segment 220 in a manner similar to backdrilling. However, with this selective segment via electroplating process, there are no multiple via stubs as with conventional backdrilling processes.

In the above embodiments, a single inner core layer is included in the laminate stack. In other embodiments, the laminate stack may include a plurality of inner core layers. Fig. 14 illustrates a cut-out side view of a portion of a printed circuit board according to yet another embodiment. The printed circuit board 302 includes two inner core layers 340 and 360. These inner core layers may be made in a similar manner to that described previously, such as by laminating two plug assemblies together. In the exemplary embodiment shown in fig. 14, the plug assembly can be manufactured with a plating resist resistant layer applied to each conductive layer of the core structure, as opposed to the single plating resist resistant layer of the plug assembly 122 of fig. 6. This plug assembly with plating resist layers on opposite sides is the basis of segment 350 shown in fig. 14. Two plugs of a type similar to plug assembly 122 may then be stacked together with the dual-sided plating-resistant resist plug assembly to form interposer layers 340 and 360. Additional layers made of multiple

non-conductive layers

304, 306 and multiple conductive layers 308 are stacked onto the interposer layers 340 and 360, and the resulting stack is laminated to form a laminated stack. The laminated stack is then drilled to form vias 310. The first plating resist stripping step, the electroless plating step, the second plating resist stripping step, and the plating step are performed in a manner similar to that described above. The resulting interposer layers 340 and 360 each include a plurality of plating resist layers 318 and

cavities

314 and 315 that form via wall plating discontinuities across the entire core layer. As this second inner core layer is added, additional sections 350 are formed.

In the above embodiment, the inner core layer is formed by laminating two plug assemblies in which the non-conductive layer is located between the respective plating resist layers of each plug assembly. Alternatively, the two plug assemblies may be laminated together without a non-conductive layer intermediate the respective plating resist resistant layers of each plug assembly. Fig. 15 shows an alternative lamination step. The laminated stack is fabricated using two plug assemblies 422 and 422 ', wherein the plating resist layer 418 of each plug assembly 422 and 422', respectively, is laminated together with the partially cleaned plug non-conductive layer at the location of the plating resist layer 118 to form the basis of the plug 440. Fig. 16 illustrates an exemplary printed circuit board 402 resulting from the lamination step of fig. 15.

It should be understood that the various structural configurations and locations of the plugs shown in the embodiments of fig. 6-16 may be interchanged depending on the particular application and requirements of the application.

The selective segmented via plating process allows for free connection of the inner layers as separate segments within the same via. The selective segment via plating process can replace backdrilling and progressive pressing methods, while achieving the same design as both processes. This saves running costs and shortens PCB processing time. The selective segment via plating process substantially eliminates plated stubs and thus improves signal transmission integrity as compared to uncontrollable stub lengths in conventional backdrilling processes. Plated stubs are conductive portions of the vias that are not connected in series with the circuit. By substantially eliminating plated stubs, signal reflection and degradation can be minimized as the signal travels along the via. The elimination of the backdrilling step also conserves unusable real estate on the printed circuit board when the physical size of the drill bit requires increased spacing of adjacent boreholes. This selective segment via plating process requires a single assembly lamination, which gives just via alignment through the entire thickness of the printed circuit board, which provides better overall layer-to-layer registration and thus more room for circuit routing, compared to the progressive lamination method. The selective segment via plating process also supports a one-time drilling step.

The present application has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of flexible printed circuits to which rigid components are attached. Many of the components shown and described in the various figures can be interchanged to achieve the results desired, and this description should be read to include such interchange as well. As such, references herein to specific embodiments and details thereof are not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the application.

Claims

1. A circuit board, comprising:

a. a lamination stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the lamination stack further comprises an inner plug layer comprising a plurality of plating resist resistant layers, the inner plug layer being stacked within an interior of the lamination stack;

b. a via formed through the laminate stack, wherein sidewalls of the via are plated with a conductive material except where the via passes through the interposer layer, thereby forming a via sidewall plating discontinuity, wherein a via sidewall defined by a surface of the non-conductive layer of the laminate stack defines a via diameter and a surface of the via sidewall plating facing into the via defines a plated via diameter that is less than the via diameter; and

c. a plurality of cavities, one for each plating resist layer, each cavity extending laterally from the longitudinal axis of the via at the same layer within the laminate stack as the respective plating resist layer, wherein each cavity is defined by cavity sidewalls comprising plating resist and by top and bottom surfaces corresponding to the layers of the laminate stack adjacently laminated to either side of the respective plating resist layer, wherein the plating resist facing surface into the via is recessed from the via sidewalls.

2. The circuit board of claim 1, wherein each of the conductive layers is patterned.

3. The circuit board of claim 1, wherein the via comprises a single bore through the entirety of the laminate stack.

4. The circuit board of claim 1, wherein the via wall plating discontinuity is aligned with the interposer layer.

5. The circuit board of claim 1, wherein the interposer layer comprises a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer, wherein the first plating resist resistant layer is coupled to a first conductive layer of the plurality of conductive layers in the laminate stack and the second plating resist resistant layer is coupled to a second conductive layer of the plurality of conductive layers in the laminate stack.

6. A circuit board, comprising:

a. a lamination stack comprising a plurality of non-conductive layers and a plurality of conductive layers, wherein the lamination stack comprises an inner plug layer comprising a plurality of plating resist resistant layers, the inner plug layer being stacked within an interior of the lamination stack;

b. a via formed through the laminate stack, wherein sidewalls of the via are plated with a conductive material except where the via passes through the interposer layer, wherein via sidewalls defined by surfaces of the non-conductive layers of the laminate stack define a via diameter and surfaces of the via sidewall plating facing into the via define a plated via diameter that is less than the via diameter; and

c. a plurality of cavities, one for each plating resist layer, each cavity extending laterally from a longitudinal axis of the via at the same layer within the laminate stack as the respective plating resist layer, wherein each cavity forms a via sidewall plating discontinuity, wherein each cavity is defined by cavity sidewalls comprising a plating resist and by top and bottom surfaces, the top and bottom surfaces correspond to layers of a laminate stack adjacently laminated to either side of a respective plating resist layer, wherein a surface of the plating resist facing into the via is recessed from the via sidewall, and wherein, the via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers that intersect the via, and the via wall plating discontinuity electrically insulates the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment.

7. The circuit board of claim 6, wherein each of the conductive layers is patterned.

8. The circuit board of claim 6, wherein the via comprises a single bore through the entirety of the laminate stack.

9. The circuit board of claim 6, wherein a first plating resist resistant layer of the plurality of plating resist resistant layers is coupled to the conductive layer of the first electrically interconnected conductive layer segment and a second plating resist resistant layer of the plurality of plating resist resistant layers is coupled to the conductive layer of the second electrically interconnected conductive layer segment.

10. The circuit board of claim 9, wherein the first plating resist layer prevents formation of a plating stub extending from the first electrically interconnected conductive layer segment.

11. The circuit board of claim 10, wherein the second plating resist layer prevents the formation of a plating stub extending from the second electrically interconnected conductive layer segment.

12. The circuit board of claim 6, comprising one or more additional interposer layers within the layer stack, wherein each additional interposer layer forms an additional via wall plating discontinuity.

13. The circuit board of claim 12, wherein each additional via wall plating discontinuity creates an additional electrical interconnect conductive layer segment.

14. The circuit board of claim 6, wherein the via wall plating discontinuity is aligned with the interposer layer.

15. The circuit board of claim 6, wherein the interposer layer comprises a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer, wherein the first plating resist resistant layer is coupled to a first conductive layer of the plurality of conductive layers in the laminate stack and the second plating resist resistant layer is coupled to a second conductive layer of the plurality of conductive layers in the laminate stack.

16. The circuit board of claim 6, further comprising a pin inserted within the via, wherein the pin is electrically coupled to each of the first and second electrical interconnect conductive layer segments to provide independent electrical connections from each of the first and second electrical interconnect conductive layer segments to the pin.

17. A method of manufacturing a circuit board, the method comprising:

a. forming a lamination stack, wherein the lamination stack comprises a plurality of non-conductive layers, a plurality of conductive layers, and an interposer layer, wherein the interposer layer comprises one or more plating resist layers;

b. forming a via through the laminate stack, wherein the via passes through the one or more plating resist resistant layers such that portions of the via wall corresponding to the one or more plating resist resistant layers comprise plating resist;

c. stripping portions of the one or more plating resist layers exposed at the via;

d. performing an electroless plating process to plate the via walls such that portions of the plating layer are formed on those portions of the via walls that include plating resist;

e. stripping those portions of the plating layer that are formed on those portions of the via wall that comprise plating resist and stripping those portions of the one or more plating resist layers to form via wall plating discontinuities on the second via wall that coincide with the one or more plating resist layers within the laminate stack; and

f. an electroplating process is performed to further electroplate the remaining portion of the plating on the via walls while maintaining the via wall plating discontinuities.

18. The method of claim 17, wherein the interposer layer comprises a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer.

19. The method of claim 18, wherein performing the electroplating process dissolves a portion of the plating on the plug non-conductive layer, thereby forming a continuous via wall plating discontinuity across the inner plug layer.

20. The method of claim 18, wherein the portions of the plating layer are stripped and the portions of the first and second plating resist layers are stripped to form the via wall plating discontinuities beginning with respective cavities extending from the via, wherein a first cavity is aligned with the first plating resist layer and a second cavity is aligned with the second plating resist layer in the laminate stack.

21. The method of claim 17, wherein stripping portions of the one or more plating resist layers forms a cavity extending from the via.

22. The method of claim 17, wherein forming the laminated stack comprises:

a. forming a first component comprising a first non-conductive layer, a first conductive layer coupled to a first surface of the first non-conductive layer, a second conductive layer coupled to a second surface of the first non-conductive layer, and a first plating resist resistant layer coupled to the second conductive layer;

b. forming a second component comprising a second non-conductive layer, a third conductive layer coupled to a first surface of the second non-conductive layer, a fourth conductive layer coupled to a second surface of the second non-conductive layer, and a second plating resist resistant layer coupled to the third conductive layer;

c. stacking the first component onto the second component such that the first plating resist resistant layer faces the second plating resist resistant layer;

d. stacking at least one additional non-conductive layer and one additional conductive layer onto the first conductive layer of the first component and onto the fourth conductive layer of the second component, thereby forming a stack; and

e. the stack is laminated to form the laminated stack.

23. The method of claim 22, wherein stacking the first component onto the second component includes positioning a non-conductive layer therebetween.

24. The method of claim 17, further comprising etching a pattern to the conductive layers in the laminate stack.

25. The method of claim 17 wherein the second via wall plating forms a plurality of electrical interconnects with a plurality of conductive layers intersecting the via, and a plurality of second via wall plating discontinuities electrically insulate the first electrical interconnect conductive layer segment from the second electrical interconnect conductive layer segment.

26. The method of claim 25, wherein performing the electroplating process comprises applying an electrical current to the first electrical interconnect conductive layer segment and to the second electrical interconnect conductive layer segment.

27. The method of claim 25, wherein the interposer layer comprises a plug non-conductive layer, a first plating resist resistant layer coupled to a first surface of the plug non-conductive layer, and a second plating resist resistant layer coupled to a second surface of the plug non-conductive layer, wherein the first plating resist resistant layer prevents formation of a plated stub extending from the first electrically interconnected conductive layer segment.

28. The method of claim 27, wherein the second plating resist layer prevents formation of a plating stub extending from the second electrically interconnected conductive layer segment.

29. The method of claim 25, wherein forming the laminate stack further comprises including one or more additional inner core layers within the laminate stack, wherein each additional inner core layer forms a plurality of additional via wall plating discontinuities.

30. The method of claim 29, wherein each additional inner core layer creates an additional electrical interconnect conductive layer segment.

31. The method of claim 17, wherein forming the via comprises drilling a single bore through the entirety of the laminate stack.