CN106027160A - Parallel optical receiver - Google Patents
Parallel optical receiver Download PDFInfo
- Publication number
- CN106027160A CN106027160A CN201610526544.0A CN201610526544A CN106027160A CN 106027160 A CN106027160 A CN 106027160A CN 201610526544 A CN201610526544 A CN 201610526544A CN 106027160 A CN106027160 A CN 106027160A
- Authority
- CN
- China
- Prior art keywords
- input
- outfan
- amplifier
- preamplifier
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
Abstract
The invention provides a parallel optical receiver. An optical detector, a pre-amplifier, a single-end/double-end interface circuit, a main amplifier, a clock recovery circuit and a data decision circuit are set; an optical signal is pre-amplified and mainly amplified; data is recovered according to a clock signal provided by the data decision circuit in combination with the clock recovery circuit; the problem that the data recovery quality is poor is solved; the clock recovery circuit is also set; an edge detector, a band-pass filter and a phase aligner structure are adopted; an accurate clock signal is provided for the data decision circuit; and thus, the data recovery quality is further improved.
Description
Technical field
The present invention relates to fiber optic communication field, particularly parallel optic-fiber receiver machine.
Background technology
Parallel optic-fiber receiver machine need to recover what the transmission of exterior light transmitter came with minimum added noise and distortion
Data entrained by light carrier, its output performance combined reaction performance of whole optical fiber telecommunications system.
The optical signal of exterior light transmitter is after fiber-optic transfer, and amplitude fading, impulse waveform also broadening, light connects
Receive it detected, amplify, shaping, regeneration, recover former data signal, but existing parallel light
In receiver, there is the problems such as circuit noise is big, circuit amplification is low, clock signal is inaccurate,
Cause data Quality of recovery poor.
Summary of the invention
The present invention provides parallel optic-fiber receiver machine, the problem solving data Quality of recovery difference.
The present invention solves the problems referred to above by the following technical programs:
Parallel optic-fiber receiver machine, including photodetector, preamplifier, single-ended-both-end interface circuit,
Main amplifier, clock recovery circuitry and data decision circuit；The input of described photodetector is through light
Fine it is connected with exterior light transmitter, the input phase of the outfan of described photodetector and preamplifier
Even；The outfan of described preamplifier is connected with the input of single-ended-both-end interface circuit；Described
Single-ended-the outfan of both-end interface circuit is connected with the input of main amplifier；Described main amplifier
No. one outfan is connected with a road input of data decision circuit, and another road of described main amplifier is defeated
Go out end to be connected with the input of clock recovery circuitry；The outfan of described clock recovery circuitry is sentenced with data
Certainly another road input of circuit is connected.
Further, described clock recovery circuitry is by marginal detector, band filter and phase alignment
Device forms；The input of described marginal detector is connected with another road outfan of main amplifier, described
The outfan of marginal detector is connected with the input of band filter；The output of described band filter
End is connected with the input of phase aligner, the outfan of described phase aligner and data decision circuitry
Another road input be connected.
Further, described preamplifier is for being total to grid preamplifier or common source across hindering preposition amplification
Device.
Further, described preamplifier is common source transimpedance preamplifier.
Further, described main amplifier is automatic gain control amplifier or limiting amplifier.
Further, described main amplifier is limiting amplifier.
Compared with prior art, have a characteristic that
1, photodetector, preamplifier, single-ended-both-end interface circuit, main amplifier, clock are extensive
Compound circuit and data decision circuit, carry out optical signal preposition amplification, main amplification, then sentenced by data
The recovering clock signals that circuit of determining combines clock recovery circuitry and provides goes out data, solves data Quality of recovery
The problem of difference；
2, clock recovery circuitry uses marginal detector, band filter and phase aligner structure,
There is provided clock signal accurately for data decision circuit, improve data Quality of recovery further.
Accompanying drawing explanation
Fig. 1 is present configuration theory diagram.
Fig. 2 is clock recovery circuitry theory diagram.
Detailed description of the invention
Below in conjunction with embodiment, the invention will be further described, but the invention is not limited in that these are real
Execute example.
Parallel optic-fiber receiver machine, including photodetector, preamplifier, single-ended-both-end interface circuit,
Main amplifier, clock recovery circuitry and data decision circuit；The input of photodetector through optical fiber with
Exterior light transmitter is connected, and the outfan of photodetector is connected with the input of preamplifier；Preposition
The outfan of amplifier is connected with the input of single-ended-both-end interface circuit；Single-ended-both-end interface circuit
Outfan be connected with the input of main amplifier；No. one outfan of main amplifier and data decision electricity
The one road input on road is connected, another road outfan of main amplifier and the input of clock recovery circuitry
It is connected；The outfan of clock recovery circuitry is connected with another road input of data decision circuit.
Photodetector is photodiode or avalanche photodide.Photodetector is for receiving
Optical signal is converted to current signal.Optical signal incides on the photosurface of photodetector, photon excitation with
Machine produces photo-generated carrier, and this noise produced by the randomness of photon excitation photo-generated carrier is existing
As referred to as quantum noise, if using avalanche photodide, then the multiplication that avalanche process causes is random
Noise is much larger than quantum noise, it is preferable that the present invention selects photodiode.
Preamplifier is grid preamplifier or common source transimpedance preamplifier altogether.The preposition amplification of grid altogether
The input impedance of device is low, it is roomy to carry, and has good time response, but does not has current gain, etc.
Effect input noise electric current is big, and input reference noise is bigger when high frequency；Common source transimpedance preamplifier
Bias current little, moreover it is possible to take into account noise and the gain of amplifier, the present invention select common source across resistance preposition
Amplifier.
Single-ended-both-end interface circuit is Single-end output due to transimpedance preamplifier, is converted into double
End, accesses in main amplifier.Single-ended-both-end interface circuit is RC low-pass network, and RC Changshu is certainly
Determining the low-frequency cut-off frequency of preamplifier, low-frequency cut-off frequency one timing, R is the biggest, and C just requires
The least, the R of the present invention uses metal-oxide-semiconductor.
Main amplifier is automatic gain control amplifier or limiting amplifier, for by preamplifier
Output signal is amplified and is maintained at certain amplitude, provides for data decision circuit and clock recovery circuitry
Satisfactory level.Main amplifier need to possess at high speed, the feature of high-gain, and bigger defeated
Enter in dynamic range, keep output level constant amplitude.Automatic gain control amplifier is accomplished that works as
When input signal amplitude changes in certain dynamic range, make defeated by being automatically adjusted the gain of amplifier
Going out signal amplitude to be kept approximately constant, i.e. when input signal is the most weak, the gain of receiver is very big, from
Dynamic gain control circuit is inoperative, and when input signal is the strongest, automatic gain control circuit is to gain
Suppress, make amplifier gain reduce.The basic structure of limiting amplifier includes a series of difference
Amplifying unit and a DC feedback loop, when the input signal amplitude of amplifier exceedes certain level
Time, amplifier enters nonlinear operation region, and output signal reaches clipping state.With automatic gain control
Amplifier amplifier processed is compared, and the amplitude limit function of limiting amplifier directly acts on each of input data
In pulse, i.e. limiting amplifier can suppress the change at a slow speed of data signal amplitude, it is also possible to suppression number
According to the very fast change of signal amplitude, and there is not automatic gain control amplifier time constant problem and go back
Having the advantage that and eliminate gain control loop, circuit design is simple, and chip area is little；External
Components and parts are less, and chip is transplanted easily.It is therefore preferred that the main amplifier of the present invention uses amplitude limit
Amplifier.
Clock recovery circuitry is made up of marginal detector, band filter and phase aligner；Described limit
It is connected along the input of detector and another road outfan of main amplifier, described marginal detector defeated
Go out end to be connected with the input of band filter；The outfan of described band filter and phase aligner
Input be connected, another road input of the outfan of described phase aligner and data decision circuitry
It is connected.Clock recovery circuitry extracts clock signal for the signal from main amplifier output, first to master
The output signal of amplifier carries out Edge check, then produces the stable letter of cycle on input data rate
Number, when data lack transition
Data decision circuit utilizes the clock signal that clock recovery circuitry provides, from the output of main amplifier
Signal recovers data signal.
The work process of the present invention is: photodetector detection optical signal, is converted into ultra-weak electronic signal,
Ultra-weak electronic signal inputs to preamplifier through single-ended-both-end interface circuit, is met main amplifier
Input range, noise is relatively low and bandwidth is bigger signal, above-mentioned signal is put by main amplifier further
After great, clock recovery circuitry therefrom recovers clock signal, and data decision circuit combines main amplifier
The clock signal that output signal and clock recovery circuitry provide, recovers identical with exterior light transmitter
Data.
Claims (6)
1. parallel optic-fiber receiver machine, it is characterised in that:
Including photodetector, preamplifier, single-ended-both-end interface circuit, main amplifier, clock
Restoring circuit and data decision circuit；
The input of described photodetector is connected with exterior light transmitter through optical fiber, described photodetector
Outfan is connected with the input of preamplifier；The outfan of described preamplifier is with single-ended-bis-
The input of end interface circuit is connected；The outfan of described single-ended-both-end interface circuit and main amplifier
Input be connected；No. one outfan of described main amplifier and a road input of data decision circuit
Being connected, another road outfan of described main amplifier is connected with the input of clock recovery circuitry；Described
The outfan of clock recovery circuitry is connected with another road input of data decision circuit.
Parallel optic-fiber receiver machine the most according to claim 1, it is characterised in that:
Described clock recovery circuitry is made up of marginal detector, band filter and phase aligner；Institute
Another road outfan of the input and main amplifier of stating marginal detector is connected, described marginal detector
Outfan be connected with the input of band filter；The outfan of described band filter and phase place pair
The input of quasi-device is connected, and the outfan of described phase aligner is defeated with another road of data decision circuitry
Enter end to be connected.
Parallel optic-fiber receiver machine the most according to claim 1, it is characterised in that: put before described
Big device is grid preamplifier or common source transimpedance preamplifier altogether.
Parallel optic-fiber receiver machine the most according to claim 3, it is characterised in that: put before described
Big device is common source transimpedance preamplifier.
Parallel optic-fiber receiver machine the most according to claim 1, it is characterised in that: described main amplification
Device is automatic gain control amplifier or limiting amplifier.
Parallel optic-fiber receiver machine the most according to claim 5, it is characterised in that: described main amplification
Device is limiting amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610526544.0A CN106027160A (en) | 2016-07-05 | 2016-07-05 | Parallel optical receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610526544.0A CN106027160A (en) | 2016-07-05 | 2016-07-05 | Parallel optical receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106027160A true CN106027160A (en) | 2016-10-12 |
Family
ID=57107380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610526544.0A Pending CN106027160A (en) | 2016-07-05 | 2016-07-05 | Parallel optical receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106027160A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198043A (en) * | 1997-03-31 | 1998-11-04 | 日本电气株式会社 | Data and clock recovery PLL circuit using windowed phase comparator |
| US20040213504A1 (en) * | 2003-04-28 | 2004-10-28 | Phyworks Limited | Integrated circuit |
| CN1767516A (en) * | 2004-10-28 | 2006-05-03 | 电子科技大学 | High-speed burst mode clock data recovery circuit |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| CN202334774U (en) * | 2011-10-10 | 2012-07-11 | 刘超 | Uncompressed digital video optical transceiver |
| CN103427830A (en) * | 2013-08-08 | 2013-12-04 | 南京邮电大学 | Semi-blind oversampling clock data recovery circuit with high locking range |
| CN103580755A (en) * | 2013-09-29 | 2014-02-12 | 中国科学院等离子体物理研究所 | Universal type high-speed data transmission device having light receiving and sending functions at same time |
| CN204272132U (en) * | 2014-12-15 | 2015-04-15 | 重庆广播电视大学 | A kind of jamproof data communication system |
| CN105306147A (en) * | 2015-10-30 | 2016-02-03 | 苏州优康通信设备有限公司 | Digital optical receiver |
-
2016
- 2016-07-05 CN CN201610526544.0A patent/CN106027160A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1198043A (en) * | 1997-03-31 | 1998-11-04 | 日本电气株式会社 | Data and clock recovery PLL circuit using windowed phase comparator |
| US20040213504A1 (en) * | 2003-04-28 | 2004-10-28 | Phyworks Limited | Integrated circuit |
| CN1767516A (en) * | 2004-10-28 | 2006-05-03 | 电子科技大学 | High-speed burst mode clock data recovery circuit |
| CN1925387A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Data clock recovery circuit |
| CN202334774U (en) * | 2011-10-10 | 2012-07-11 | 刘超 | Uncompressed digital video optical transceiver |
| CN103427830A (en) * | 2013-08-08 | 2013-12-04 | 南京邮电大学 | Semi-blind oversampling clock data recovery circuit with high locking range |
| CN103580755A (en) * | 2013-09-29 | 2014-02-12 | 中国科学院等离子体物理研究所 | Universal type high-speed data transmission device having light receiving and sending functions at same time |
| CN204272132U (en) * | 2014-12-15 | 2015-04-15 | 重庆广播电视大学 | A kind of jamproof data communication system |
| CN105306147A (en) * | 2015-10-30 | 2016-02-03 | 苏州优康通信设备有限公司 | Digital optical receiver |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6107146B2 (en) | Optical receiver circuit | |
| US8879927B2 (en) | Optical receiver based on a decision feedback equalizer | |
| EP2291709B1 (en) | High sensitivity optical receiver employing a high gain amplifier and an equalizing circuit | |
| CN105227245B (en) | A kind of reception device of the visible light communication system based on white light LEDs | |
| CN105306147A (en) | Digital optical receiver | |
| CN105547470A (en) | Self-cancellation single photon detection system | |
| CN103929139A (en) | Transimpedance pre-amplifier of photo-receiver with high-precision automatic gain control | |
| CN202974453U (en) | Bipolar-bias-voltage single photon detection device | |
| CN102833006B (en) | Optical receiver | |
| CN102004003B (en) | High time resolution low noise single photon detector based on optical pulse synchronization | |
| CN108599866A (en) | A kind of transmission rate 25Gbps high-speed light receivers | |
| CN110445551B (en) | 25Gb/s optical receiver automatic gain control module with reset function | |
| CN202713264U (en) | Circuit converting single-terminal signal into difference signal | |
| CN202550965U (en) | Avalanche photodiode detection circuit | |
| CN117097410A (en) | Single photon magnitude balance detection method and balance detection chip | |
| CN106027160A (en) | Parallel optical receiver | |
| CN107733641B (en) | High-speed high-adjustable-bandwidth quantum balance homodyne detector and control method thereof | |
| CN105162515A (en) | Balance phase-locked loop system and method with separated phase lock and data | |
| CN103001589B (en) | Photoelectric signal conversion and amplification device | |
| CN201828343U (en) | Optical-pulse synchronous single-photon detector with high time resolution and low noise | |
| CN204145419U (en) | High-speed-differential photodetector system | |
| KR20110063251A (en) | Method and apparatus for cancellation of transient voltage spike | |
| CN207200709U (en) | Digital light receiver | |
| KR101043954B1 (en) | Apparatus for discriminating optical receiver threshold using attenuator | |
| CN102624449B (en) | A kind of signal sensor and detection circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20161012 |
|
| WD01 | Invention patent application deemed withdrawn after publication |