CN106027052A - Current control delay line circuit - Google Patents
Current control delay line circuit Download PDFInfo
- Publication number
- CN106027052A CN106027052A CN201610325878.1A CN201610325878A CN106027052A CN 106027052 A CN106027052 A CN 106027052A CN 201610325878 A CN201610325878 A CN 201610325878A CN 106027052 A CN106027052 A CN 106027052A
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- data
- signal
- control signal
- output
- controlled delay
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Abstract
The invention belongs to the technical field of integrated circuits, and relates to a current control delay line circuit. The current control delay line circuit is composed of a plurality of delay modules connected in sequence, wherein the right shift output end of each delay module is connected with the right shift input end of the next delay module, and the left shift output end of each delay module is connected with the left shift input end of the last delay module; each delay module is composed of a data selector, a controlled delay unit, a latch and a data distributor; each data selector is connected with left and right input signals, and the control signal input end of the data selector is connected with an external digital control signal; each controlled delay unit is connected with an external current control signal, and the output end of the controlled delay unit is connected with the corresponding latch; the output end of each latch is connected with the data input end of the corresponding data distributor, the control signal input end of the data distributor is connected with an external digital control signal, and the data distributor outputs left and right signals. The current control delay line circuit has the beneficial effects that on the one hand, the higher sampling efficiency can be achieved, and on the other hand, the circuit is simple in structure, and the power consumption and circuit area can be very small.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of Current controlled delay line circuit.
Background technology
Portable electric appts plays the most important role in the productive life of people, and flying power is as portable electric
The important performance characteristic of subset is mainly determined by power module, and DC-DC converter is one of base component of power module, people
DC-DC converter is had higher requirement: small size, high efficiency, fast transient response.Therefore, a kind of based on ripple control
The structure of the DC-DC converter of system (Ripple-Based Control) is arisen at the historic moment.This DC-DC converter to load and
The change of power supply all has quick transient response, superior closed loop stability and periodically overcurrent turn-off function and preferably protects out
Guan Guan.As important analogue unit, inductive current sample circuit is the basis that above advantage realizes.
Inductive current sample circuit generally uses RC circuit that inductance ripple current is converted into ripple voltage, then utilizes ADC by mould
The ripple voltage signal intended is converted into digital signal.But ADC can take larger area on chip and power consumption is relatively big (common
ADC power consumption often at several mW), run counter to the principle of the high efficiency of DC-DC converter, small size.
Summary of the invention
To be solved by this invention, it is simply that for the problem that the power consumption of above-mentioned ADC and circuit area are the biggest, propose a kind of novel
The Current controlled delay line that utilizes realize low-power consumption, the analog to digital conversion circuit of little area.
The technical scheme is that a kind of Current controlled delay line circuit, described delay line is by multiple Postponement modules successively
Connect and compose, each Postponement module move to right the output next Postponement module of termination move to right input, each Postponement module
Move to left output terminate previous Postponement module move to left input；Each Postponement module is by data selector, controlled delay list
Unit, latch and data distributor are constituted；One data input pin of data selector connects and moves to right signal, and another data input
Termination moves to left signal, and control signal input termination external digital control signal, the data that outfan connects controlled delay unit respectively are defeated
Enter a data input pin of end and latch；The control signal termination foreign current control signal of controlled delay unit, controlled prolongs
Another input of the output termination latch of unit late；The time delay of described controlled delay unit and foreign current signal
Size is inversely；The data input pin of the output termination data distributor of latch, the control signal input of data distributor
Termination external digital control signal, a data output end output of data distributor moves to right signal, and another data output end is defeated
Go out to move to left signal；Described external digital control signal includes 0 and 1 two signal, when external digital control signal is 0, and number
Export according to selector and data distributor and move to left signal, when external digital control signal is 1, data selector and data distribution
Device output moves to right signal.
Beneficial effects of the present invention is, uses Current controlled delay line to realize the inductive current analog digital conversion in DC-DC circuit,
On the one hand higher sample frequency can be reached；On the other hand, circuit structure is simple, and main modular is made up of gate circuit, power consumption
Can reach the least with circuit area, defer to the principle of the high efficiency of DC-DC converter, small size.
Accompanying drawing explanation
Fig. 1 is the Current controlled delay line of the present invention and single Postponement module schematic diagram；
Fig. 2 is the Postponement module internal structure schematic diagram of the present invention；
Fig. 3 is that Current controlled delay line is to inductive current analog to digital conversion circuit schematic diagram；
Fig. 4 is inductive current analog digital conversion waveform diagram；
Fig. 5 is direction switching waveform contrast schematic diagram；A () is unlocked storage oscillogram, (b) is for adding latch postwave
Shape figure；
Fig. 6 is direction handover module Output simulation oscillogram.
Detailed description of the invention
Below in conjunction with the accompanying drawings, technical scheme is described in detail:
As it is shown in figure 1, Current controlled delay line is made up of multiple Postponement modules, each module move to right outfan FoutConnect down
One module move to right input Fin, each module move to left outfan BoutConnect previous module moves to left input Bin。DIR
When digital signal is 1, signal moves to right, and when DIR digital signal is 0, signal moves to left, electric current IbiasControl prolonging of delay cell
Late the time, Q is the output of each module.
As in figure 2 it is shown, Postponement module internal structure includes data selector MUX, data distributor DIV, controlled delay unit,
Latch module.
Described data selector MUX moves to right input signal F for selectioninOr move to left input signal Bin；When DIR is 1,
Data selector selects to move to right input signal FinExporting as data selector, when DIR is 0, data selector selects to move to left
Input signal BinExporting as data selector, gained output is defeated as of the input of Current controlled delay unit and latch
Enter.
Described data distributor DIV is for distributing to move to right output signal F by prime latch output QoutOr move to left output
Signal Bout；When DIR is 1, latch is exported Q and distributes to move to right output signal F by data distributorout, when DIR is 0
Time, latch is exported Q and distributes to move to left output signal B by data distributorout。
Described Current controlled delay unit is for producing one by electric current IbiasThe delay t controlleddelay, it is achieved the letter to delay line
The regulation and control of number flowing velocity；Time delay tdelayWith electric current IbiasBecoming approximation inverse relation, the output that this element produces is selected with data
Select the input two inputs as latch of device.
Described latch is used for the transmission to input signal or latch, it is to avoid the mistake upset caused during DIR signal switching direction；
The truth table that latch is corresponding is as shown in table 1.
Table 1 latch truth table
| S1 | S2 | Q |
| 1 | 1 | 1 |
| 0 | 0 | 0 |
| 1 | 0 | Previous Q-value |
| 0 | 1 | Previous Q-value |
The operation principle of the present invention is:
Input signal on one direction, under the control of DIR signal, is introduced inside modules, through I by each Postponement modulebiasAdjust
Produce a delay waveform after the controlled cell of control, as the output signal on same direction, utilize controlled delay unit, permissible
Reaching auto-control signal transmission rate, electric current is the biggest, and time delay is the shortest, and signal transmission rate is the fastest.
In the case of not having latch, circuit can realize moving to right normally or moving to left, but cannot realize DIR and normally cut
Change, this is because, in that time of direction switching, owing to postponing, output signal has just completed that module of switching can be by signal
Pass to next module and produce a pulse less than a time delay, but owing to direction switches, this pulse can reversely pass again
Pull over and cause upset by mistake, as shown in Fig. 5 (a).After adding above-mentioned latch in Postponement module, it becomes possible to successfully eliminate
Fall this upset by mistake, it is achieved the switching of perfect direction, as shown in Fig. 5 (b), corresponding circuit simulation oscillogram is as shown in Figure 6.
As it is shown on figure 3, by sample circuit adopt inductive current information as Current controlled delay line control signal, inductive current
Size determines the time delay of each Postponement module, and electric current is the biggest, and signal transmission rate is the fastest.Delay line high order end input signal
Being 1, low order end input signal is 0, when comparator exports high level, and delay line DIR signal is 1, and signal moves to right, Ge Jiyan
Module output late becomes 1 from 0 the most successively；When comparator is output as low level, and delay line DIR signal is 0, and signal moves to left,
Postponement modules at different levels output becomes 1 from 0 the most successively.By judging the module position of output potential change, it is right to can be achieved with
The matching of inductive current, completes analog-digital conversion function, as shown in Figure 4.
Claims (1)
1. a Current controlled delay line circuit, described delay line is sequentially connected with by multiple Postponement modules and constitutes, and each prolongs
Late module move to right the next Postponement module of output termination move to right input, each Postponement module to move to left output termination previous
Individual Postponement module move to left input；Each Postponement module is divided by data selector, controlled delay unit, latch and data
Orchestration is constituted；One data input pin of data selector connects and moves to right signal, and another data input pin connects and moves to left signal, controls
Signal input part connects external digital control signal, and outfan meets the data input pin of controlled delay unit and one of latch respectively
Data input pin；The control signal termination foreign current control signal of controlled delay unit, the output termination lock of controlled delay unit
Another input of storage；The size of the time delay of described controlled delay unit and foreign current signal is inversely；Lock
The data input pin of the output termination data distributor of storage, the control signal input termination external digital of data distributor controls letter
Number, a data output end output of data distributor moves to right signal, and the output of another data output end moves to left signal；Outside described
Portion's digital controlled signal includes 0 and 1 two signal, when external digital control signal is 0, and data selector and data distribution
Device output moves to left signal, and when external digital control signal is 1, data selector and data distributor output move to right signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610325878.1A CN106027052B (en) | 2016-05-17 | 2016-05-17 | A kind of Current controlled delay line circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610325878.1A CN106027052B (en) | 2016-05-17 | 2016-05-17 | A kind of Current controlled delay line circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106027052A true CN106027052A (en) | 2016-10-12 |
| CN106027052B CN106027052B (en) | 2019-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610325878.1A Expired - Fee Related CN106027052B (en) | 2016-05-17 | 2016-05-17 | A kind of Current controlled delay line circuit |
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Citations (6)
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|---|---|---|---|---|
| CN1499523A (en) * | 2002-10-30 | 2004-05-26 | ����ʿ�뵼������˾ | Delay locking loop having acceleration mode and controlled by register |
| CN1622467A (en) * | 2003-11-27 | 2005-06-01 | 中国科学院半导体研究所 | Phase-locked loop frequency synthesizer |
| CN101061627A (en) * | 2004-10-01 | 2007-10-24 | 亚历山大·普罗迪奇 | Numerical controller used for DC-DC switching inverter with ultra-high stable switching frequency work |
| CN101711457A (en) * | 2007-02-28 | 2010-05-19 | 爱萨有限公司 | Niversal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters |
| CN102082573A (en) * | 2009-11-30 | 2011-06-01 | Nxp股份有限公司 | Analog to digital conversion circuit and method |
| US20110285373A1 (en) * | 2008-10-20 | 2011-11-24 | Rohm Co., Ltd. | Pulse generating circuit and pulse width modulator |
-
2016
- 2016-05-17 CN CN201610325878.1A patent/CN106027052B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499523A (en) * | 2002-10-30 | 2004-05-26 | ����ʿ�뵼������˾ | Delay locking loop having acceleration mode and controlled by register |
| CN1622467A (en) * | 2003-11-27 | 2005-06-01 | 中国科学院半导体研究所 | Phase-locked loop frequency synthesizer |
| CN101061627A (en) * | 2004-10-01 | 2007-10-24 | 亚历山大·普罗迪奇 | Numerical controller used for DC-DC switching inverter with ultra-high stable switching frequency work |
| CN101711457A (en) * | 2007-02-28 | 2010-05-19 | 爱萨有限公司 | Niversal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters |
| US20110285373A1 (en) * | 2008-10-20 | 2011-11-24 | Rohm Co., Ltd. | Pulse generating circuit and pulse width modulator |
| CN102082573A (en) * | 2009-11-30 | 2011-06-01 | Nxp股份有限公司 | Analog to digital conversion circuit and method |
Non-Patent Citations (1)
| Title |
|---|
| 赵娟: "《电子设计实践指导》", 31 March 2013, 中国地质大学出版社 * |
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| CN106027052B (en) | 2019-03-29 |
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