CN1622467A - Phase-locked loop frequency synthesizer - Google Patents
Phase-locked loop frequency synthesizer Download PDFInfo
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Abstract
The phase locking loop frequency synthesizer includes one frequency discriminating phase detector, one charge pump with input connected to the output of the frequency discriminating phase detector, one low-pass filter with input connected to the output of the charge pump, one mixed digital and analog signal controlled vibrator accepting the signal from the low-pass filter and an N frequency dividing signal, and one 1/N frequency divider, and all the above said circuits constitute a phase locking loop. The mixed digital and analog signal controlled vibrator is controlled with the mixed digital and analog signal to realize fast frequency and phase locking; the digital signal determines the frequency of vibrator directly; and the analog signal controls the precision of the output frequency of the vibrator.
Description
Technical field
The present invention relates to be used for the frequency synthesis technique field of command, control, communications, and information processing unit, be meant a kind of phase-locked loop frequency synthesizer especially.
Background technology
Frequency synthesis be with a high stability and high precision standard frequency through the technology that adds, subtracts, the multiplication and division arithmetic produces a series of high-quality frequencies, the frequency generating apparatus that constitutes according to this principle is called frequency synthesizer or frequency synthesizer.Frequency synthesizer has obtained increasingly extensive application at aspects such as wireless every field such as modern communications, radar, TV, remote-control romote-sensing, electronic countermeasures and modern equipment instrument, is called " heart " of contemporary electronic systems.
The technical method of frequency synthesis has three major types types such as direct modeling frequency synthesis, phase-locked loop (PLL) frequency synthesis and Direct Digital frequency synthesis.Frequency synthesis technique has all reached comparative maturity and perfect stage from theory into action.Take all factors into consideration the requirements such as speed, precision, stability, power consumption of frequency synthesis, pll frequency synthesizer remains a kind of technical scheme of main flow, and typical PLL circuit as shown in Figure 1.It comprises the phase-locked loop of the phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO) and the 1/N program divider composition that connect successively.
Phase-locked loop frequency is synthetic on operation principle, be a process of feedback cycle repeatedly, so it having a born shortcoming, is exactly that frequency inverted speed is unhappy, be that locking time is long, this can not satisfy the demand far away in the extremely short fields such as frequency hopping communications of frequency inverted time requirement.
In modern communications was used, the frequency control word N of program divider was by predetermined rule saltus step, with synthetic different frequency in the frequency synthesizer.If produce frequency again through comparing with reference frequency behind the frequency division by phase-locked loop phase demodulation, low-pass filtering, VCO, this is a process of circulation repeatedly, needs long locking time.
In order to accelerate the speed of frequency locking, people have proposed many ways, and relatively more typical it by D/A converter, converts divider ratio N to analog control voltage, directly is added to the control end of VCO as the preset voltage method, produces the frequency of expection.Because error and loop noise, the frequency that preset voltage produces can not be very accurate, and therefore accurate locking is still regulated by analog phase-locked look.The speed and the precision problem of frequency synthesis have so just been solved preferably.But it is still having following problem on circuit is realized: the complexity, power consumption and the area that the 1) mutual interference mutually 2 of the control voltage after the control voltage after the D/A conversion and the phase-locked loop low-pass filtering) have increased circuit.
In order to address this problem, we have proposed the method for the direct predetermined frequency of digital signal.Adopted a kind of can be with the VCO of digital and analog signaling control, directly be preset to VCO with the digital signal relevant and go up the generation desired frequency with frequency control word N, with the aanalogvoltage control VCO of PLL loop filter output, carry out the locking of precise frequency simultaneously.Realize the speed of frequency synthesis and the high unity of precision, and the complexity increase of circuit seldom.
The content of invention
The objective of the invention is to, a kind of phase-locked loop frequency synthesizer is provided, its advantage is that frequency and phase locking speed are fast, precision height and good stability.
Technical solution of the present invention is:
A kind of phase-locked loop frequency synthesizer of the present invention is characterized in that it comprises:
One phase frequency detector;
One charge pump, the input of this charge pump links to each other with the output of phase frequency detector;
One low pass filter, the input of this low pass filter links to each other with the electric charge delivery side of pump;
One digital-to-analogue mixed signal control generator, this digital-to-analogue mixed signal control generator receives the signal and the divider ratio n-signal of low pass filter;
One 1/N frequency divider, this 1/N frequency divider receives the signal of digital-to-analogue mixed signal control generator; This 1/N frequency divider receives the control signal of outside divider ratio simultaneously;
Form phase-locked loop by above circuit, wherein the digital-to-analogue mixed signal control generator is controlled by numeral and analog mixed-signal, realizes fast frequency and phase locking; Wherein digital signal is directly determined the frequency of digital-to-analogue mixed signal control generator; The precision of the output frequency of analog signal control digital-to-analogue mixed signal control generator; The divider ratio n-signal of wherein controlling the 1/N frequency divider produces the digital controlled signal that digital-to-analogue mixed signal is controlled the digital-to-analogue mixed signal control generator through encoder, and digital controlled signal is used to control the digital-to-analogue mixed signal control generator.
Wherein the digital-to-analogue mixed signal control generator comprises: a digital-to-analogue hybrid voltage controlled oscillator; One encoder, this encoder carries out transcoding, coding transform with divider ratio N, the Digital Signals digital-to-analogue hybrid voltage controlled oscillator after its conversion.
Description of drawings
The present invention is described in more detail below in conjunction with drawings and Examples
Fig. 1 is typical phase-locked loop frequency synthesizer schematic diagram;
Fig. 2 is a system schematic of the present invention;
Fig. 3 is digital-to-analogue mixed signal control generator (DACO) schematic diagram;
Fig. 4 is the circuit structure diagram of digital-to-analogue mixed signal control loop oscillator;
Fig. 5 is delay unit circuit figure.
Embodiment
As shown in Figure 2; the phase-locked loop that the high-speed phase-locked loop frequency synthesizer is made up of the phase frequency detector (PFD) that connects successively, charge pump (CP), low pass filter (LPF), digital-to-analogue mixed signal control generator (Digital-Analog mixed-signal Controlled Oscillator is called for short DACO) and 1/N program divider.The input signal of high-speed phase-locked loop frequency synthesizer is the frequency control word signal N of reference frequency signal fr and program divider, and output signal is the frequency signal fo of the expectation of synthesizer generation.We have proposed the method for the direct predetermined frequency of digital signal.Adopted a kind of can be with the DACO of digital and analog signaling control; directly be preset on the digital-to-analogue mixed signal control generator with the digital signal relevant and produce desired frequency with frequency control word N; with the aanalogvoltage control DACO of PLL loop filter output, carry out the locking of precise frequency simultaneously.Wherein DACO has digital input end b0 b1 ... bn, analog input end Uc, output is frequency of oscillation fo.
Its annexation is: a phase frequency detector 10; One charge pump 20, the input of this charge pump 20 links to each other with the output of phase frequency detector 10; One low pass filter 30, the input of this low pass filter 30 links to each other with the output of charge pump 20; One digital-to-analogue mixed signal control generator 40, this digital-to-analogue mixed signal control generator 40 receives the signal and the divider ratio n-signal of low pass filter 30; One 1/N frequency divider 50, this 1/N frequency divider 50 receives the signal of digital-to-analogue mixed signal control generator 40; This 1/N frequency divider 50 receives the control signal of outside frequency division numeral simultaneously.
As shown in Figure 3, we propose a kind of VCO that can control simultaneously with digital and analog signaling is called digital-to-analogue mixed signal control generator (DACO), and it can be formed by voltage controlled oscillator and an encoder of digital and analog signaling control simultaneously by one.Its digital input end is divider ratio control word signal N, and analog input end is the output Uc of low pass filter, and its output is frequency f o.The effect of encoder is control signal b0, the b1 that control word signal N is converted into voltage controlled oscillator ... bn.Its annexation is that digital-to-analogue mixed signal control generator 40 comprises: a digital-to-analogue hybrid voltage controlled oscillator 41; One encoder 42, this encoder 42 carries out transcoding, coding transform with divider ratio N, the Digital Signals digital-to-analogue hybrid voltage controlled oscillator after its conversion.
Fig. 4 has provided the frame structure that adopts the DACO embodiment of loop oscillator form.Loop oscillator is made of odd number inverter and the digital and analog signaling that adds.Adopted 9 inverter Uc1-9 among Fig. 4, wherein 8 inverters are controlled jointly by digital signal N and analog signal Uc, are called digital-to-analogue mixed signal control lag unit.Digital signal N and analog signal Uc come the time of delay of common control lag unit, and the variation of time of delay causes the loop oscillation frequency change, thereby reach the purpose of control output frequency.For simplicity, frequency control word signal N is not encoded in this embodiment, go up the generation desired frequency but digital signal N directly is preset to VCO.The 9th is common inverter, and be changeless time of delay.
Fig. 5 is illustrated in the structure chart of the digital-to-analogue mixed signal control lag unit among the DACO embodiment.It comprises a main inverter (MN 10 and MP 10), 10 inverters, 10 n channel MOS field-effect transistors, 10 p channel MOS field-effect transistors, 10 control signal ends (Ct1, b0 b1 ... b7 and Uc) and an output out.Control signal end Ct1 remains on logic state " 1 " usually, it controls the conducting state of MN 9,9 two metal-oxide-semiconductors of MP, guarantee at b0 ... master's inverter was not in cut-off state when b7 and Uc were in logic state " 0 ", vibrated thereby each delay cell of whole loop oscillator can be connected connect to form.This moment, each delay cell time-delay was the longest, and frequency of oscillation is minimum.
The encoded device of " b0 b1 ... b7 " frequency control word signal N transforms and obtains.Control signal b0 b1 ... b7 directly is added to 8 n channel MOS field effect transistor M Ni (i=0,1,2 ... 7) upward and by 8 inverters be added to 8 p channel MOS field effect transistor M pi (i=0,1,2 ... 7) on, the He Guanlai that opens of control MOS field-effect transistor reaches the time of delay of control lag unit and the purpose of change frequency.The output frequency fo of N and DACO concerns one to one.In the process of the synthetic new frequency of frequency synthesizer, when the control word N of 1/N program divider changed, the control signal of DACO also changed simultaneously, produced needed frequency.
Main inverter is realized upset by load capacitance is discharged and recharged, and charging and discharging currents is big more, and it is fast more overturn, just time of delay short more, the loop oscillator frequency that this inverter is connected in series is just high more.8 n channel MOS field effect transistor M Ni (i=0,1,2 in circuit shown in Figure 5 ... 7) and 8 p channel MOS field effect transistor M pi (i=0,1,2 ... 7) size of control discharge and charging current respectively.According to metal-oxide-semiconductor inverter principle: the charging and discharging currents size is directly proportional with channel width-over-length ratio, as long as the channel width-over-length ratio that therefore metal-oxide-semiconductor be set increases in * 2 ratio, then reduces by * 2 ratio time of delay, and frequency is also with regard in * 2 ratio increase.The channel width-over-length ratio of 8 n (p) channel MOS tube increases by following rule: the breadth length ratio of Mn (p) i+1=2 * Mn (p) i.The control signal of metal-oxide-semiconductor is " b0 b1 ... b7 ".So just realized the 8 bit digital control of frequency, i.e. numerical control vibration.Certainly, the relation of transistorized size and frequency of oscillation is not desirable proportional relation, and this need be regulated in specific design.
Control word figure place (the b0 b1 of above-mentioned delay cell ... b7 ...) many more, the frequency accuracy of digit preset is high more.But because the restriction of device, the metal-oxide-semiconductor size can not unrestrictedly increase with * 2 ratio, and this just need consider the expansion of position from others.Wherein a kind of way is: in the delay cell of Fig. 5, increase the duplicate CMOS pipe of a pair of and b7, its control end is called b8, but such delay cell to have only half (4) in the loop oscillator of accompanying drawing 3 be such.Can imagine that if the delay when having only b8 to be high potential should be half that postpones when having only b7 for high potential, i.e. the frequency of b8 control is 2 times of frequency of b7 control.Like this, control bit has just been expanded 1.The rest may be inferred, and 2 delay cells increase a pair of and the identical CMOS pipe of b7 therein, and its control end is called b9; One increases a pair of such CMOS pipe therein, claims b10.Can realize 11 controls of frequency so altogether.
" Uc " is the aanalogvoltage control signal, i.e. the output of phase-locked loop low pass filter.Control signal " Uc " directly is added on 1 n channel MOS field effect transistor M N 8 and by 8 inverters and is added on the p channel MOS field effect transistor M P 8, thus the time of delay that the conducting degree of control MOS field-effect transistor reaches the control lag unit purpose of control frequency accurately.If the frequency that " b0 b1 ... b7 " presets is very accurate, the phase bit comparison of phase-locked loop so, low-pass filtering output are 0, and promptly Uc is 0.But the precision of digit preset is often not enough owing to the restriction of circuit, has error, and loop noise or interference simultaneously also can bring error, therefore Uc still has less output, thereby the frequency output of control DACO is revised predetermined frequency, thereby is reached accurate locking.
Obviously, this direct voltage presets, again by the frequency combining method of traditional analog phase-locked look correction, improves one's methods soon the precision height than many other.It has had digital phase-locked loop high speed and analog phase-locked look high-precision two big characteristics concurrently.In general phase-locked loop design,, require the low pass filter bandwidth to do widely in order to accelerate locking time; And, require bandwidth to do narrowly in order to improve the stability of loop; This is two conflicting requirements.Therefore and in the present invention,, can do the low pass filter bandwidth narrowly because that voltage presets is very fast, to improve stability, solved this contradiction well.From another angle, we also can regard the operation principle of this frequency synthesizer as the digital signal coarse adjustment, the process of analog signal fine tuning.When saltus step took place program divider N, N directly preset the frequency of DACO, and this is the process of a coarse adjustment, and speed is very fast; This moment, frequency was drawn near the required frequency, carried out fine tuning by analog phase-locked look again, thereby reached accurate locking, and obviously, this is faster than pure analog phase-locked look.It is again than the precision height of pure digital phase-locked loop simultaneously, and stability is also better.
Claims (2)
1. phase-locked loop frequency synthesizer is characterized in that it comprises:
One phase frequency detector;
One charge pump, the input of this charge pump links to each other with the output of phase frequency detector;
One low pass filter, the input of this low pass filter links to each other with the electric charge delivery side of pump;
One digital-to-analogue mixed signal control generator, this digital-to-analogue mixed signal control generator receives the signal and the divider ratio n-signal of low pass filter;
One 1/N frequency divider, this 1/N frequency divider receives the signal of digital-to-analogue mixed signal control generator; This 1/N frequency divider receives the control signal of outside divider ratio simultaneously;
Form phase-locked loop by above circuit, wherein the digital-to-analogue mixed signal control generator is controlled by numeral and analog mixed-signal, realizes fast frequency and phase locking; Wherein digital signal is directly determined the frequency of digital-to-analogue mixed signal control generator; The precision of the output frequency of analog signal control digital-to-analogue mixed signal control generator; The divider ratio n-signal of wherein controlling the 1/N frequency divider produces the digital controlled signal that digital-to-analogue mixed signal is controlled the digital-to-analogue mixed signal control generator through encoder, and digital controlled signal is used to control the digital-to-analogue mixed signal control generator.
2. phase-locked loop frequency synthesizer as claimed in claim 1 is characterized in that, wherein the digital-to-analogue mixed signal control generator comprises: a digital-to-analogue hybrid voltage controlled oscillator; One encoder, this encoder carries out transcoding, coding transform with divider ratio N, the Digital Signals digital-to-analogue hybrid voltage controlled oscillator after its conversion.
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| CNB2003101196497A CN1300946C (en) | 2003-11-27 | 2003-11-27 | Phase-locked loop frequency synthesizer |
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| CNB2003101196497A CN1300946C (en) | 2003-11-27 | 2003-11-27 | Phase-locked loop frequency synthesizer |
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| CN1300946C CN1300946C (en) | 2007-02-14 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373131C (en) * | 2005-11-24 | 2008-03-05 | 上海交通大学 | Phase demodulating circuit for incremeutal rotary encoder |
| CN101183870B (en) * | 2006-11-17 | 2012-03-28 | 卓联半导体有限公司 | Asynchronous phase obtaining unit with dithering |
| CN102412832A (en) * | 2010-09-22 | 2012-04-11 | 台湾积体电路制造股份有限公司 | Injection-locked frequency divider, phase locking circuit and integrated circuit |
| CN106027052A (en) * | 2016-05-17 | 2016-10-12 | 电子科技大学 | Current control delay line circuit |
| CN112166581A (en) * | 2018-05-31 | 2021-01-01 | 华为技术有限公司 | Radio frequency transmitter and signal processing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0903860A1 (en) * | 1997-09-17 | 1999-03-24 | Matsushita Electric Industrial Co., Ltd. | PLL frequency synthesizer |
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2003
- 2003-11-27 CN CNB2003101196497A patent/CN1300946C/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100373131C (en) * | 2005-11-24 | 2008-03-05 | 上海交通大学 | Phase demodulating circuit for incremeutal rotary encoder |
| CN101183870B (en) * | 2006-11-17 | 2012-03-28 | 卓联半导体有限公司 | Asynchronous phase obtaining unit with dithering |
| CN102412832A (en) * | 2010-09-22 | 2012-04-11 | 台湾积体电路制造股份有限公司 | Injection-locked frequency divider, phase locking circuit and integrated circuit |
| CN102412832B (en) * | 2010-09-22 | 2014-07-02 | 台湾积体电路制造股份有限公司 | Injection-locked frequency divider, phase locking circuit and integrated circuit |
| CN106027052A (en) * | 2016-05-17 | 2016-10-12 | 电子科技大学 | Current control delay line circuit |
| CN106027052B (en) * | 2016-05-17 | 2019-03-29 | 电子科技大学 | A kind of Current controlled delay line circuit |
| CN112166581A (en) * | 2018-05-31 | 2021-01-01 | 华为技术有限公司 | Radio frequency transmitter and signal processing method |
| CN112166581B (en) * | 2018-05-31 | 2022-04-29 | 华为技术有限公司 | Radio frequency transmitter and signal processing method |
| US11563452B2 (en) | 2018-05-31 | 2023-01-24 | Huawei Technologies Co., Ltd. | Radio frequency transmitter and signal processing method |
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| CN1300946C (en) | 2007-02-14 |
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