CN106026989B - The Continuous time functions signal generating circuit of Digital Signals - Google Patents

The Continuous time functions signal generating circuit of Digital Signals Download PDF

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Publication number
CN106026989B
CN106026989B CN201610429524.1A CN201610429524A CN106026989B CN 106026989 B CN106026989 B CN 106026989B CN 201610429524 A CN201610429524 A CN 201610429524A CN 106026989 B CN106026989 B CN 106026989B
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tube
drain electrode
port
connect
nmos tube
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CN106026989A (en
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辛晓宁
赵豪
范超
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Shenyang University of Technology
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Shenyang University of Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)

Abstract

A kind of Continuous time functions signal generating circuit of Digital Signals, the circuit include: that triangular wave generates sub-circuit, and reference voltage generates and switching sub-circuit, waveform convertion sub-circuit and controller sub-circuit.The problems of at present, the present invention is that a kind of frequency and waveform all can be by the Continuous time functions signal generating circuits of Digital Signals to its very good solution.

Description

The Continuous time functions signal generating circuit of Digital Signals
Technical field: the present invention relates to integrated circuit fields, in particular to by the Continuous time functions of Digital Signals Signal generating circuit.
Background technique: in IC design problem, to generate waveform and frequency all can be by the company of Digital Signals Continuous function of time signal be it is relatively difficult, the prior art usually requires higher clock frequency and more complex circuit, causes System power dissipation is very high and chip occupying area is larger.
Summary of the invention:
Goal of the invention: the present invention provides a kind of Continuous time functions signal generating circuit of Digital Signals, purpose Be solve it is the problems of previous.
Technical solution:
A kind of Continuous time functions signal generating circuit of Digital Signals, in a first aspect, the circuit includes:
Triangular wave generates sub-circuit, and reference voltage generates and switching sub-circuit, waveform convertion sub-circuit and controller electricity Road.
Wherein, output required for described " waveform convertion sub-circuit " is generated according to the scanning voltage and reference voltage of input Signal waveform.
" the triangular wave generation sub-circuit " is for generating an output voltage in two particular voltage level V1And V2Between line Property variation triangle wave voltage signal, while generating the status signal of an instruction triangle wave voltage change direction.It is described " triangular wave generation sub-circuit " is connected by the triangle wave voltage signal with " the waveform convertion sub-circuit ", is become for waveform It changes sub-circuit and scanning voltage is provided." the triangular wave generation sub-circuit " passes through status signal and " reference voltage generation Circuit " is connected, for switching the output reference voltage of " the reference voltage generation sub-circuit ".
" the reference voltage generation sub-circuit " is for generating one group of reference voltage." the reference voltage generation sub-circuit " It is connect by the reference voltage of output with " the waveform convertion sub-circuit ", for controlling signal output waveform.
" the controller sub-circuit " is according to the status signal of external input signal and " the triangular wave generation sub-circuit " Generate the enable signal of " triangular wave generation sub-circuit " and " the waveform convertion sub-circuit " work described in control, for controlling State the slop control signal of " triangular wave generation sub-circuit " output voltage rise time and fall time and for controlling " the ginseng Examine voltage generate sub-circuit " output reference voltage switching signal.
With reference to first aspect, in the first possible implementation, the waveform convertion sub-circuit includes that an IV turns Change circuit and at least one GS1 type current unit circuit.The structure feature of the GS1 type current unit circuit is that have 7 ends Mouthful, it is respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2, operating current control terminal VB, electric current Output end IOAnd working power anode V+ and working power negative terminal V-.
The GS1 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is approximately
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined Fixed, k is the constant determined by transistor size in circuit.
In the first possible implementation of the waveform convertion sub-circuit, all GS1 type current unit circuits VIEnd links together, and the triangle wave voltage signal for generating sub-circuit with the triangular wave is connected.All GS1 type electric current lists The I of first circuitOEnd links together, and forms resultant current signal IOA, connect IV conversion circuit.The V of all GS1 type unitsS1End, VS2End and VBEnd generates sub-circuit with the reference voltage respectively and is connected.The end V+ of all GS1 type units connects working power The end V- of anode, all GS1 type units connects working power negative terminal.
In the first possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the second possible implementation, the waveform convertion sub-circuit includes that an IV turns Change sub-circuit, a current transformation sub-circuit and at least one GS2 type current unit circuit.The GS2 type current unit circuit Structure feature be have 7 ports, be respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2、 Operating current control terminal VB, current output terminal IOAnd working power anode V+ and working power negative terminal V-.
In the waveform convertion sub-circuit, the V of all GS2 type current unit circuitsIEnd links together, and with it is described The triangle wave voltage signal that triangular wave generates sub-circuit is connected.The I of all GS2 type current unit circuitsOEnd links together, Form resultant current IOS, and connect current transformation sub-circuit.The V of all GS2 type unitsS1End, VS2End and VBEnd respectively with it is described Reference voltage generates and switching sub-circuit is connected.The end V+ of all GS2 type units connects working power anode, all GS2 types The end V- of unit connects working power negative terminal.
The GS2 type element circuit is from IOPort absorbs electric current, absorbs electric current IOWith ViThe relationship of variation is approximately
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined Fixed, k is the constant determined by transistor size in circuit.
In the second possible implementation, the current transformation sub-circuit absorbs electric current I for that will synthesizeOSIt is converted to Output electric current I proportional theretoOAAnd it is connected to IV conversion circuit.
In second of possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the third possible implementation, the waveform convertion sub-circuit includes that an IV turns Change circuit and at least one GS3 type current unit circuit.The structure feature of the GS3 type current unit circuit is that have 7 ends Mouthful, it is respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2, operating current control terminal VB, electric current Output end IOAnd working power anode V+ and working power negative terminal V-.
The GS3 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is approximately
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined It is fixed, k1And k2It is the constant determined by transistor size in circuit.
In the third possible implementation of the waveform convertion sub-circuit, all GS3 type current unit circuits VIEnd links together, and the triangle wave voltage signal for generating sub-circuit with the triangular wave is connected.All GS3 type electric current lists The I of first circuitOEnd links together, and forms resultant current signal IOA, connect IV conversion circuit.The V of all GS3 type unitsS1End, VS2End and VBEnd generates respectively and is switched with the reference voltage sub-circuit and is connected.The end V+ of all GS3 type units connects work Make power positive end, the end V- of all GS3 type units connects working power negative terminal.
In the third possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the fourth possible implementation, the waveform convertion sub-circuit includes that an IV turns Change sub-circuit, a current transformation sub-circuit and at least one GS4 type current unit circuit.The GS4 type current unit circuit Structure feature be have 7 ports, be respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2、 Operating current control terminal VB, current output terminal IOAnd working power anode V+ and working power negative terminal V-.
In the waveform convertion sub-circuit, the V of all GS4 type current unit circuitsIEnd links together, and with it is described The triangle wave voltage signal that triangular wave generates sub-circuit is connected.The I of all GS4 type current unit circuitsOEnd links together, Form resultant current IOS, and connect current transformation sub-circuit.The V of all GS4 type unitsS1End, VS2End and VBEnd respectively with it is described Reference voltage generates and switching sub-circuit is connected.The end V+ of all GS4 type units connects working power anode, all GS4 types The end V- of unit connects working power negative terminal.
The GS4 type element circuit is from IOPort absorbs electric current, absorbs electric current IOWith ViThe relationship of variation is seemingly
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined It is fixed, k1And k2It is the constant determined by transistor size in circuit.
In the fourth possible implementation, the current transformation sub-circuit absorbs electric current I for that will synthesizeOSIt is converted to Output electric current I proportional theretoOAAnd it is connected to IV conversion circuit.
In the 4th kind of possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
The possible implementation of with reference to first aspect the first, a kind of possible implementation of the GS1 type unit To be realized using 6 NMOS tubes and 4 PMOS tube, specific connection relationship are as follows: first NMOS tube N1Drain electrode connect the port V+, N1Grid connect VIPort, N1Source electrode connect second NMOS tube N2Source electrode and third NMOS tube N3Drain electrode, N1's Body connects the port V-.Second NMOS tube N2Drain electrode connect P1Drain electrode, P1Grid and P2Grid, N2Grid connection VS1Port, N2Source electrode connect N1Source electrode and N3Drain electrode, N2Body connect the port V-.Third NMOS tube N3Drain electrode connect Meet N1Source electrode and N2Source electrode, N3Grid connect VBPort, N3Source electrode the port V- is connected with body.4th NMOS tube N4's The 4th PMOS tube P of drain electrode connection4Drain electrode, P4Grid and P3Grid, N4Grid connect VIPort, N4Source electrode connection 5th NMOS tube N5Source electrode and the 6th NMOS tube N6Drain electrode, N4Body connect the port V-.5th NMOS tube N5Leakage Pole connects the port V+, N5Grid connect VS2Port, N5Source electrode connect N4Source electrode and the 6th NMOS tube N6Drain electrode, N5 Body connect the port V-.6th NMOS tube N6Drain electrode connect N4Source electrode and N5Source electrode, N6Grid connect VBPort, N6 Source electrode and N6Body all connect the port V-.First PMOS tube P1Drain electrode and P1Grid link together and connect N2's Drain electrode and second PMOS tube P2Grid, P1Source electrode and P1Body all connect the port V+.Second PMOS tube P2Drain electrode connect Meet I/O port, P2Grid connect P1Grid, P1Drain electrode and N2Drain electrode, P2Source electrode and body all connect the port V+.Third A PMOS tube P3Drain electrode connect I/O port, P3Grid connect the 4th PMOS tube P4Grid, P4Drain electrode and N4Drain electrode, P3Source electrode and body all connect the port V+.4th PMOS tube P4Drain and gate connect third metal-oxide-semiconductor P3The N of grid4's Drain electrode, P4Source electrode and P4Body all connect the port V+.
The possible implementation of second with reference to first aspect, a kind of possible implementation of the GS2 type unit To be realized using 6 PMOS tube and 4 NMOS tubes, specific connection relationship are as follows: first PMOS tube P1Drain electrode and the port V- connect It connects, P1Grid and VIPort connection, P1Source electrode and second PMOS tube P2Source electrode and third PMOS tube P3Drain electrode connect It connects, P1Body connect with the port V+.Second PMOS tube P2Drain electrode and first NMOS tube N1Drain electrode, N1Grid and Two NMOS tube N2Grid connection, P2Grid and VS1Port connection, P2Source electrode and P1Source electrode, P3Drain electrode connection, P2 Body connect with the port V+.Third PMOS tube P3Drain electrode and first PMOS tube P1Source electrode and second PMOS tube P2's Source electrode connection, P3Grid and VBPort connection, P3Drain electrode and body connect with the port V+.4th PMOS tube P4Drain electrode with Third NMOS tube N3Grid, the 4th NMOS tube N4Grid and N4Drain electrode connection, P4Grid and VIPort connection, P4 Source electrode and the 5th PMOS tube P5Source electrode and the 6th PMOS tube P6Drain electrode connection, P4Body connect with the port V+.5th A PMOS tube P5Drain electrode connect with the port V-, P5Grid and VS2Port connection, P5Source electrode and P4Source electrode and the 6th The drain electrode of PMOS tube connects, P5Body connect with the port V+.First NMOS tube N1Drain electrode links together with grid and with second A PMOS tube P2Drain electrode and second NMOS tube N2Grid connection, N1Source electrode the port V- is connected with body.Second NMOS tube N2Drain electrode and IOPort connection, N2Grid and N1Grid, N1Drain electrode and P2Drain electrode connection, N2Source electrode connected with body The port V-.Third NMOS tube N3Drain electrode connect IOPort, N3Grid and the 4th NMOS tube N4Grid, N4Drain electrode with And P4Drain electrode connection, N3Source electrode the port V- is connected with body.4th NMOS tube N4Drain electrode and grid link together and with N3Grid and P4Drain electrode connection, N4Source electrode the port V- is connected with body.
The third possible implementation with reference to first aspect, a kind of possible implementation of the GS3 type unit To be realized using 6 NMOS tubes and 4 PMOS tube, specific connection relationship are as follows: first NMOS tube N1Drain electrode connect the port V+, N1Grid connect VIPort, N1Source electrode connect second NMOS tube N2Source electrode and third NMOS tube N3Drain electrode, N1's Body connects the port V-.Second NMOS tube N2Drain electrode connect P1Drain electrode, P1Grid and P2Grid, N2Grid connection VS1Port, N2Source electrode connect N1Source electrode and N3Drain electrode, N2Body connect the port V-.Third NMOS tube N3Drain electrode connect Meet N1Source electrode and N2Source electrode, N3Grid connect VBPort, N3Source electrode the port V- is connected with body.4th NMOS tube N4's The 4th PMOS tube P of drain electrode connection4Drain electrode, P4Grid and P3Grid, N4Grid connect VIPort, N4Source electrode connection 5th NMOS tube N5Source electrode and the 6th NMOS tube N6Drain electrode, N4Body connect the port V-.5th NMOS tube N5Leakage Pole connects the port V+, N5Grid connect VS2Port, N5Source electrode connect N4Source electrode and the 6th NMOS tube N6Drain electrode, N5 Body connect the port V-.6th NMOS tube N6Drain electrode connect N4Source electrode and N5Source electrode, N6Grid connect VBPort, N6 Source electrode and N6Body all connect the port V-.First PMOS tube P1Drain electrode and P1Grid link together and connect N2's Drain electrode and second PMOS tube P2Grid, P1Source electrode and P1Body all connect the port V+.Second PMOS tube P2Drain electrode connect Meet third metal-oxide-semiconductor P3Source electrode, P2Grid connect P1Grid, P1Drain electrode and N2Drain electrode, P2Source electrode and body all connect Connect the port V+.Third PMOS tube P3Drain electrode connect I/O port, P3Grid connect the 4th PMOS tube P4Grid, P4's Drain electrode and N4Drain electrode, P3Source electrode connect P2Drain electrode, P3Body all connect the port V+.4th PMOS tube P4Drain electrode and grid Pole connects third metal-oxide-semiconductor P3The N of grid4Drain electrode, P4Source electrode and P4Body all connect the port V+.
The 4th kind of possible implementation with reference to first aspect, a kind of possible implementation of the GS4 type unit To be realized using 6 PMOS tube and 4 NMOS tubes, specific connection relationship are as follows: first PMOS tube P1Drain electrode and the port V- connect It connects, P1Grid and VIPort connection, P1Source electrode and second PMOS tube P2Source electrode and third PMOS tube P3Drain electrode connect It connects, P1Body connect with the port V+.Second PMOS tube P2Drain electrode and first NMOS tube N1Drain electrode, N1Grid and Two NMOS tube N2Grid connection, P2Grid and VS1Port connection, P2Source electrode and P1Source electrode, P3Drain electrode connection, P2 Body connect with the port V+.Third PMOS tube P3Drain electrode and first PMOS tube P1Source electrode and second PMOS tube P2's Source electrode connection, P3Grid and VBPort connection, P3Drain electrode and body connect with the port V+.4th PMOS tube P4Drain electrode with 4th NMOS tube N4Grid, third NMOS tube N3Grid and N3Drain electrode connection, P4Grid and VIPort connection, P4 Source electrode and the 5th PMOS tube P5Source electrode and the 6th PMOS tube P6Drain electrode connection, P4Body connect with the port V+.5th A PMOS tube P5Drain electrode connect with the port V-, P5Grid and VS2Port connection, P5Source electrode and P4Source electrode and the 6th The drain electrode of PMOS tube connects, P5Body connect with the port V+.First NMOS tube N1Drain electrode links together with grid and with second A PMOS tube P2Drain electrode and second NMOS tube N2Grid connection, N1Source electrode the port V- is connected with body.Second NMOS tube N2Drain electrode and IOPort connection, N2Grid and N1Grid, N1Drain electrode and P2Drain electrode connection, N2Source electrode and the 4th NMOS tube N4Drain electrode connection, N2Body connect the port V-.Third NMOS tube N3Drain electrode and grid link together and and N4 Grid and P4Drain electrode connection, N3Source electrode the port V- is connected with body.4th NMOS tube N4Drain electrode and N2Source electrode connect It connects, N4Grid and third NMOS tube N3Grid, N3Drain electrode and P4Drain electrode connection, N4Source electrode the end V- is connected with body Mouthful.
Advantage and effect: the invention patent provides a kind of Continuous time functions signal generating circuit of Digital Signals, The problems of at present, the present invention is that a kind of frequency and waveform all can be by the continuous of Digital Signals to its very good solution Function of time signal generating circuit.
Detailed description of the invention:
The functional block diagram of the Continuous time functions signal generating circuit of Digital Signals described in Fig. 1.
The first implementation of waveform synthetic circuit described in Fig. 2.
Second of implementation of waveform synthetic circuit described in Fig. 3.
The third implementation of waveform synthetic circuit described in Fig. 4.
4th kind of implementation of waveform synthetic circuit described in Fig. 5.
A kind of specific implementation of GS1 type element circuit described in Fig. 6.
A kind of specific implementation of GS2 type element circuit described in Fig. 7.
A kind of specific implementation of GS3 type element circuit described in Fig. 8.
A kind of specific implementation of GS4 type element circuit described in Fig. 9.
The specific embodiment of waveform convertion circuit in a kind of embodiment Figure 10 of the invention.
Reference voltage in a kind of embodiment Figure 11 of the invention generates the specific embodiment of sub-circuit.
Specific embodiment: following further describes the present invention with reference to the drawings:
As shown, the present invention provides a kind of Continuous time functions signal generating circuit of Digital Signals, first party Face, the circuit include:
Triangular wave generates sub-circuit, and reference voltage generates and switching sub-circuit, waveform convertion sub-circuit and controller electricity Road.
Wherein, output required for described " waveform convertion sub-circuit " is generated according to the scanning voltage and reference voltage of input Signal waveform.
" the triangular wave generation sub-circuit " is for generating an output voltage in two particular voltage level V1And V2Between line Property variation triangle wave voltage signal, while generating the status signal of an instruction triangle wave voltage change direction.It is described " triangular wave generation sub-circuit " is connected by the triangle wave voltage signal with " the waveform convertion sub-circuit ", is become for waveform It changes sub-circuit and scanning voltage is provided." the triangular wave generation sub-circuit " passes through status signal and " reference voltage generation Circuit " is connected, for switching the output reference voltage of " the reference voltage generation sub-circuit ".
" the reference voltage generation sub-circuit " is for generating one group of reference voltage." the reference voltage generation sub-circuit " It is connect by the reference voltage of output with " the waveform convertion sub-circuit ", for controlling signal output waveform.
" the controller sub-circuit " is according to the status signal of external input signal and " the triangular wave generation sub-circuit " Generate the enable signal of " triangular wave generation sub-circuit " and " the waveform convertion sub-circuit " work described in control, for controlling State the slop control signal of " triangular wave generation sub-circuit " output voltage rise time and fall time and for controlling " the ginseng Examine voltage generate sub-circuit " output reference voltage switching signal.
With reference to first aspect, in the first possible implementation, the waveform convertion sub-circuit includes that an IV turns Change circuit and at least one GS1 type current unit circuit.The structure feature of the GS1 type current unit circuit is that have 7 ends Mouthful, it is respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2, operating current control terminal VB, electric current Output end IOAnd working power anode V+ and working power negative terminal V-.
The GS1 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is approximately
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined Fixed, k is the constant determined by transistor size in circuit.
In the first possible implementation of the waveform convertion sub-circuit, all GS1 type current unit circuits VIEnd links together, and the triangle wave voltage signal for generating sub-circuit with the triangular wave is connected.All GS1 type electric current lists The I of first circuitOEnd links together, and forms resultant current signal IOA, connect IV conversion circuit.The V of all GS1 type unitsS1End, VS2End and VBEnd generates sub-circuit with the reference voltage respectively and is connected.The end V+ of all GS1 type units connects working power The end V- of anode, all GS1 type units connects working power negative terminal.
In the first possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the second possible implementation, the waveform convertion sub-circuit includes that an IV turns Change sub-circuit, a current transformation sub-circuit and at least one GS2 type current unit circuit.The GS2 type current unit circuit Structure feature be have 7 ports, be respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2、 Operating current control terminal VB, current output terminal IOAnd working power anode V+ and working power negative terminal V-.
In the waveform convertion sub-circuit, the V of all GS2 type current unit circuitsIEnd links together, and with it is described The triangle wave voltage signal that triangular wave generates sub-circuit is connected.The I of all GS2 type current unit circuitsOEnd links together, Form resultant current IOS, and connect current transformation sub-circuit.The V of all GS2 type unitsS1End, VS2End and VBEnd respectively with it is described Reference voltage generates and switching sub-circuit is connected.The end V+ of all GS2 type units connects working power anode, all GS2 types The end V- of unit connects working power negative terminal.
The GS2 type element circuit is from IOPort absorbs electric current, absorbs electric current IOWith ViThe relationship of variation is approximately
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined Fixed, k is the constant determined by transistor size in circuit.
In the second possible implementation, the current transformation sub-circuit absorbs electric current I for that will synthesizeOSIt is converted to Output electric current I proportional theretoOAAnd it is connected to IV conversion circuit.
In second of possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the third possible implementation, the waveform convertion sub-circuit includes that an IV turns Change circuit and at least one GS3 type current unit circuit.The structure feature of the GS3 type current unit circuit is that have 7 ends Mouthful, it is respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2, operating current control terminal VB, electric current Output end IOAnd working power anode V+ and working power negative terminal V-.
The GS3 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is approximately
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined It is fixed, k1And k2It is the constant determined by transistor size in circuit.
In the third possible implementation of the waveform convertion sub-circuit, all GS3 type current unit circuits VIEnd links together, and the triangle wave voltage signal for generating sub-circuit with the triangular wave is connected.All GS3 type electric current lists The I of first circuitOEnd links together, and forms resultant current signal IOA, connect IV conversion circuit.The V of all GS3 type unitsS1End, VS2End and VBEnd generates respectively and is switched with the reference voltage sub-circuit and is connected.The end V+ of all GS3 type units connects work Make power positive end, the end V- of all GS3 type units connects working power negative terminal.
In the third possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
With reference to first aspect, in the fourth possible implementation, the waveform convertion sub-circuit includes that an IV turns Change sub-circuit, a current transformation sub-circuit and at least one GS4 type current unit circuit.The GS4 type current unit circuit Structure feature be have 7 ports, be respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2、 Operating current control terminal VB, current output terminal IOAnd working power anode V+ and working power negative terminal V-.
In the waveform convertion sub-circuit, the V of all GS4 type current unit circuitsIEnd links together, and with it is described The triangle wave voltage signal that triangular wave generates sub-circuit is connected.The I of all GS4 type current unit circuitsOEnd links together, Form resultant current IOS, and connect current transformation sub-circuit.The V of all GS4 type unitsS1End, VS2End and VBEnd respectively with it is described Reference voltage generates and switching sub-circuit is connected.The end V+ of all GS4 type units connects working power anode, all GS4 types The end V- of unit connects working power negative terminal.
The GS4 type element circuit is from IOPort absorbs electric current, absorbs electric current IOWith ViThe relationship of variation is seemingly
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage at end is determined It is fixed, k1And k2It is the constant determined by transistor size in circuit.
In the fourth possible implementation, the current transformation sub-circuit absorbs electric current I for that will synthesizeOSIt is converted to Output electric current I proportional theretoOAAnd it is connected to IV conversion circuit.
In the 4th kind of possible implementation of the waveform convertion sub-circuit, the IV conversion sub-circuit is for amplifying The resultant current I of all current unit circuitsOA, and realize the conversion of current signal to voltage signal.
The possible implementation of with reference to first aspect the first, a kind of possible implementation of the GS1 type unit To be realized using 6 NMOS tubes and 4 PMOS tube, specific connection relationship are as follows: first NMOS tube N1Drain electrode connect the port V+, N1Grid connect VIPort, N1Source electrode connect second NMOS tube N2Source electrode and third NMOS tube N3Drain electrode, N1's Body connects the port V-.Second NMOS tube N2Drain electrode connect P1Drain electrode, P1Grid and P2Grid, N2Grid connection VS1Port, N2Source electrode connect N1Source electrode and N3Drain electrode, N2Body connect the port V-.Third NMOS tube N3Drain electrode connect Meet N1Source electrode and N2Source electrode, N3Grid connect VBPort, N3Source electrode the port V- is connected with body.4th NMOS tube N4's The 4th PMOS tube P of drain electrode connection4Drain electrode, P4Grid and P3Grid, N4Grid connect VIPort, N4Source electrode connection 5th NMOS tube N5Source electrode and the 6th NMOS tube N6Drain electrode, N4Body connect the port V-.5th NMOS tube N5Leakage Pole connects the port V+, N5Grid connect VS2Port, N5Source electrode connect N4Source electrode and the 6th NMOS tube N6Drain electrode, N5 Body connect the port V-.6th NMOS tube N6Drain electrode connect N4Source electrode and N5Source electrode, N6Grid connect VBPort, N6 Source electrode and N6Body all connect the port V-.First PMOS tube P1Drain electrode and P1Grid link together and connect N2's Drain electrode and second PMOS tube P2Grid, P1Source electrode and P1Body all connect the port V+.Second PMOS tube P2Drain electrode connect Meet I/O port, P2Grid connect P1Grid, P1Drain electrode and N2Drain electrode, P2Source electrode and body all connect the port V+.Third A PMOS tube P3Drain electrode connect I/O port, P3Grid connect the 4th PMOS tube P4Grid, P4Drain electrode and N4Drain electrode, P3Source electrode and body all connect the port V+.4th PMOS tube P4Drain and gate connect third metal-oxide-semiconductor P3The N of grid4's Drain electrode, P4Source electrode and P4Body all connect the port V+.
The possible implementation of second with reference to first aspect, a kind of possible implementation of the GS2 type unit To be realized using 6 PMOS tube and 4 NMOS tubes, specific connection relationship are as follows: first PMOS tube P1Drain electrode and the port V- connect It connects, P1Grid and VIPort connection, P1Source electrode and second PMOS tube P2Source electrode and third PMOS tube P3Drain electrode connect It connects, P1Body connect with the port V+.Second PMOS tube P2Drain electrode and first NMOS tube N1Drain electrode, N1Grid and Two NMOS tube N2Grid connection, P2Grid and VS1Port connection, P2Source electrode and P1Source electrode, P3Drain electrode connection, P2 Body connect with the port V+.Third PMOS tube P3Drain electrode and first PMOS tube P1Source electrode and second PMOS tube P2's Source electrode connection, P3Grid and VBPort connection, P3Drain electrode and body connect with the port V+.4th PMOS tube P4Drain electrode with Third NMOS tube N3Grid, the 4th NMOS tube N4Grid and N4Drain electrode connection, P4Grid and VIPort connection, P4 Source electrode and the 5th PMOS tube P5Source electrode and the 6th PMOS tube P6Drain electrode connection, P4Body connect with the port V+.5th A PMOS tube P5Drain electrode connect with the port V-, P5Grid and VS2Port connection, P5Source electrode and P4Source electrode and the 6th The drain electrode of PMOS tube connects, P5Body connect with the port V+.First NMOS tube N1Drain electrode links together with grid and with second A PMOS tube P2Drain electrode and second NMOS tube N2Grid connection, N1Source electrode the port V- is connected with body.Second NMOS tube N2Drain electrode and IOPort connection, N2Grid and N1Grid, N1Drain electrode and P2Drain electrode connection, N2Source electrode connected with body The port V-.Third NMOS tube N3Drain electrode connect IOPort, N3Grid and the 4th NMOS tube N4Grid, N4Drain electrode with And P4Drain electrode connection, N3Source electrode the port V- is connected with body.4th NMOS tube N4Drain electrode and grid link together and with N3Grid and P4Drain electrode connection, N4Source electrode the port V- is connected with body.
The third possible implementation with reference to first aspect, a kind of possible implementation of the GS3 type unit To be realized using 6 NMOS tubes and 4 PMOS tube, specific connection relationship are as follows: first NMOS tube N1Drain electrode connect the port V+, N1Grid connect VIPort, N1Source electrode connect second NMOS tube N2Source electrode and third NMOS tube N3Drain electrode, N1's Body connects the port V-.Second NMOS tube N2Drain electrode connect P1Drain electrode, P1Grid and P2Grid, N2Grid connection VS1Port, N2Source electrode connect N1Source electrode and N3Drain electrode, N2Body connect the port V-.Third NMOS tube N3Drain electrode connect Meet N1Source electrode and N2Source electrode, N3Grid connect VBPort, N3Source electrode the port V- is connected with body.4th NMOS tube N4's The 4th PMOS tube P of drain electrode connection4Drain electrode, P4Grid and P3Grid, N4Grid connect VIPort, N4Source electrode connection 5th NMOS tube N5Source electrode and the 6th NMOS tube N6Drain electrode, N4Body connect the port V-.5th NMOS tube N5Leakage Pole connects the port V+, N5Grid connect VS2Port, N5Source electrode connect N4Source electrode and the 6th NMOS tube N6Drain electrode, N5 Body connect the port V-.6th NMOS tube N6Drain electrode connect N4Source electrode and N5Source electrode, N6Grid connect VBPort, N6 Source electrode and N6Body all connect the port V-.First PMOS tube P1Drain electrode and P1Grid link together and connect N2's Drain electrode and second PMOS tube P2Grid, P1Source electrode and P1Body all connect the port V+.Second PMOS tube P2Drain electrode connect Meet third metal-oxide-semiconductor P3Source electrode, P2Grid connect P1Grid, P1Drain electrode and N2Drain electrode, P2Source electrode and body all connect Connect the port V+.Third PMOS tube P3Drain electrode connect I/O port, P3Grid connect the 4th PMOS tube P4Grid, P4's Drain electrode and N4Drain electrode, P3Source electrode connect P2Drain electrode, P3Body all connect the port V+.4th PMOS tube P4Drain electrode and grid Pole connects third metal-oxide-semiconductor P3The N of grid4Drain electrode, P4Source electrode and P4Body all connect the port V+.
The 4th kind of possible implementation with reference to first aspect, a kind of possible implementation of the GS4 type unit To be realized using 6 PMOS tube and 4 NMOS tubes, specific connection relationship are as follows: first PMOS tube P1Drain electrode and the port V- connect It connects, P1Grid and VIPort connection, P1Source electrode and second PMOS tube P2Source electrode and third PMOS tube P3Drain electrode connect It connects, P1Body connect with the port V+.Second PMOS tube P2Drain electrode and first NMOS tube N1Drain electrode, N1Grid and Two NMOS tube N2Grid connection, P2Grid and VS1Port connection, P2Source electrode and P1Source electrode, P3Drain electrode connection, P2 Body connect with the port V+.Third PMOS tube P3Drain electrode and first PMOS tube P1Source electrode and second PMOS tube P2's Source electrode connection, P3Grid and VBPort connection, P3Drain electrode and body connect with the port V+.4th PMOS tube P4Drain electrode with 4th NMOS tube N4Grid, third NMOS tube N3Grid and N3Drain electrode connection, P4Grid and VIPort connection, P4 Source electrode and the 5th PMOS tube P5Source electrode and the 6th PMOS tube P6Drain electrode connection, P4Body connect with the port V+.5th A PMOS tube P5Drain electrode connect with the port V-, P5Grid and VS2Port connection, P5Source electrode and P4Source electrode and the 6th The drain electrode of PMOS tube connects, P5Body connect with the port V+.First NMOS tube N1Drain electrode links together with grid and with second A PMOS tube P2Drain electrode and second NMOS tube N2Grid connection, N1Source electrode the port V- is connected with body.Second NMOS tube N2Drain electrode and IOPort connection, N2Grid and N1Grid, N1Drain electrode and P2Drain electrode connection, N2Source electrode and the 4th NMOS tube N4Drain electrode connection, N2Body connect the port V-.Third NMOS tube N3Drain electrode and grid link together and and N4 Grid and P4Drain electrode connection, N3Source electrode the port V- is connected with body.4th NMOS tube N4Drain electrode and N2Source electrode connect It connects, N4Grid and third NMOS tube N3Grid, N3Drain electrode and P4Drain electrode connection, N4Source electrode the end V- is connected with body Mouthful.
In conclusion the embodiment of the present invention is a kind of controllable function wave that can produce sine wave, 2PSK signal and fsk signal Shape generative circuit.
The basic thought of this circuit is to utilize several GS1-GS4 type units and reference voltage generating circuit appropriate When input voltage changes between V1-V2, the relationship for exporting VO and inputting between VI meets required function for synthesis one The waveform convertion circuit of relationship is in the present embodiment near sinusoidal functional relation, then by the waveform convertion circuit and is exported Triangle wave circuit and the controller circuitry connection that voltage changes between V1-V2, to generate the continuous function waveform needed letter Number.Can produce the waveform convertion circuit of sine wave a kind of implementation method be will be shown in waveform convertion circuit shown in Figure 10 and Figure 11 Reference voltage generating circuit is connected, then when inputting VI and changing between 1.2V to 1.6V, output voltage VO and input voltage VI Between relationship meet near sinusoidal functional relation.SW in Figure 11 is a kind of crossbar switch, and function is, when S is logically high When level, VO1=VI1, VO2=VI2, when S is logic low, VO1=VI2, VO2=VI1.By VI and output electricity It is pressed in the symmetric triangular wave signal changed between 1.2-1.6 to be connected, controls the S signal and instruction triangular wave electricity of crossbar switch The logical signal that pressure rises or falls state is connected, so that it may continuous sine wave is generated in the output end of waveform convertion circuit, Frequency is equal with triangular wave frequency.If S signal is controlled by controller, 2PSK signal can produce.If triangular signal Rise time and fall time difference is controllable, under controller action, that is, can produce fsk signal.
The routine that the design of the crossbar switch, triangular-wave generator, controller belongs in IC design problem is set Meter problem, claimed is the design method of the waveform convertion circuit.

Claims (8)

1. a kind of Continuous time functions signal generating circuit of Digital Signals, it is characterised in that: signal generating circuit is used for In integrated circuits generate have complicated function waveform controllable signal, signal generating circuit include: triangular wave generate sub-circuit, Waveform convertion sub-circuit and controller sub-circuit, three subcircuits are connected with each other, wherein waveform convertion sub-circuit and several ginsengs It examines voltage to be connected, controller sub-circuit is connected with external control signal；
Waveform convertion sub-circuit contains at least one the element circuit with similar Gaussian function IV characteristic, has similar Gaussian function The element circuit of number IV characteristic includes 4 kinds of GS1 type, GS2 type, GS3 type and GS4 type element circuits, constitutes waveform convertion sub-circuit When, selection only uses one of them or is used in mixed way；4 kinds of element circuit outside ports having the same, each element circuit There are 7 ports, is respectively defined as scanning voltage input terminal VI, two threshold voltage control terminal VS1And VS2, operating current control terminal VB, current output terminal IOAnd working power anode V+ and working power negative terminal V-；GS1 type element circuit is from IOPort is defeated outward Electric current out exports electric current IOWith ViThe relationship of variation is
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage decision at end, k It is the constant determined by transistor size in circuit；
GS2 type is from IOPort absorbs electric current, absorbs electric current IOWith input voltage ViRelationship be
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage decision at end, k It is the constant determined by transistor size in circuit；
GS3 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage decision at end, k1 And k2It is the constant determined by transistor size in circuit；
GS3 type element circuit is from IOPort exports electric current outward, exports electric current IOWith ViThe relationship of variation is
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage decision at end, k1 And k2It is the constant determined by transistor size in circuit；
GS4 type element circuit is from IOPort absorbs electric current, absorbs electric current IOWith ViThe relationship of variation is
In formula,
Wherein ViTo be added in VIThe voltage at end, VS1For VS1The voltage at end, VS2For VS2The voltage at end, ISBy VBThe voltage decision at end, k1 And k2It is the constant determined by transistor size in circuit.
2. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: three Angle wave generates sub-circuit and generates two signals, one of them is output voltage linear change between two voltage values V1 and V2 Triangular signal, another is the status signal for indicating triangular wave uplink and downlink, and triangular signal is used for as scanning voltage Waveform convertion sub-circuit is to generate the signal changed over time；Status signal is used to control the modulus of conversion of waveform convertion sub-circuit Formula；Status signal is connected with controller sub-circuit, is used to indicate the output voltage change direction that triangular wave generates sub-circuit.
3. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: control System circuit generates control triangular-wave generator sub-circuit output triangular wave up and down for receiving external control signal The signal of time and the reference voltage selection signal of waveform convertion sub-circuit.
4. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: wave Fractal transform sub-circuit is used to be converted to the voltage of linear change the voltage signal changed by required functional relation, and mapping mode is logical Cross status signal and reference voltage control that triangular wave generates sub-circuit.
5. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: The implementation of GS1 type element circuit includes being realized using 6 NMOS tubes and 4 PMOS tube, connection relationship are as follows: first NMOS Manage (N1) drain electrode connection the port V+, grid connect VIPort, first NMOS tube (N1) source electrode connect second NMOS tube (N2) source electrode and third NMOS tube (N3) drain electrode, first NMOS tube (N1) body connect the port V-；
Second NMOS tube (N2) drain electrode connect first PMOS tube (P1) drain electrode, grid and second PMOS tube (P2) Grid；Second NMOS tube (N2) grid connect VS1Port, second NMOS tube (N2) source electrode connect first NMOS tube (N1) source electrode and third NMOS tube (N3) drain electrode, second NMOS tube (N2) body connect the port V-；
Third NMOS tube (N3) drain electrode connect first NMOS tube (N1) source electrode and second NMOS tube (N2) source electrode, Third NMOS tube (N3) grid connect VBPort, third NMOS tube (N3) source electrode the port V- is connected with body；
4th NMOS tube (N4) drain electrode connect the 4th PMOS tube (P4) drain electrode, the 4th PMOS tube (P4) grid and Third PMOS tube (P3) grid, the 4th NMOS tube (N4) grid connect VIPort, the 4th NMOS tube (N4) source electrode Connect the 5th NMOS tube (N5) source electrode and the 6th NMOS tube (N6) drain electrode, the 4th NMOS tube (N4) body connect V- Port；
5th NMOS tube (N5) drain electrode connect the port V+, the 5th NMOS tube (N5) grid connect VS2Port, the 5th NMOS tube (N5) source electrode connect the 4th NMOS tube (N4) source electrode and the 6th NMOS tube (N6) drain electrode, the 5th NMOS Manage (N5) body connect the port V-；
6th NMOS tube (N6) drain electrode connect the 4th NMOS tube (N4) source electrode and the 5th NMOS tube (N5) source electrode, 6th NMOS tube (N6) grid connect VBPort, the 6th NMOS tube (N6) source electrode and body all connect the port V-；
First PMOS tube (P1) drain and gate link together and jointly connect second NMOS tube (N2) drain electrode and Two PMOS tube (P2) grid, first PMOS tube (P1) source electrode and body all connect the port V+；
Second PMOS tube (P2) drain electrode connect I/O port, second PMOS tube (P2) grid connect first PMOS tube (P1) grid, drain electrode and second NMOS tube (N2) drain electrode, second PMOS tube (P2) source electrode and body all connect the end V+ Mouthful；
Third PMOS tube (P3) drain electrode connect I/O port, third PMOS tube (P3) grid connect the 4th PMOS tube (P4) grid, drain electrode and the 4th NMOS tube (N4) drain electrode, third PMOS tube (P3) source electrode and body all connect the end V+ Mouthful；
4th PMOS tube (P4) drain and gate connect third metal-oxide-semiconductor (P3) grid the 4th NMOS tube (N4) leakage Pole, the 4th PMOS tube (P4) source electrode and body all connect the port V+.
6. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: The implementation of GS2 type element circuit includes being realized using 6 PMOS tube and 4 NMOS tubes, connection relationship are as follows: first PMOS Manage (P1) drain electrode connect with the port V-, first PMOS tube (P1) grid and VIPort connection, first PMOS tube (P1) Source electrode and second PMOS tube (P2) source electrode and third PMOS tube (P3) drain electrode connection, first PMOS tube (P1) body It is connect with the port V+；
Second PMOS tube (P2) drain electrode and first NMOS tube (N1) drain electrode, grid and second NMOS tube (N2) Grid connection, second PMOS tube (P2) grid and VS1Port connection, second PMOS tube (P2) source electrode and first PMOS tube (P1) source electrode and third metal-oxide-semiconductor (P3) drain electrode connection, second PMOS tube (P2) body and the port V+ connect It connects；
Third PMOS tube (P3) drain electrode and first PMOS tube (P1) source electrode and second PMOS tube (P2) source electrode connect It connects, third PMOS tube (P3) grid and VBPort connection, third PMOS tube (P3) drain electrode and body connect with the port V+；
4th PMOS tube (P4) drain electrode and third NMOS tube (N3) grid, the 4th NMOS tube (N4) grid and 4th NMOS tube (N4) drain electrode connection, the 4th PMOS tube (P4) grid and VIPort connection, the 4th PMOS tube (P4) Source electrode and the 5th PMOS tube (P5) source electrode and the 6th PMOS tube (P6) drain electrode connection, the 4th PMOS tube (P4) Body is connect with the port V+；
5th PMOS tube (P5) drain electrode connect with the port V-, the 5th PMOS tube (P5) grid and VS2Port connection, the 5th A PMOS tube (P5) source electrode and the 4th PMOS tube (P4) source electrode and the 6th PMOS tube (P6) drain electrode connection, the 5th A PMOS tube (P5) body connect with the port V+；
First NMOS tube (N1) drain electrode and grid link together and with second PMOS tube (P2) drain electrode and second NMOS tube (N2) grid connection, first NMOS tube (N1) source electrode the port V- is connected with body；
Second NMOS tube (N2) drain electrode and IOPort connection, second NMOS tube (N2) grid and first NMOS tube (N1) Grid, drain electrode and second PMOS tube (P2) drain electrode connection, second NMOS tube (N2) source electrode the end V- is connected with body Mouthful；
Third NMOS tube (N3) drain electrode connect IOPort, third NMOS tube (N3) grid and the 4th NMOS tube (N4) Grid, the 4th NMOS tube (N4) drain electrode and the 4th PMOS tube (P4) drain electrode connection, third NMOS tube (N3) source electrode The port V- is connected with body；
4th NMOS tube (N4) drain electrode and grid link together and with third NMOS tube (N3) grid and the 4th PMOS tube (P4) drain electrode connection, the 4th NMOS tube (N4) source electrode the port V- is connected with body.
7. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: The implementation of GS3 type element circuit includes being realized using 6 NMOS tubes and 4 PMOS tube, connection relationship are as follows: first NMOS Manage (N1) drain electrode connect the port V+, first NMOS tube (N1) grid connect VIPort, first NMOS tube (N1) source electrode Connect second NMOS tube (N2) source electrode and third NMOS tube (N3) drain electrode, first NMOS tube (N1) body connect V- Port；
Second NMOS tube (N2) drain electrode connect first PMOS tube (P1) drain electrode, first PMOS tube (P1) grid with And second PMOS tube (P2) grid, second NMOS tube (N2) grid connect VS1Port, second NMOS tube (N2) source Pole connects first NMOS tube (N1) source electrode and third NMOS tube (N3) drain electrode, second NMOS tube (N2) body connection The port V-；
Third NMOS tube (N3) drain electrode connect first NMOS tube (N1) source electrode and second NMOS tube (N2) source electrode, Third NMOS tube (N3) grid connect VBPort, third NMOS tube (N3) source electrode the port V- is connected with body；
4th NMOS tube (N4) drain electrode connect the 4th PMOS tube (P4) drain electrode, the 4th PMOS tube (P4) grid with And P3Grid, the 4th NMOS tube (N4) grid connect VIPort, the 4th NMOS tube (N4) source electrode connect the 5th NMOS tube (N5) source electrode and the 6th NMOS tube (N6) drain electrode, the 4th NMOS tube (N4) body connect the port V-；
5th NMOS tube (N5) drain electrode connect the port V+, the 5th NMOS tube (N5) grid connect VS2Port, the 5th NMOS tube (N5) source electrode connect the 4th NMOS tube (N4) source electrode and the 6th NMOS tube (N6) drain electrode, the 5th NMOS tube (N5) body connect the port V-；
6th NMOS tube (N6) drain electrode connect the 4th NMOS tube (N4) source electrode and the 5th NMOS tube (N5) source electrode, 6th NMOS tube (N6) grid connect VBPort, the 6th NMOS tube (N6) source electrode and body all connect the port V-；
First PMOS tube (P1) drain and gate link together and jointly connect second NMOS tube (N2) drain electrode and Second PMOS tube (P2) grid, first PMOS tube (P1) source electrode and first PMOS tube (P1) body all connect the end V+ Mouthful；
Second PMOS tube (P2) drain electrode connect third metal-oxide-semiconductor (P3) source electrode, second PMOS tube (P2) grid connection First PMOS tube (P1) grid, first PMOS tube (P1) drain electrode and second NMOS tube (N2) drain electrode, second PMOS tube (P2) source electrode and body all connect the port V+；
Third PMOS tube (P3) drain electrode connect I/O port, third PMOS tube (P3) grid connect the 4th PMOS tube (P4) grid, the 4th PMOS tube (P4) drain electrode and the 4th NMOS tube (N4) drain electrode, third PMOS tube (P3) Source electrode connects second PMOS tube (P2) drain electrode, third PMOS tube (P3) body all connect the port V+；
4th PMOS tube (P4) drain and gate connect third metal-oxide-semiconductor (P3) grid and the 4th NMOS tube (N4) Drain electrode, the 4th PMOS tube (P4) source electrode and the 4th PMOS tube (P4) body all connect the port V+.
8. the Continuous time functions signal generating circuit of Digital Signals according to claim 1, it is characterised in that: The implementation of GS4 type element circuit includes being realized using 6 PMOS tube and 4 NMOS tubes, connection relationship are as follows: first PMOS Manage (P1) drain electrode connect with the port V-, first PMOS tube (P1) grid and VIPort connection, first PMOS tube (P1) Source electrode and second PMOS tube (P2) source electrode and third PMOS tube (P3) drain electrode connection, first PMOS tube (P1) Body is connect with the port V+；
Second PMOS tube (P2) drain electrode and first NMOS tube (N1) drain electrode, first NMOS tube (N1) grid and Second NMOS tube (N2) grid connection, second PMOS tube (P2) grid and VS1Port connection, second PMOS tube (P2) Source electrode and first PMOS tube (P1) source electrode and third PMOS tube (P3) drain electrode connection, second PMOS tube (P2) Body connect with the port V+；
Third PMOS tube (P3) drain electrode and first PMOS tube (P1) source electrode and second PMOS tube (P2) source electrode connect It connects, third PMOS tube (P3) grid and VBPort connection, third PMOS tube (P3) drain electrode and body connect with the port V+；
4th PMOS tube (P4) drain electrode and the 4th NMOS tube (N4) grid, third NMOS tube (N3) grid and Third NMOS tube (N3) drain electrode connection, the 4th PMOS tube (P4) grid and VIPort connection, the 4th PMOS tube (P4) Source electrode and the 5th PMOS tube (P5) source electrode and the 6th PMOS tube (P6) drain electrode connection, the 4th PMOS tube (P4) Body is connect with the port V+；
5th PMOS tube (P5) drain electrode connect with the port V-, the 5th PMOS tube (P5) grid and VS2Port connection, the 5th A PMOS tube (P5) source electrode and the 4th PMOS tube (P4) source electrode and the 6th PMOS tube (P6) drain electrode connection, the 5th A PMOS tube (P5) body connect with the port V+；
First NMOS tube (N1) drain electrode and grid link together and with second PMOS tube (P2) drain electrode and second NMOS tube (N2) grid connection, first NMOS tube (N1) source electrode the port V- is connected with body；
Second NMOS tube (N2) drain electrode and IOPort connection, second NMOS tube (N2) grid and first NMOS tube (N1) Grid, first NMOS tube (N1) drain electrode and second PMOS tube (P2) drain electrode connection, second NMOS tube (N2) Source electrode and the 4th NMOS tube (N4) drain electrode connection, second NMOS tube (N2) body connect the port V-；
Third NMOS tube (N3) drain electrode and grid link together and with the 4th NMOS tube (N4) grid and the 4th PMOS tube (P4) drain electrode connection, third NMOS tube (N3) source electrode the port V- is connected with body；
4th NMOS tube (N4) drain electrode and second NMOS tube (N2) source electrode connection, the 4th NMOS tube (N4) grid With third NMOS tube (N3) grid, third NMOS tube (N3) drain electrode and the 4th PMOS tube (P4) drain electrode connection, 4th NMOS tube (N4) source electrode the port V- is connected with body.
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