CN106024714A - 具有含锗的释放层的iii-v族化合物和锗化合物纳米线悬置 - Google Patents
具有含锗的释放层的iii-v族化合物和锗化合物纳米线悬置 Download PDFInfo
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Abstract
一种器件包括:衬底层;限定nFET(n型场效应晶体管)区域的源极/漏极部件的第一集合;限定pFET(p型场效应晶体管)区域的源极/漏极部件的第二集合;第一悬置纳米线,至少部分地悬置在nFET区域中的衬底层之上并且由III‑V族材料制成;以及第二悬置纳米线,至少部分地悬置在pFET区域中的衬底层之上并且由含锗材料制成。在一些实施例中,通过在含锗的释放层的顶部上添加合适的纳米线层并且随后移除含锗的释放层以使得纳米线悬置而制造第一悬置纳米线和第二悬置纳米线。
Description
技术领域
本发明总体涉及纳米线型半导体器件的领域,并且更具体地涉及具有“释放层”(也即,当首先形成纳米线结构时在纳米线下方并支撑纳米线、但是随后被移除以使得纳米线被悬置而并不具有在纳米线悬置区段下方并支撑纳米线悬置区段的任何材料的层)的纳米线型半导体器件。
背景技术
制造包括纳米线部分的半导体器件是已知的。例如,一些晶体管使用纳米线以形成晶体管的栅极部分。纳米线器件的“释放”是在制造工艺中的关键步骤。更具体地,在纳米线型半导体器件中“释放”纳米线涉及如下制造工艺,其中(i)首先在另一层(也即“释放层”)的顶表面上初始地形成纳米线,以及(ii)从纳米线的下方移除(或释放)释放层或者释放层的至少一部分(并不移除纳米线);以及(iii)结果,纳米线被悬置在其中释放层曾经所处的区域之上。
在半导体器件中使用“III-V族化合物”作为半导体材料是已知的。示例性的并且最通常使用的III-V族半导体材料包括但不限于;砷化镓(GaAs)、磷化铟(InP)和砷化铟镓(InGaAs)。可以使用任何其他二元、三元或其他组合的III-V族半导体。
发明内容
根据本发明的一个方面,一种至少部分地制造半导体器件的方法包括以下步骤(并不必然按照以下顺序):(i)提供第一子组件,包括衬底层、形成在衬底层的顶表面的至少一部分上的含锗的层、位于含锗的层的顶表面的一部分上的III-V族材料纳米线层、位于含锗的层的顶表面的一部分上的硅-锗(SiGe)纳米线层;以及(ii)通过移除含锗的层将第一子组件精炼为第二子组件,从而(a)III-V族材料纳米线层至少部分地悬置在衬底层之上;以及(b)SiGe纳米线层至少部分地悬置在衬底层之上。
根据本发明的另一方面,一种至少部分地制造半导体器件的方法包括以下步骤(并不必然按照以下顺序):(i)提供第一子组件,第一子组件包括第一处理晶片、形成在第一处理晶片的顶表面的至少一部分上的第一含锗的层、以及位于第一含锗的层的顶表面的至少一部分上的III-V族材料纳米线层,其中针对III-V族材料生长而优化第一含锗的层,从而III-V族材料层具有相对低的拉伸应变;(ii)提供第二子组件,第二子组件包括第二处理晶片、形成在第二处理晶片的顶表面的至少一部分上的第二含锗的层,其中优化第二含锗的层以用作用于p型场效应晶体管栅极材料生长的种子层;(iii)通过将第一子组件晶片接合至第二子组件的顶表面上将第一和第二子组件精炼为第三子组件,从而第三子组件包括第二处理晶片、形成在第二处理晶片的顶表面的至少一部分上的第二含锗的层、以及位于第二含锗的层的顶表面的至少一部分上的III-V族材料纳米线层;(iv)通过将III-V族材料纳米线层的一部分替换为硅-锗(SiGe)纳米线层而将第三子组件精炼为第四子组件,其中SiGe纳米线层位于第二含锗的层的顶表面的至少一部分之上;以及(v)通过移除第二含锗的层将第四子组件精炼为第五子组件,从而:(a)III-V族材料纳米线层至少部分地悬置在第二处理晶片之上;以及(b)SiGe纳米线层至少部分地悬置在第二处理晶片层之上。
根据本发明的另一方面,一种半导体器件包括:(i)衬底层;(ii)源极/漏极部件的第一集合,在衬底层中限定nFET(n型场效应晶体管)区域;(iii)源极/漏极部件的第二集合,在衬底层中限定pFET(p型场效应晶体管)区域;(iv)第一悬置纳米线,至少部分地悬置在nFET区域中衬底层之上,由III-V族材料制成,并且电连接以用作用于源极/漏极部件的第一集合的栅极;以及(v)第二悬置纳米线,至少部分地悬置在pFET区域中的衬底层之上,由硅-锗(SiGe)制成,并且电连接以用作用于源极/漏极部件的第二集合的栅极。
附图说明
图1A是根据本发明的在制造半导体器件的第一实施例中使用的第一中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图1B是在制造第一实施例半导体器件中使用的第二中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图1C是在制造第一实施例半导体器件中使用的第三中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图1D是在制造第一实施例半导体器件中使用的第四中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图1E是在制造第一实施例半导体器件中使用的第四中间子组件的横向剖视图(为了清楚示意目的省略了剖面线);
图2A是根据本发明的在制造半导体器件的第二实施例中使用的第一中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图2B是在制造第二实施例半导体器件中使用的第二中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图2C是在制造第二实施例半导体器件中使用的第三中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图2D是在制造第二实施例半导体器件中使用的第四中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);
图2E是在制造第二实施例半导体器件中使用的第五中间子组件的纵向剖视图(为了清楚示意目的省略了剖面线);以及
图2F是在制造第二实施例半导体器件中使用的第五中间子组件的横向剖视图(为了清楚示意目的省略了剖面线)。
具体实施方式
本发明的一些实施例涉及一种器件,包括:衬底层;源极/漏极部件的第一集合,限定nFET(n型场效应晶体管)区域;源极/漏极部件的第二集合,限定pFET(p型场效应晶体管)区域;第一悬置纳米线,至少部分地悬置在nFET区域中的衬底层之上并且由III-V族材料制成;以及第二悬置纳米线,至少部分地悬置在pFET区域中衬底层之上并且由含锗材料制成。在一些实施例中,通过在含锗的释放层的顶部上添加合适的纳米线层并且随后移除含锗的释放层以使得纳米线悬置来制造第一悬置纳米线和第二悬置纳米线。
在一些实施例中,一种用于制造悬置纳米线型半导体器件的制造方法包括:(i)由III-V族化合物制造纳米线;以及(ii)使用含锗(含Ge)的层作为用于悬置III-V族化合物悬置纳米线的释放层(在制造期间至少部分地被移除)。“晶格匹配”是可以与III-V悬置纳米线/含锗的释放层制造工艺结合使用的有用的技术。半导体材料通常具有晶体结构,其中原子在由晶格常数特征化的规则晶格中。晶格匹配尝试匹配(或至少接近匹配)用于将被混合和/或相互邻近定位的两种半导体材料的晶格常数。例如:(i)GaAs是具有5.65325A(埃)晶格常数的III-V族半导体材料;以及(ii)锗是具有5.658A晶格常数的用于半导体器件中的材料;以及(iii)因为GaAs和锗的晶格常数值非常接近,这些材料出于大多数目的而被视作是晶格匹配的。
在本发明的一些实施例中,锗(Ge)或硅-锗(SiGe)层用作释放层。在此,锗释放层和/或SiGe释放层将共同地称作“含锗的释放层”。在本发明的一些实施例中,选择性地刻蚀含锗的释放层,意味着通过采用移除锗和/或SiGe而并不移除正制造的中间悬置纳米线型半导体子组件中其他材料的刻蚀剂刻蚀来释放锗或SiGe释放层(或释放层的锗或SiGe部分)。
用于制作处理晶片的材料可以渐变直至纯锗。为了解释,如在本文献中所使用的那样,术语“渐变SiGe”涉及SiGe层的锗含量增加至不具有硅的纯锗的最大等级。例如,10%等级SiGe在其合金构成中将具有10%锗以及90%硅。
图1A至图1C示出了用于制造纳米线型半导体器件100的第一工艺流程。更具体地:(i)图1A示出了第一中间子组件100a;(ii)图1B示出了第二中间子组件100b;以及(iii)图1C示出了第三中间子组件100c。
如图1A中所示,第一中间子组件100a包括:处理晶片102;含锗的释放层104;III-V族化合物纳米线层106;以及虚线区域107。在该示例中:(i)处理晶片层由纯硅制成,数百微米厚;(ii)含锗的释放层由4-8nm(纳米)厚的相对富锗SiGe制成(备选地,其可以由纯Ge制成);以及(iii)III-V族化合物纳米线层由4至8nm厚(其他实施例可以范围在2至20nm厚之间)的合适的III-V族化合物制成。
开始于中间子组件100a,执行以下操作以便于形成氧化物隔离区域:(i)焊盘氮化物;(ii)刻蚀沟槽(参见虚线区域107,示出了刻蚀沟槽所在处);(iii)沉积氧化物停止层108(参见图1B);(v)对焊盘抛光;以及(v)剥除焊盘。现在将在以下中更详细描述形成氧化物隔离区域的该工艺。
关于操作(i),在该步骤中沉积的氮化物焊盘并未示出在图中,但是本领域技术人员将知晓焊盘氮化物是标准的STI(浅沟槽隔离)工艺。在该实施例中,焊盘氮化物操作中使用的具体氮化物是氮化硅。更具体地,在该实施例中,由等离子增强化学气相沉积(PECVD)执行焊盘氮化物操作,其是用于形成有源区域的STI工艺。更具体地,氮化物焊盘有助于在虚线区域107的左手侧形成NFET(n型场效应晶体管)区域120(参见图1C)以及在虚线区域107的右手侧形成PFET(p型场效应晶体管)区域122(参见图1C)。
关于操作(ii)(刻蚀沟槽),用于移除材料并且制造沟槽的工艺是RIE(反应离子刻蚀)。如在图1A中由虚线区域107所示,沟槽向下延伸进入含锗的层104中。
关于操作(iii),根据用于沉积氧化物停止层的当前传统工艺在操作(ii)处之前形成的沟槽中沉积氧化物停止层108。
关于“对焊盘抛光”操作(iv),执行化学机械平坦化(CMP)以从氮化物焊盘(图中未示出)的顶表面向下自顶向下移除材料。氧化物停止层108的顶表面停止了由操作(iv)的CMP自顶向下移除材料以使得氮化物焊盘(图中未示出)将是平坦和水平的并且将具有合适的高度。更具体地,氧化物停止层108防止操作(iv)的CMP从III-V族化合物纳米线层106移除材料(该层106在该示例中的厚度仅为4至8纳米,并且因此无法容许传统的CMP工艺)。
在剥除焊盘的步骤(v)处,由传统的剥除工艺移除氮化物焊盘(图中未示出)以完成浅沟槽隔离并且因此形成NFET和PFET区域。在形成氧化物隔离区域的工艺的操作(i)至(v)之后,获得了图1B的中间子组件100b。中间子组件100b包括:处理晶片102;含锗的释放层104;III-V族化合物纳米线层106;以及氧化物停止层108。如图1B中所示,氧化物停止层108现在将III-V族化合物层106分隔为两个区域120和122。
为了从图1B的中间子组件100b得到图1C的中间子组件100c,执行SiGe纳米线层形成工艺。SiGe纳米线层形成工艺包括以下操作:(i)采用硬掩模(例如SiN或SiO2硬掩模材料)图案化;(ii)在区域122中(而非在区域120中)刻蚀掉III-V族化合物纳米线层;以及(iii)生长SiGe纳米线层112(参见图1C)。在以下段落中将讨论SiGe纳米线层形成工艺的步骤。
在SiGe纳米线层形成工艺的操作(i)处,由传统的硬掩模施加工艺,在区域120中而非在区域122中施加硬掩模层110。
在SiGe纳米线层形成工艺的操作(ii)处,在区域122中而非在区域120中(由硬掩模层110保护免受刻蚀)刻蚀去除III-V纳米线层。刻蚀化学剂的选择强烈地取决于所使用的III-V族化合物,如本领域技术人员所知。例如,刻蚀化学剂可以是:(i)在GaAs或InGaAs的情形中的HF;或(ii)在InP的情形中的HCl。
在SiGe纳米线层形成工艺的操作(iii)处,在区域122中在含锗的释放层104的顶部上生长SiGe纳米线层112(参见图1C)。SiGe纳米线层112相对于SiGe释放层104是相对贫锗的。在纯硅可以用于纳米线层112的角度来说,纯硅应该在本公开之下视作用于制造纳米线的一类“SiGe层”。稍后当SiGe释放层104被移除(也即释放)时,这将变得重要。在该实施例中,SiGe纳米线层112由外延生长而生长,但是其可以由当前传统或未来将要研发的任何工艺添加。在该实施例中,层112的厚度为2-20nm,优选4-8nm。在含锗的纳米线层生长步骤期间,含锗的释放层104在SiGe纳米线层112下方并且支撑它。在SiGe纳米线生长步骤(iii)的结束处,获得了图1C的中间子组件100c。
在如上所述的SiGe纳米线层形成工艺之后,由传统工艺移除硬掩模层110(将图1C的中间子组件100c与图1D的中间子组件100d比较)。随后执行修整(touch-up)CMP以平坦化III-V族化合物纳米线层106和SiGe纳米线层112的顶表面。再一次,氧化物停止层108的顶表面用作用于修整CMP的停止层。
图1C的中间子组件100c与图1D的中间子组件100d的比较示出含锗的释放层104的释放,这导致III-V族化合物纳米线层106和SiGe纳米线层112的悬置。如图1D中所示,悬置区域130现在没有材料,从而III-V族化合物纳米线层和含锗的纳米线层悬置在处理晶片102之上并且并未支撑在它们相应下侧。
更具体地,在该实施例中,由湿法刻蚀工艺移除(或“释放”)含锗的释放层。相对于纳米线层的锗含量,相对较高的锗含量有助于移除释放层而不损伤含锗的纳米线层,因为高锗含量部分可以被湿法刻蚀而基本上不会刻蚀或损伤相对低锗含量(SiGe)部分。为了使得选择性刻蚀成功,在SiGe释放层与SiGe纳米线层之间通常存在至少20-30%的锗含量差。
如图1E的正交左侧视图100e中所示(参见,对于观察者朝向而言为图1D中截面箭头),III-V族化合物纳米线层106在该实施例中具有矩形截面。备选地,悬置纳米线可以分布(例如通过退火)以具有其他形状,诸如圆形截面。纳米线106和112可以包括在场效应晶体管(FET)器件中作为栅极区域,其中:(i)III-V族化合物纳米线106用作用于半导体器件的nFET部分(也称作nFET区域)的栅极;以及(ii)SiGe纳米线112用作用于半导体器件的pFET部分(也称作pFET区域)的栅极。用于pFET和nFET区域的源极/漏极部件(参见图1D在方框150和152处)仅以示意形式示出,因为这些在该实施例中类似于已知的nFET/pFET半导体器件的源极/漏极部件而构造并定位。现在将参照图2A至图2C讨论对于如上所述半导体器件制造方法的变化。该方法实施晶片接合方案以解决PFET区域的应变工程设计。工艺开始于提供如图2A中所示的第一子组件200a和如图2B中所示第二子组件200b。第一子组件200a包括:第一处理晶片层202;第一含锗的层204(在该实施例中是具有将针对III-V族材料层界面优化的原子比例和/或掺杂的SiGe);以及III-V族材料层206。第二子组件200b包括:第二处理晶片层220;以及第二含锗的层222(在该实施例中是具有将原子比例和/或掺杂优化以用作用于PFET的种子层的SiGe)。
第一组件200a和第二子组件200b“晶片接合”在一起(也即以两个面包片制作三明治的方式放置在一起)以制造如图2C中所示的第三子组件。注意,第一晶片层和第二晶片层分别是如图2C中所示第三子组件的顶部和底部外层。精炼第三子组件以制造如现在将要讨论的第四子组件。从第三子组件的顶部移除第一处理晶片层202和第一含锗的层204(如图2C中所示)以产生第四子组件(如图2D中所示)。第四子组件(如图2D中所示)在结构上类似于第一中间子组件100a,这是对于结合系列图1讨论工艺的开始工件。然而,在系列图2中所示的该变形例中,III-V族材料层206初始地生长和/或沉积在针对III-V族材料界面优化的层(具体地第一含锗的层204)上的事实意味着III-V族材料层206可以经受与来自系列图1的III-V族材料层106相比较小的相反拉伸应力和/或应变。
第四子组件(如图2D中所示)随后经过类似于结合图1A至图1E如上所述类似的处理以使得释放了第二含锗的层222并且III-V族材料层206悬置作为在第二处理晶片层220之上的悬置纳米线(参见图2E和图2F)。
为了示意性说明目的已经展示了本发明的各个实施例的说明,但是并非意在为穷举性或限定于所公开的实施例。许多修改例和变形例对于本领域技术人员将是明显的而并未脱离本发明的范围和精神。选择在此所使用的术语以最佳地解释实施例的原理、实际应用或者对于市场上找到技术的技术改进,或者使得本领域其他技术人员能够理解在此所公开的实施例。
以下段落为了理解和/或解释该文献的目的而阐述了对于某些词语或术语的一些定义。
本发明:不应视作绝对指示了由术语“本发明”所述的主题由如所提交的权利要求、或者在专利诉讼之后可以最终出版的权利要求所覆盖;而术语“本发明”用于帮助读者获得对于在此本公开相信潜在地是新颖的普遍感觉,如通过使用术语“本发明”所指示的该理解是假设性和临时性的,并且当相关信息发展并且潜在地修改权利要求时经受在专利诉讼期间的改变。
实施例:参见以上“本发明”的定义-类似的警告适用于术语“实施例”。
和/或:包括性的或;例如,A、B“和/或”C意味着A或B或C的至少一个是真实并可应用的。
在……之上:直接地在……之上,和/或间接地在……之上;例如,如果桌子具有桌布,并且玻璃固定在桌布“之上”,则玻璃也将视作固定在桌子“之上”,因为词语“在……之上”由此定义。
Claims (19)
1.一种至少部分地制造半导体器件的方法,所述方法包括:
提供第一子组件,所述第一子组件包括衬底层、形成在所述衬底层的顶表面的至少一部分上的含锗的层、位于所述含锗的层的顶表面的一部分上的III-V族材料纳米线层、位于所述含锗的层的顶表面的一部分上的硅-锗SiGe纳米线层;以及
通过移除所述含锗的层将所述第一子组件精炼为第二子组件,从而:(i)所述III-V族材料纳米线层至少部分地悬置在所述衬底层上方,以及(ii)所述SiGe纳米线层至少部分地悬置在所述衬底层上方。
2.根据权利要求1所述的方法,进一步包括:
将所述III-V族材料纳米线层电连接至源极/漏极部件的第一集合,从而所述III-V族材料纳米线层用作用于n型场效应晶体管nFET的栅极;以及
将所述SiGe纳米线层电连接至源极/漏极部件的第二集合,从而所述SiGe纳米线层用作用于p型场效应晶体管pFET的栅极。
3.根据权利要求2所述的方法,其中,所述第一子组件进一步包括硬掩模材料层,所述硬掩模材料层至少基本上位于所述III-V族材料纳米线层的顶表面上,所述方法进一步包括:
通过从所述第二子组件剥除所述硬掩模材料层,将所述第二子组件精炼为第三子组件。
4.根据权利要求2所述的方法,其中:
所述第一子组件进一步包括氧化物停止层,所述氧化物停止层位于所述衬底层的顶表面上并且在所述III-V族材料纳米线层和所述含锗的纳米线层之间;
在所述第二子组件中,由所述氧化物停止层至少部分地支撑所述III-V族材料纳米线层的第一端;以及
在所述第二子组件中,由所述氧化物停止层至少部分地支撑所述SiGe纳米线层的第一端。
5.根据权利要求2所述的方法,其中,所述衬底是渐变为Ge的处理晶片。
6.根据权利要求2所述的方法,其中,用于制造所述III-V族材料纳米线层的III-V族材料与用于制造所述含锗的层的材料至少基本上晶格匹配。
7.根据权利要求2所述的方法,其中,用于制造所述含锗的层的材料具有比所述SiGe纳米线层更高的锗比例。
8.根据权利要求2所述的方法,其中,用于制造所述含锗的层的材料具有比所述SiGe纳米线层至少高百分之20的锗比例。
9.根据权利要求2所述的方法,其中,由湿法刻蚀工艺执行所述含锗的层的移除。
10.根据权利要求2所述的方法,其中,由湿法刻蚀工艺执行所述含锗的层的移除而基本上并不从所述SiGe纳米线层移除任何材料。
11.一种至少部分地制造半导体器件的方法,所述方法包括:
提供第一子组件,所述第一子组件包括第一处理晶片、形成在所述第一处理晶片的顶表面的至少一部分上的第一含锗的层、以及位于所述第一含锗的层的顶表面的一部分上的III-V族材料纳米线层,其中针对III-V族材料生长优化所述第一含锗的层,从而所述III-V族材料层具有相对低的拉伸应变;
提供第二子组件,所述第二子组件包括第二处理晶片、以及形成在所述第二处理晶片的顶表面的至少一部分上的第二含锗的层,其中优化所述第二含锗的层以用作用于p型场效应晶体管栅极材料生长的种子层;
通过将所述第一子组件晶片接合至所述第二子组件的顶表面上,将所述第一子组件和所述第二子组件精炼为第三子组件,从而所述第三子组件包括所述第二处理晶片、形成在所述第二处理晶片的顶表面的至少一部分上的所述第二含锗的层、以及位于所述第二含锗的层的顶表面的一部分上的所述III-V族材料纳米线层;
通过将所述III-V族材料纳米线层的一部分替换为硅-锗SiGe纳米线层,将所述第三子组件精炼为第四子组件,其中所述SiGe纳米线层位于所述第二含锗的层的顶表面的至少一部分之上;以及
通过移除所述第二含锗的层,将所述第四子组件精炼为第五子组件,从而:(i)所述III-V族材料纳米线层至少部分地悬置在所述第二处理晶片上方,以及(ii)所述SiGe纳米线层至少部分地悬置在所述第二处理晶片层上方。
12.根据权利要求11所述的方法,进一步包括:
将所述III-V族材料纳米线层电连接至源极/漏极部件的第一集合,从而所述III-V族材料纳米线层用作用于n型场效应晶体管nFET的栅极;以及
将所述SiGe纳米线层电连接至源极/漏极部件的第二集合,从而所述SiGe纳米线层用作用于p型场效应晶体管pFET的栅极。
13.根据权利要求12所述的方法,其中:
所述第四子组件进一步包括氧化物停止层,位于所述第二处理晶片的顶表面上并且在所述III-V族材料纳米线层和所述SiGe纳米线层之间;
在所述第五子组件中,由所述氧化物停止层至少部分地支撑所述III-V族材料纳米线层的第一端;以及
在所述第五子组件中,由所述氧化物停止层至少部分地支撑所述SiGe纳米线层的第一端。
14.根据权利要求12所述的方法,其中,所述第二处理晶片渐变至Ge。
15.根据权利要求12所述的方法,其中,用于制造所述III-V族材料纳米线层的III-V族材料与用于制造所述第一含锗的层的材料至少基本上晶格匹配。
16.根据权利要求12所述的方法,其中,用于制造所述第二含锗的层的材料具有比所述SiGe纳米线层更高的锗比例。
17.根据权利要求12所述的方法,其中,由湿法刻蚀工艺执行所述第二含锗的层的移除。
18.根据权利要求12所述的方法,其中,由湿法刻蚀工艺执行所述第二含锗的层的移除而基本上并不从所述SiGe纳米线层移除任何材料。
19.一种半导体器件,包括:
衬底层;
源极/漏极部件的第一集合,在所述衬底层中限定n型场效应晶体管nFET;
源极/漏极部件的第二集合,在所述衬底层中限定p型场效应晶体管pFET;
第一悬置纳米线,至少部分地悬置在所述nFET区域中的所述衬底层之上,由III-V族材料制成,并且电连接以用作用于所述源极/漏极部件的第一集合的栅极;以及
第二悬置纳米线,至少部分地悬置在所述pFET区域中的所述衬底层之上,由硅-锗SiGe制成,并且电连接以用作用于所述源极/漏极部件的第二集合的栅极。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110012090A1 (en) * | 2007-12-07 | 2011-01-20 | Agency For Science, Technology And Research | Silicon-germanium nanowire structure and a method of forming the same |
US20110059598A1 (en) * | 2009-09-10 | 2011-03-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for stabilizing germanium nanowires obtained by condensation |
US20110070734A1 (en) * | 2009-09-18 | 2011-03-24 | Commissariat A L'energie Atomique Et Aux Ene. Alt. | Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate |
US8445348B1 (en) * | 2011-12-28 | 2013-05-21 | National Chiao Tung University | Manufacturing method of a semiconductor component with a nanowire channel |
CN103378099A (zh) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于高k和金属栅极堆叠件的器件和方法 |
CN104011849A (zh) * | 2011-12-23 | 2014-08-27 | 英特尔公司 | Cmos纳米线结构 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7888753B2 (en) | 2006-07-31 | 2011-02-15 | International Business Machines Corporation | Ultra-sensitive detection techniques |
US20120199812A1 (en) | 2009-10-07 | 2012-08-09 | University Of Florida Research Foundation, Incorporated | Strain tunable silicon and germanium nanowire optoelectronic devices |
US8614492B2 (en) | 2009-10-26 | 2013-12-24 | International Business Machines Corporation | Nanowire stress sensors, stress sensor integrated circuits, and design structures for a stress sensor integrated circuit |
US20120168711A1 (en) | 2011-01-05 | 2012-07-05 | Mark Albert Crowder | Narrow-Waist Nanowire Transistor with Wide Aspect Ratio Ends |
US8580624B2 (en) | 2011-11-01 | 2013-11-12 | International Business Machines Corporation | Nanowire FET and finFET hybrid technology |
US8492208B1 (en) * | 2012-01-05 | 2013-07-23 | International Business Machines Corporation | Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process |
US8674342B2 (en) * | 2012-02-27 | 2014-03-18 | International Business Machines Corporation | Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers |
US20140091279A1 (en) | 2012-09-28 | 2014-04-03 | Jessica S. Kachian | Non-planar semiconductor device having germanium-based active region with release etch-passivation surface |
US8969145B2 (en) | 2013-01-19 | 2015-03-03 | International Business Machines Corporation | Wire-last integration method and structure for III-V nanowire devices |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110012090A1 (en) * | 2007-12-07 | 2011-01-20 | Agency For Science, Technology And Research | Silicon-germanium nanowire structure and a method of forming the same |
US20110059598A1 (en) * | 2009-09-10 | 2011-03-10 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for stabilizing germanium nanowires obtained by condensation |
US20110070734A1 (en) * | 2009-09-18 | 2011-03-24 | Commissariat A L'energie Atomique Et Aux Ene. Alt. | Manufacturing a microelectronic device comprising silicon and germanium nanowires integrated on a same substrate |
CN104011849A (zh) * | 2011-12-23 | 2014-08-27 | 英特尔公司 | Cmos纳米线结构 |
US8445348B1 (en) * | 2011-12-28 | 2013-05-21 | National Chiao Tung University | Manufacturing method of a semiconductor component with a nanowire channel |
CN103378099A (zh) * | 2012-04-26 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于高k和金属栅极堆叠件的器件和方法 |
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