CN105990320B - Transient voltage suppressor, electrostatic protection element thereof and array thereof - Google Patents
Transient voltage suppressor, electrostatic protection element thereof and array thereof Download PDFInfo
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- CN105990320B CN105990320B CN201510045415.5A CN201510045415A CN105990320B CN 105990320 B CN105990320 B CN 105990320B CN 201510045415 A CN201510045415 A CN 201510045415A CN 105990320 B CN105990320 B CN 105990320B
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- 230000001052 transient effect Effects 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000002955 isolation Methods 0.000 claims description 38
- 230000005611 electricity Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 10
- 229910052785 arsenic Inorganic materials 0.000 description 10
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 230000036632 reaction speed Effects 0.000 description 8
- 230000003068 static effect Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Abstract
The invention provides a transient voltage suppressor, an electrostatic protection element thereof and an array thereof. The voltage suppressor includes: the semiconductor device comprises a substrate, a well region with a first conduction type, a first doped region with a second conduction type and a second doped region with the second conduction type. The substrate is electrically floating. The well region is located in a substrate. The first doped region is located in the well region to form a diode, and the first doped region is electrically connected with a first voltage. The second doped region is located in the well region and electrically connected to a second voltage.
Description
Technical field
The present invention relates to a kind of Transient Voltage Suppressor with high reaction speed, its electrostatic protection element and its arrays.
Background technique
With the current rapid development of science and technology, integrated circuit is widely used in electronic device.In general, electronic product is very
It is easy the impact by burst of and uncontrollable static discharge (ElectroStatic Discharge, referred to as: ESD),
And the problem of causing the restarting of electronic product generating system or even hardware to come to harm and can not restore.Currently, for electronics
The ESD problem of product is more using Transient Voltage Suppressor (Transient Voltage Suppressor, referred to as: TVS)
Effective solution method.Transient Voltage Suppressor may make that the energy of ESD is discharged quickly through Transient Voltage Suppressor, keep away
Exempt from electronic product to be damaged by the impact of ESD.Therefore, now electronic product for Transient Voltage Suppressor demand with
Dependence increases therewith.And the typical case of Transient Voltage Suppressor is universal serial bus (USB) power supply, data line protection, number
Word video interface, high-speed local network, laptop, display device and plane formula panel display etc..
(such as high-resolution multimedia interface (High-Definition Multimedia is applied for high-speed interface
Interface, referred to as: HDMI 2.0), display port (Display port), USB 3.x etc.) for, in order to promote transient state electricity
The reaction speed of suppressor is pressed, size and breakdown voltage (Breakdown Voltage), meeting design smaller better as far as possible.
However, can then design the Transient Voltage Suppressor of larger size in order to preferable static discharge efficiency.In other words, it reacts
Speed and static discharge efficiency are in a kind of trade-off relationship.
Summary of the invention
The present invention provides a kind of Transient Voltage Suppressor, its electrostatic protection element and its array, reaction with higher
Speed is beneficial to signal transmitting.
The present invention provides a kind of Transient Voltage Suppressor comprising: substrate, has the at the wellblock with the first conductive type
First doped region of two conductivity types and the second doped region with the second conductive type.Substrate is electrically floating.Wellblock is located at lining
In bottom.First doped region is located in wellblock, and the first doped region and first voltage are electrically connected.Second doped region is located at wellblock
In, and the second doped region and second voltage are electrically connected.
In one embodiment of this invention, non-grid knot on the wellblock between above-mentioned first doped region and the second doped region
Structure.
It in one embodiment of this invention, further include that two isolation structures are located in substrate.Above-mentioned first doped region and
Two doped regions are located between two isolation structures, and do not contact with two isolation structures.
In one embodiment of this invention, the wellblock other than above-mentioned first doped region and except the second doped region
In, it is identical in the doping concentration of the first conductive type of same depth.
In one embodiment of this invention, above-mentioned substrate is wavy curve along the doping concentration of first direction.Wavy curve
It include: most wave crests and most troughs.Above-mentioned wave crest be located at one of two isolation structures and the first doped region it
Between, between the first doped region and the second doped region and the second doped region and two isolation structures it is another between.Above-mentioned trough
It is located in the first doped region and the second doped region.Each trough is between two neighboring wave crest.Above-mentioned wave crest and wave
Paddy alternates along first direction.
In one embodiment of this invention, in the wellblock other than above-mentioned first doped region and except the second doped region
Not with the doped region of the first conductive type.
In one embodiment of this invention, when the first conductive type is p-type, the second conductive type is N-type；When the first conductive type is
N-type, the second conductive type are p-type.
The present invention provides a kind of electrostatic protection element comprising: above-mentioned Transient Voltage Suppressor and at least one two pole
Pipe cascaded structure.At least one Diode series structure is in parallel with above-mentioned Transient Voltage Suppressor.
In one embodiment of this invention, at least one above-mentioned Diode series structure include: first diode and
Second diode.Above-mentioned first diode is located at the side of Transient Voltage Suppressor.First diode includes: with
First wellblock of one conductivity type, the third doped region with the second conductive type and the 4th doped region with the first conductive type.
First wellblock is located in substrate.Third doped region is located in the first wellblock.4th doped region is located in the first wellblock.Above-mentioned 4th
Doped region and the second doped region are electrically connected.Above-mentioned second diode be located at first diode and Transient Voltage Suppressor it
Between.Second diode includes: the second wellblock with the second conductive type, the 5th doped region with the second conductive type and tool
There is the 6th doped region of the first conductive type.Second wellblock is located in substrate.5th doped region is located in the second wellblock.6th doping
Area is located in the second wellblock.Above-mentioned 5th doped region and the first doped region are electrically connected.
In one embodiment of this invention, above-mentioned third doped region and the 6th doped region are electrically connected input/output terminal (I/
O).Above-mentioned 5th doped region and the first doped region are electrically connected first voltage.Above-mentioned 4th doped region and the second doped region are electrical
Connect second voltage.Above-mentioned first voltage is greater than second voltage.
In one embodiment of this invention, above-mentioned second voltage is ground voltage.
In one embodiment of this invention, at least one above-mentioned Diode series structure include: third diode and
4th diode.Third diode is between first diode and second diode.Third diode includes:
Third wellblock with the first conductive type, the 7th doped region with the second conductive type and the with the first conductive type the 8th mix
Miscellaneous area.Third wellblock is located in substrate.7th doped region is located in third wellblock.8th doped region is located in third wellblock.On
It states the 8th doped region and third doped region is electrically connected.4th diode be located at third diode and second diode it
Between.4th diode includes: the 4th wellblock with the second conductive type, the 9th doped region with the second conductive type and tool
There is the tenth doped region of the first conductive type.4th wellblock is located in substrate.9th doped region is located in the 4th wellblock.Tenth doping
Area is located in the 4th wellblock.Above-mentioned 9th doped region and the 6th doped region are electrically connected.
In one embodiment of this invention, above-mentioned 7th doped region and the tenth doped region are electrically connected input/output terminal (I/
O).Above-mentioned 5th doped region and the first doped region are electrically connected first voltage.Above-mentioned 4th doped region and the second doped region are electrical
Connect second voltage.Above-mentioned first voltage is greater than second voltage.
In one embodiment of this invention, above-mentioned second voltage is ground voltage.
It in one embodiment of this invention, further include light doped well zone between substrate and wellblock.Light doped well zone with
The conductivity type of substrate is different.
The present invention provides a kind of Transient Voltage Suppressor array comprising: above-mentioned Transient Voltage Suppressor and at least two
A Diode series structure.Above-mentioned at least two Diode series structure is in parallel with Transient Voltage Suppressor.At least two 2 poles
One in pipe cascaded structure is electrically connected with the first input/output terminal (I/O1).And at least two Diode series structures
Another and the second input/output terminal (I/O2) be electrically connected.
There is the first doped region and the second doping of same conductivity based on above-mentioned, of the invention Transient Voltage Suppressor
Area.Since the first doped region and first voltage are electrically connected, and the second doped region and second voltage are electrically connected, and therefore, are compared
In the Transient Voltage Suppressor of three pins of the prior art, the area of Transient Voltage Suppressor of the invention is smaller, can mention
Rise the reaction speed of element.Further, since the substrate of Transient Voltage Suppressor of the invention is electrically floating, therefore, electrostatic is put
Electric current will be transmitted along lateral path, without transmitting along vertical-path.In this way, which wink of the invention can be reduced
The breakdown voltage (BVceo) of state voltage suppressor, with the reaction speed of more lift elements.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of the Transient Voltage Suppressor of one embodiment of the invention；
Fig. 2 is in Fig. 1 along the first conductive type of I-I ' line and the doping concentration curve graph of the second conductive type；
Fig. 3 is the circuit diagram of the electrostatic protection element of first and second embodiment of the invention；
Fig. 4 is the diagrammatic cross-section of the electrostatic protection element of first embodiment of the invention；
Fig. 5 is the diagrammatic cross-section of the electrostatic protection element of second embodiment of the invention；
Fig. 6 is the circuit diagram of the electrostatic protection element of third of the present invention and fourth embodiment；
Fig. 7 is the diagrammatic cross-section of the electrostatic protection element of third embodiment of the invention；
Fig. 8 is the diagrammatic cross-section of the electrostatic protection element of fourth embodiment of the invention；
Fig. 9 is the circuit diagram of the Transient Voltage Suppressor array of one embodiment of the invention.
Description of symbols:
1: Transient Voltage Suppressor；
2,3,4,5: Diode series structure；
2a, 2b, 3a, 3b, 3c, 3d, 4a, 4b, 5a, 5b: diode；
10,20,30,40,50,60: isolation structure；
100: substrate；
102: wellblock；
108: the first wellblocks；
114: the second wellblocks；
122: third wellblock；
128: the four wellblocks；
104: the first doped regions；
106: the second doped regions；
110: third doped region；
112: the four doped regions；
116: the five doped regions；
118: the six doped regions；
124: the seven doped regions；
126: the eight doped regions；
130: the nine doped regions；
132: the ten doped regions；
120: light doped well zone；
I/O: input/output terminal；
I/O1: the first input/output terminal；
I/O2: the second input/output terminal；
N1, N2: trough；
P1, P2, P3: wave crest；
V1: first voltage；
V2: second voltage；
X1~X5: distance.
Specific embodiment
Below in an example, when the first conductive type is p-type, the second conductive type is N-type；When the first conductive type be N-type,
The second conductive type is p-type.The admixture of p-type is, for example, boron or boron difluoride.The admixture of N-type is, for example, phosphorus or arsenic.In this implementation
, can be using the first conductive type as p-type in example, the second conductive type is to implement for N-type.But the present invention is not limited thereto, on the contrary
Also implementable.
Fig. 1 is the diagrammatic cross-section of the Transient Voltage Suppressor of one embodiment of the invention.Fig. 2 is in Fig. 1 along I-I ' line
The first conductive type and the second conductive type doping concentration curve graph.
Fig. 1 is please referred to, the present invention provides a kind of Transient Voltage Suppressor 1 comprising: substrate 100 has the first conductive type
Wellblock 102, the first doped region 104 with the second conductive type, the second doped region 106 with the second conductive type and two
Isolation structure 10,20.Substrate 100 is electrically floating.Substrate 100 be, for example, semiconductor substrate, semiconducting compound substrate or
There is semiconductor substrate (Semiconductor Over Insulator, referred to as: SOI) on insulating layer.Semiconductor is, for example, IVA race
Atom, such as silicon or germanium.Semiconducting compound is, for example, that the atom of IVA race is formed by semiconducting compound, e.g. carbon
SiClx or germanium silicide or Group IIIA atom and VA race atom are formed by semiconducting compound, e.g. GaAs.At this
In embodiment, substrate 100 can have n-type doping.But the present invention is not limited thereto, and in other embodiments, substrate 100 can also
It is adulterated with p-type.
Wellblock 102 has the first conductive type, is located in substrate 100.The admixture of wellblock 102 is, for example, boron or bifluoride
Boron, doping concentration can be for example 1 × 1015/cm3To 1 × 1017/cm3.First doped region 104 and the second doped region 106 all positions
In wellblock 102.The admixture of first doped region 104 and the second doped region 106 is, for example, phosphorus or arsenic, the first doped region 104
Doping concentration can be for example 1 × 1020/cm3To 1 × 1022/cm3；And the doping concentration of the second doped region 106 can be for example 1 ×
1020/cm3To 1 × 1022/cm3.First doped region 104 and first voltage V1 is electrically connected.Second doped region 106 and second voltage
V2 is electrically connected.In the present embodiment, the first doped region 104 has different conductivity types from wellblock 102, may make up two poles
Pipe.And the second doped region 106 also has different conductivity types from wellblock 102, also may make up another diode.
Isolation structure 10 and isolation structure 20 are all located in substrate 100.First doped region 102 and the second doped region 104
It is not contacted between isolation structure 10 and isolation structure 20, and with isolation structure 10 with isolation structure 20.Isolation structure 10 with every
It can be for example zone oxidation structure (LOCOS) or shallow slot isolation structure (STI) from structure 20.Isolation structure 10 and isolation structure
20 material can be for example silica, silicon nitride or combinations thereof.
Referring to Fig. 1 and Fig. 2, substrate 100 is along the first conductive type of I-I ' line and the doping concentration of the second conductive type
It can be for example wavy curve.In the present embodiment, I-I ' line can be considered first direction.Above-mentioned wavy curve includes: wave crest P1-P3
And trough N1-N2.Trough N1 is between wave crest P1 and wave crest P2；And trough N2 is then located between wave crest P2 and wave crest P3.
Wave crest P1-P3 and trough N1-N2 can be alternateed along the direction of I-I ' line.In the present embodiment, distance X2 indicates the second doping
The wavy curve of the width in area 106, the region trough N1 indicates the doping concentration with the second doped region 106 of the second conductive type；
Distance X4 indicates that the width of the first doped region 104, the wavy curve in the region trough N2 indicate have the first of the second conductive type to mix
The doping concentration in miscellaneous area 104.
In the same manner, distance X1 indicates the distance between the second doped region 106 and isolation structure 20, the waveform in the region wave crest P1
Curve indicates the doping concentration of the wellblock 102 (with the first conductive type) between the second doped region 106 and isolation structure 20.Distance
X3 indicates that the distance between the first doped region 104 and the second doped region 106, the wavy curve in the region wave crest P2 indicate the first doping
The doping concentration of wellblock 102 (with the first conductive type) between area 104 and the second doped region 106；And distance X5 indicates first
The distance between doped region 104 and isolation structure 10, the wavy curve in the region wave crest P3 then indicate the first doped region 104 be isolated
The doping concentration of wellblock 102 (with the first conductive type) between structure 10.
Due in the wellblock 102 other than the first doped region 104 and except the second doped region 106, have the
The doped region of one conductivity type, therefore, the doping concentration of the first conductive type in wellblock 102 with same depth are identical.In addition,
On wellblock 102 between first doped region 104 and the second doped region 106, exist without gate structure.
Transient Voltage Suppressor of the invention has the first doped region and the second doped region of same conductivity.Due to first
Doped region and first voltage are electrically connected, and the second doped region and second voltage are electrically connected, therefore, compared to the prior art
The area of the Transient Voltage Suppressor of three pins, Transient Voltage Suppressor of the invention is smaller, can lift elements reaction
Speed.Further, since the substrate of Transient Voltage Suppressor of the invention is electrically floating, therefore, static discharge current will edge
Lateral path transmission, without being transmitted along vertical-path.In this way, which the breakdown potential of Transient Voltage Suppressor can be reduced
It presses (BVceo), the reaction speed of lift elements.
Fig. 3 is the circuit diagram of the electrostatic protection element of first and second embodiment of the invention.Fig. 4 is the present invention first
The diagrammatic cross-section of the electrostatic protection element of embodiment.Fig. 5 is that the section of the electrostatic protection element of second embodiment of the invention shows
It is intended to.
Referring to figure 3., the present invention provides a kind of electrostatic protection element comprising Transient Voltage Suppressor 1 and diode
Cascaded structure 2.Transient Voltage Suppressor 1 is in parallel with Diode series structure 2.Transient Voltage Suppressor 1 and Diode series knot
One end of structure 2 is electrically connected first voltage V1.Transient Voltage Suppressor 1 and the other end of Diode series structure 2 are electrically connected
Second voltage V2.Diode series structure 2 includes first diode 2a and second diode 2b.First diode 2a with
Second diode 2b is electrically connected input/output terminal I/O.First voltage V1 is greater than second voltage V2.In one embodiment,
Two voltage V2 are ground voltage.For example, when there is positive electrostatic event that the input/output terminal (I/ at input/output terminal (I/O) occurs
O) receive positive electrostatic potential so that the cathode voltage of first diode 2a is greater than cathode voltage, first diode 2a at
For forward bias voltage drop state and be connected.Whereby, static discharge current can press down by first diode 2a, then via transient voltage
Device 1 processed.After Transient Voltage Suppressor 1 punctures, then static discharge current can be directed to ground terminal.Due to wink of the invention
The substrate of state voltage suppressor be electrically it is floating, therefore, static discharge current will be transmitted along lateral path, without along
Vertical-path transmission.In this way, which the breakdown voltage (BVceo) of Transient Voltage Suppressor, the reaction of lift elements can be reduced
Speed.
In detail, referring to figure 4., electrostatic protection element of the invention includes Transient Voltage Suppressor 1 and diode
Cascaded structure 2.Transient Voltage Suppressor 1 (as shown in Figure 1) illustrates in above-mentioned paragraph, just repeats no more herein.Diode string
Being coupled structure 2 includes first diode 2a and second diode 2b.Second diode 2b be located at first diode 2a with
Between Transient Voltage Suppressor 1.
First diode 2a includes: that the first wellblock 108 with the first conductive type, the third with the second conductive type are mixed
Miscellaneous area 110 and the 4th doped region 112 with the first conductive type.First wellblock 108 is located in substrate 100.First wellblock 108
Admixture be, for example, boron or boron difluoride, doping concentration can be for example 1 × 1015/cm3To 1 × 1017/cm3.Third doping
Area 110 and the 4th doped region 112 are all located in the first wellblock 108.The admixture of third doped region 110 is, for example, phosphorus or arsenic, and
The doping concentration of three doped regions 110 can be for example 1 × 1020/cm3To 1 × 1022cm3.The admixture of 4th doped region 112 is, for example,
The doping concentration of boron or boron difluoride, the 4th doped region 112 can be for example 1 × 1020/cm3To 1 × 1022/cm3。
Second diode 2b includes: the second wellblock 114 with the second conductive type, the with the second conductive type the 5th mixes
Miscellaneous area 116 and the 6th doped region 118 with the first conductive type.Second wellblock 114 is located in substrate 100.Second wellblock 114
Admixture be, for example, phosphorus or arsenic, the doping concentration of the second wellblock 114 can be for example 1 × 1015/cm3To 1 × 1017/cm3.5th
Doped region 116 and the 6th doped region 118 are all located in the second wellblock 114.The admixture of 5th doped region 116 be, for example, phosphorus or
The doping concentration of arsenic, the 5th doped region 116 can be for example 1 × 1020/cm3To 1 × 1022/cm3.The admixture of 6th doped region 118
The doping concentration of e.g. boron or boron difluoride, the 6th doped region 118 can be for example 1 × 1020/cm3To 1 × 1022/cm3。
First doped region 104 of Transient Voltage Suppressor 1 and the 5th doped region 116 and first of second diode 2b
Voltage V1 is electrically connected.Second doped region 106 of Transient Voltage Suppressor 1 and the 4th doped region of first diode 2a
112 are electrically connected with second voltage V2.First voltage V1 is greater than second voltage V2.In the present embodiment, second voltage V2 is to connect
Ground voltage.And the 6th doped region 118 of the third doped region 110 of first diode 2a and second diode 2b then with it is defeated
Enter/output end I/O electric connection.
In addition, the electrostatic protection element of Fig. 4 can further include isolation structure 10,20,30 in the substrate 100 and
40.Isolation structure 10,20 is located at the two sides of Transient Voltage Suppressor 1.Isolation structure 30,40 is located at the two of first diode 2a
Side, and isolation structure 30 is between first diode 2a and second diode 2b.Isolation structure 10,20,30 and 40
It can avoid the leakage current (Leakage between Transient Voltage Suppressor 1, first diode 2a and second diode 2b
Current).In this way, which it may make electrostatic protection element of the invention to have lower input capacitance, with favorable signal product
Matter is more suitable for the electronic component of high-speed interface application.
Referring to figure 5., the electrostatic protection element of Fig. 5 is similar to Fig. 4 electrostatic protection element, the difference is that: Fig. 5's
Electrostatic protection element further includes that light doped well zone 120 is located at substrate 100 and wellblock 102, the first wellblock 108 and the second wellblock
Between 114.The admixture of light doped well zone 120 is, for example, phosphorus or arsenic, and the doping concentration of light doped well zone 120 can be for example 1 ×
1015/cm3To 1 × 1017/cm3.In the present embodiment, light doped well zone 120 is different from the conductivity type of substrate 100.For example,
When substrate 100 is p-type doping, light doped well zone 120 is n-type doping.
Fig. 6 is the circuit diagram of the electrostatic protection element of third of the present invention and fourth embodiment.Fig. 7 is third of the present invention
The diagrammatic cross-section of the electrostatic protection element of embodiment.Fig. 8 is that the section of the electrostatic protection element of fourth embodiment of the invention shows
It is intended to.
Fig. 6 is please referred to, the present invention provides another electrostatic protection element comprising Transient Voltage Suppressor 1 and two poles
Pipe cascaded structure 3.Transient Voltage Suppressor 1 is in parallel with Diode series structure 3.Diode series structure 3 includes: first two
Pole pipe 3a, second diode 3b, third diode 3c and the 4th diode 3d.Transient Voltage Suppressor 1 and two poles
One end of pipe cascaded structure 3 is electrically connected first voltage V1.The other end of Transient Voltage Suppressor 1 and Diode series structure 3
It is electrically connected second voltage V2.Third diode 3c and the 4th diode 3d is electrically connected input/output terminal I/O.
In detail, Fig. 7 is please referred to, electrostatic protection element of the invention includes Transient Voltage Suppressor 1 and diode
Cascaded structure 3.Transient Voltage Suppressor 1 (as shown in Figure 1) illustrates in above-mentioned paragraph, just repeats no more herein.Diode string
Being coupled structure 3 includes: first diode 3a, second diode 3b, third diode 3c and the 4th diode 3d.The
One diode 3a and the structure of second diode 3b and first diode 2a are similar to the structure of second diode 2b,
Also illustrate in above-mentioned paragraph, just repeat no more herein.Third diode 3c and the 4th diode 3d is all located at first
Between diode 3a and second diode 3b, and the 4th diode 3d is then located at third diode 3c and second two pole
Between pipe 3b.
Third diode 3c includes: the third wellblock 122 with the first conductive type, the with the second conductive type the 7th mixes
Miscellaneous area 124 and the 8th doped region 126 with the first conductive type.The admixture of third wellblock 122 is, for example, boron or bifluoride
Boron, doping concentration can be for example 1 × 1015/cm3To 1 × 1017/cm3.7th doped region 124 and the 8th doped region 126 all positions
In third wellblock 122.The admixture of 7th doped region 124 is, for example, phosphorus or arsenic, and the doping concentration of the 7th doped region 124 can example
In this way 1 × 1020/cm3To 1 × 1022/cm3.The admixture of 8th doped region 126 is, for example, boron or boron difluoride, the 8th doped region
126 doping concentration can be for example 1 × 1020/cm3To 1 × 1022/cm3。
4th diode 3d includes: the 4th wellblock 128 with the second conductive type, the with the second conductive type the 9th mixes
Miscellaneous area 130 and the tenth doped region 132 with the first conductive type.4th wellblock 128 is located in substrate 100.4th wellblock 128
Admixture be, for example, phosphorus or arsenic, the doping concentration of the 4th wellblock 128 can be for example 1 × 1015/cm3To 1 × 1017/cm3.9th
Doped region 130 and the tenth doped region 132 are all located in the 4th wellblock 128.The admixture of 9th doped region 130 be, for example, phosphorus or
The doping concentration of arsenic, the 9th doped region 130 can be for example 1 × 1020/cm3To 1 × 1022/cm3.The admixture of tenth doped region 132
The doping concentration of e.g. boron or boron difluoride, the tenth doped region 132 can be for example 1 × 1020/cm3To 1 × 1022/cm3。
First doped region 104 of Transient Voltage Suppressor 1 and the 5th doped region 116 and first of second diode 3b
Voltage V1 is electrically connected.Second doped region 106 of Transient Voltage Suppressor 1 and the 4th doped region of first diode 3a
112 are electrically connected with second voltage V2.First voltage V1 is greater than second voltage V2.In the present embodiment, second voltage V2 is to connect
Ground voltage.The 9th doped region 130 electric connection of the 6th doped region 118 and the 4th diode 3d of second diode 3b.
And the 7th doped region 124 and input/output terminal of the tenth doped region 132 of the 4th diode 3d and third diode 3c
I/O is electrically connected.The 8th doped region 126 of third diode 3c and the third doped region 110 of first diode 3a are electrical
Connection.
In addition, the electrostatic protection element of Fig. 7 further includes that isolation structure 10 to isolation structure 60 is located in substrate 100.Isolation
Structure 10,60 is located at the two sides of electrostatic protection element.Isolation structure 20 to isolation structure 50 is located at transient voltage suppression
Between device 1 and second diode 3b processed, between second diode 3b and the 4th diode 3d, the 4th diode 3d with
Between third diode 3c and between third diode 3c and first diode 3a.Isolation structure 10 is to isolation structure
60 1, first diode 3a of avoidable Transient Voltage Suppressor, second diode 3b, third diode 3c and the 4th
Leakage phenomenon between a diode 3d occurs.In this way, which it may make electrostatic protection element of the invention with lower
Input capacitance the electronic component of high-speed interface application is more suitable for favorable signal quality.
Fig. 8 is please referred to, the electrostatic protection element of Fig. 8 is similar to Fig. 7 electrostatic protection element, the difference is that: Fig. 8's
Electrostatic protection element further include light doped well zone 120 be located at substrate 100 and wellblock 102, the first wellblock 108, the second wellblock 114,
Between third wellblock 122 and the 4th wellblock 128.The admixture of light doped well zone 120 is, for example, phosphorus or arsenic, light doped well zone
120 doping concentration can be for example 1 × 1015/cm3To 1 × 1017/cm3.In the present embodiment, light doped well zone 120 and substrate
100 conductivity type is different.For example, when light doped well zone 120 be n-type doping, and substrate 100 then for p-type adulterate.
Fig. 9 is the circuit diagram of the Transient Voltage Suppressor array of one embodiment of the invention.
Fig. 9 is please referred to, the present invention provides a kind of Transient Voltage Suppressor array comprising: Transient Voltage Suppressor 1, two
Pole pipe cascaded structure 4 and Diode series structure 5.Diode series structure 4, Diode series structure 5 and transient voltage
Suppressor 1 is parallel with one another.One end of Transient Voltage Suppressor 1 and Diode series structure 4 is electrically connected first voltage V1.Transient state
Voltage suppressor 1 and the other end of Diode series structure 4 are electrically connected second voltage V2.Diode series structure 4 includes the
One diode 4a and second diode 4b.First diode 4a and second diode 4b be electrically connected the first input/
Output end I/O1.Diode series structure 5 includes first diode 5a and second diode 5b.First diode 5a with
Second diode 5b is electrically connected the second input/output terminal I/O2.Although the Transient Voltage Suppressor array packet of the present embodiment
Include two input/output terminals and two Diode series structures.But the present invention is not limited thereto, in other embodiments,
Transient Voltage Suppressor array may also comprise most input/output terminals and most Diode series structures, to meet electricity
The design of subcomponent.
In conclusion Transient Voltage Suppressor of the invention has the first doped region and the second doping of same conductivity
Area.Since the first doped region and first voltage are electrically connected, and the second doped region and second voltage are electrically connected, and therefore, are compared
In the Transient Voltage Suppressor of three pins of the prior art, the area of Transient Voltage Suppressor of the invention is smaller, can mention
Rise the reaction speed of element.In addition, since the substrate of Transient Voltage Suppressor of the invention is electrically floating, electrostatic is put
Electric current will be transmitted along lateral path, without transmitting along vertical-path.In this way, which wink of the invention can be reduced
The breakdown voltage of state voltage suppressor, with the reaction speed of more lift elements.In addition, isolation structure of the invention may make wink
State voltage suppressor and the wellblock of each diode are electrically insulated from each other so that electrostatic protection element of the invention have compared with
Low input capacitance, with promotion signal quality.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (16)
1. a kind of Transient Voltage Suppressor characterized by comprising
The Zener diode of two-way discharge, comprising:
Substrate, the substrate are electrically floating；
Wellblock with the first conductive type is located in the substrate；
The first doped region with the second conductive type is located in the wellblock, and first doped region electrically connects with first voltage
It connects；And
The second doped region with the second conductive type is located in the wellblock, second doped region and second voltage electricity
Property connection.
2. Transient Voltage Suppressor according to claim 1, which is characterized in that first doped region is mixed with described second
Non-grid structure on the wellblock between miscellaneous area.
3. Transient Voltage Suppressor according to claim 1, which is characterized in that further include two isolation structures, be located at institute
State in substrate, wherein first doped region and second doped region be between described two isolation structures, not with it is described
Two isolation structure contacts.
4. Transient Voltage Suppressor according to claim 3, which is characterized in that other than first doped region and
It is identical in the doping concentration of the first conductive type of same depth in the wellblock except second doped region.
5. Transient Voltage Suppressor according to claim 3, which is characterized in that the substrate is dense along the doping of first direction
Degree is wavy curve, and the wavy curve includes:
Most wave crests are located between one of described two isolation structures and first doped region, first doping
Between area and second doped region and second doped region and described two isolation structures it is another between；And
Most troughs, are located in first doped region and second doped region, wherein each trough is located at phase
Between adjacent two wave crests, wherein the most wave crests are alternateed with the most troughs along the first direction.
6. Transient Voltage Suppressor according to claim 1, which is characterized in that other than first doped region and
Not with the doped region of the first conductive type in the wellblock except second doped region.
7. Transient Voltage Suppressor according to claim 1, which is characterized in that when the first conductive type be p-type, it is described
The second conductive type is N-type；When the first conductive type is N-type, the second conductive type is p-type.
8. a kind of electrostatic protection element characterized by comprising
Transient Voltage Suppressor according to any one of claims 1 to 7；And
At least one Diode series structure, it is in parallel with the Transient Voltage Suppressor.
9. electrostatic protection element according to claim 8, which is characterized in that at least one described Diode series structure packet
It includes:
First diode, positioned at the side of the Transient Voltage Suppressor, first diode includes:
The first wellblock with the first conductive type is located in the substrate；
Third doped region with the second conductive type is located in first wellblock；And
The 4th doped region with the first conductive type is located in first wellblock, wherein the 4th doped region and institute
State the electric connection of the second doped region；And
Second diode, between first diode and the Transient Voltage Suppressor, wherein described second
Diode includes:
The second wellblock with the second conductive type is located in the substrate；
The 5th doped region with the second conductive type is located in second wellblock；And
The 6th doped region with the first conductive type is located in second wellblock, wherein the 5th doped region and institute
State the electric connection of the first doped region.
10. electrostatic protection element according to claim 9, which is characterized in that the third doped region is mixed with the described 6th
Miscellaneous area is electrically connected input/output terminal；
5th doped region and first doped region are electrically connected the first voltage；And
4th doped region and second doped region are electrically connected the second voltage, wherein the first voltage is greater than institute
State second voltage.
11. electrostatic protection element according to claim 10, which is characterized in that the second voltage is ground voltage.
12. electrostatic protection element according to claim 9, which is characterized in that at least one described Diode series structure
Include:
Third diode, between first diode and second diode, the third diode
Include:
Third wellblock with the first conductive type is located in the substrate；
The 7th doped region with the second conductive type is located in the third wellblock；And
The 8th doped region with the first conductive type is located in the third wellblock, wherein the 8th doped region and institute
State the electric connection of third doped region；And
4th diode, between the third diode and second diode, wherein described 4th two
Pole pipe includes:
The 4th wellblock with the second conductive type is located in the substrate；
The 9th doped region with the second conductive type is located in the 4th wellblock；And
The tenth doped region with the first conductive type is located in the 4th wellblock, wherein the 9th doped region and institute
State the electric connection of the 6th doped region.
13. electrostatic protection element according to claim 12, which is characterized in that the 7th doped region, the described tenth mix
Miscellaneous area is electrically connected input/output terminal；
5th doped region and first doped region are electrically connected the first voltage；
4th doped region and second doped region are electrically connected the second voltage, wherein the first voltage is greater than institute
State second voltage.
14. electrostatic protection element according to claim 13, which is characterized in that the second voltage is ground voltage.
15. electrostatic protection element according to claim 8, which is characterized in that further include light doped well zone, be located at the lining
Between bottom and the wellblock, wherein the light doped well zone is different from the conductivity type of the substrate.
16. a kind of Transient Voltage Suppressor array characterized by comprising
Transient Voltage Suppressor according to any one of claims 1 to 7；And
At least two Diode series structures, it is in parallel with the Transient Voltage Suppressor,
Wherein one in at least two Diode series structure, with the first input/output terminal be electrically connected, and it is described extremely
Another in two Diode series structures less, is electrically connected with the second input/output terminal.
Applications Claiming Priority (2)
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| TW103144513A TWI658563B (en) | 2014-12-19 | 2014-12-19 | Transient voltage suppressor and esd protection device thereof, and array thereof |
| TW103144513 | 2014-12-19 |
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| US10043793B2 (en) * | 2016-02-03 | 2018-08-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and circuit |
| CN108039347A (en) * | 2018-01-17 | 2018-05-15 | 上海长园维安微电子有限公司 | A kind of integrated ultra-low capacitance returns greatly the common mode filtering device of TVS suddenly |
| US10573635B2 (en) * | 2018-07-23 | 2020-02-25 | Amazing Microelectronics Corp. | Transient voltage suppression device with improved electrostatic discharge (ESD) robustness |
| CN110875304B (en) * | 2018-08-31 | 2022-06-17 | 无锡华润上华科技有限公司 | Transient voltage suppression device and method of manufacturing the same |
| CN109314131B (en) * | 2018-09-05 | 2021-06-08 | 香港应用科技研究院有限公司 | Low capacitance electrostatic discharge (ESD) protection structure with double floating-connected wells |
| US10930637B2 (en) * | 2018-09-06 | 2021-02-23 | Amazing Microelectronic Corp. | Transient voltage suppressor |
| CN109300786B8 (en) * | 2018-10-08 | 2021-12-24 | 电子科技大学中山学院 | Transient voltage suppressor and manufacturing method thereof |
| CN111640740A (en) * | 2020-06-03 | 2020-09-08 | 捷捷微电(上海)科技有限公司 | TVS device and manufacturing method thereof |
| TWI768451B (en) * | 2020-08-31 | 2022-06-21 | 創意電子股份有限公司 | Semiconductor structure and electrostatic discharge protection circuit |
| CN115483206A (en) * | 2021-06-15 | 2022-12-16 | 无锡华润上华科技有限公司 | Electrostatic protection structure and preparation method thereof |
| US20230010423A1 (en) * | 2021-07-06 | 2023-01-12 | Amazing Microelectronic Corp. | Multi-channel transient voltage suppression device |
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| JPH0955471A (en) * | 1995-08-10 | 1997-02-25 | Denso Corp | Surge protective circuit |
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| US8431958B2 (en) * | 2006-11-16 | 2013-04-30 | Alpha And Omega Semiconductor Ltd | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (TVS) |
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| TWI658563B (en) | 2019-05-01 |
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| TW201624664A (en) | 2016-07-01 |
| US20160181236A1 (en) | 2016-06-23 |
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