CN101504916A - Production method for transistor, method for forming channel stop and semi-conductor element - Google Patents
Production method for transistor, method for forming channel stop and semi-conductor element Download PDFInfo
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- CN101504916A CN101504916A CNA2008100054491A CN200810005449A CN101504916A CN 101504916 A CN101504916 A CN 101504916A CN A2008100054491 A CNA2008100054491 A CN A2008100054491A CN 200810005449 A CN200810005449 A CN 200810005449A CN 101504916 A CN101504916 A CN 101504916A
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- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 43
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 43
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims description 47
- 150000002500 ions Chemical class 0.000 claims description 37
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 29
- 230000000694 effects Effects 0.000 description 15
- -1 Phosphonium ion Chemical class 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen(.) Chemical compound [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- VCZQFJFZMMALHB-UHFFFAOYSA-N tetraethylsilane Chemical compound CC[Si](CC)(CC)CC VCZQFJFZMMALHB-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a method for manufacturing a metal oxide semiconductor transistor, which comprises the following steps: firstly, providing a substrate, and forming a first conductive well region on the substrate; secondly, forming a grid structure on the substrate of the first conductive well region, and forming a second conductive source/drain region on the substrate on two sides of the grid structure; and thirdly, performing a process of first conductive ion implantation on the substrate, and forming a first conductive doped region in the substrate under the second conductive source/drain region by penetrating the grid structure, wherein the depth of the first conductive doped region is larger than that of the first conductive well region.
Description
Technical field
The invention relates to a kind of manufacture method and structure of integrated circuit, and particularly relevant for a kind of manufacture method of metal oxide semiconductor transistor, the method that the formation raceway groove blocks, and a kind of semiconductor element.
Background technology
Flourish along with integrated circuit, the kind of electronic product is also more and more various, in order to meet the demand of various products, except general low voltage component, also need can tolerating high voltage high voltage device.High voltage device generally is meant the element that can tolerate 20～200 volts of high pressure.
On the other hand, because the size of semiconductor element is dwindled day by day, the channel length of element also can and then shorten, for high voltage device, the high voltage that puts on the high voltage device grid can improve the intensity of raceway groove electric field, and produces gate induced drain leakage (GIDL) effect.Because the energy of electronics strengthens in the raceway groove, be easy to cause the phenomenon of electrical breakdown (Electrical Breakdown), cause the puncture voltage of high voltage device to descend, reduce the reliability of element.
In addition, please refer to Fig. 2, in order to prevent electric leakage or the short circuit between the high voltage device 245, except using isolation structure 210, also can be below high voltage device 245 and isolation structure 210, form the doped region 260 of a whole layer and source/drain regions 240 opposite conductivity types, the generation that suppresses to leak electricity.Yet the formation of this layer doped region 260 can be strengthened bulk effect (Body Effect), causes the threshold voltage (Threshold Voltage) of element to raise, and increases the power consumption of element, and reduces the yield of product.
Summary of the invention
The invention provides a kind of manufacture method of metal oxide semiconductor transistor, can suppress the generation of gate induced drain leakage in the substrate, improve transistorized puncture voltage, can also reduce bulk effect, obtain yield height, the good metal oxide semiconductor transistor of element efficiency.
The invention provides a kind of method that raceway groove blocks that forms, penetrate high voltage device and carry out the ion injection, only in the source/drain regions below, the light doping section of formation and source/drain regions opposite conductivity type, and be minimized the harmful effect that bulk effect produces high voltage device.
The present invention proposes a kind of manufacture method of metal oxide semiconductor transistor, and the method for example is that substrate is provided earlier, forms the first conductivity type well region in substrate.Then, in the substrate of the first conductivity type well region, form grid structure.And in the grid structure substrate on two sides, form second conductivity type source electrode/drain region.Then, the first conduction type ion injection technology is carried out in substrate, penetrate grid structure and form the first conductivity type doped region in the substrate of second conductivity type source electrode/below, drain region, wherein the degree of depth of the first conductivity type doped region is greater than the degree of depth of the first conductivity type well region.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor wherein has been formed with a plurality of isolation structures in the substrate, and the first conductivity type well region is arranged in the substrate between the isolation structure.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein the first conductivity type doped region extends in the substrate of isolation structure below.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein the implantation concentration of the first conduction type ion injection technology is between 10
11～10
12Ions/cm
2Between.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein the injection energy of the first conduction type ion injection technology is according to gate structure height and the substrate isolation structure degree of depth and decide.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor also is included in the process that forms second conductivity type source electrode/drain region, forms the light doped region of one first conductivity type among second conductivity type source electrode/drain region.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor also is included in and carries out forming one second conductivity type contact areas in second conductivity type source electrode/top, drain region after the first conduction type ion injection technology.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein the ion concentration of the second conductivity type contact areas is greater than the ion concentration of second conductivity type source electrode/drain region.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein grid structure from bottom to top comprises a gate dielectric layer and a grid.The material of grid for example is a polysilicon.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein grid structure also comprises a metal silicide layer, is arranged on the grid.
In one of the present invention embodiment, the manufacture method of above-mentioned metal oxide semiconductor transistor, wherein first conductivity type is the P type, second conductivity type is the N type.
The manufacture method of above-mentioned metal oxide semiconductor transistor because of among second conductivity type source electrode/drain region, forms the doped region of opposite conductivity type, can improve the puncture voltage of metal oxide semiconductor transistor; In addition, the transmission grating electrode structure has formed the first conductivity type doped region below second conductivity type source electrode/drain region, can also reach the advantage that reduces bulk effect and keep threshold voltage.
A kind ofly form the method that raceway groove blocks, be applicable to a substrate, be formed with a plurality of isolation structures in the substrate, be formed with high voltage device between the isolation structure, high voltage device comprises source.The method for example is to penetrate high voltage device, and an ion implantation technology is carried out in substrate, forms a light doping section in the source/drain regions below, and wherein, the conductivity type of ion implantation technology is opposite with the conductivity type of source/drain regions.
In one of the present invention embodiment, the method that above-mentioned formation raceway groove blocks, light doping section also comprises in the substrate that extends to the isolation structure below.
In one of the present invention embodiment, the method that above-mentioned formation raceway groove blocks, wherein the degree of depth of light doping section is greater than the degree of depth of source/drain regions.
In one of the present invention embodiment, the method that above-mentioned formation raceway groove blocks also is included in before the formation high voltage device, forms a well region in the substrate between isolation structure, and well region has identical conductivity type with light doping section.
In one of the present invention embodiment, the method that above-mentioned formation raceway groove blocks, wherein the degree of depth of well region is less than the degree of depth of light doping section.
In one of the present invention embodiment, the method that above-mentioned formation raceway groove blocks, wherein high voltage device comprises high voltage most.
The present invention proposes a kind of semiconductor element, comprises substrate, well region, grid structure, source/drain regions and doped region.Be formed with a plurality of isolation structures in the substrate, well region is arranged in the substrate between the isolation structure, and grid structure is arranged in the substrate between the isolation structure.Source/drain regions is arranged in the well region of grid structure both sides.Doped region only is arranged in the substrate of source/drain regions below, and the degree of depth of doped region is greater than the degree of depth of source/drain regions, well region, and doped region with have identical conductivity type with well region, then have opposite conductivity type with source/drain regions.
In one of the present invention embodiment, above-mentioned semiconductor element, wherein doped region extends in the substrate of isolation structure below.
In one of the present invention embodiment, above-mentioned semiconductor element, wherein grid structure from bottom to top comprises gate dielectric layer and grid.
In one of the present invention embodiment, above-mentioned semiconductor element, wherein the material of grid comprises polysilicon.
In one of the present invention embodiment, above-mentioned semiconductor element, wherein grid structure also comprises the layer of metal silicide layer, is arranged on the grid.
The method that above-mentioned formation raceway groove blocks, in substrate with isolation structure and high voltage device, carrying out ion injects, and below source/drain regions and isolation structure, form doped region, both can block the undesired conducting situation that produces electric leakage, short circuit between the adjacent high voltage device, also help to reduce the influence of bulk effect high voltage device.
State feature and advantage on the present invention and can become apparent for allowing, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process profile that illustrates a kind of metal oxide semiconductor transistor of one embodiment of the invention.
Fig. 2 is the section of structure that illustrates known high voltage device.
The main element symbol description
100,200: substrate 110,210: isolation structure
120: the first conductivity type well regions 130: grid structure
133: gate dielectric layer 135: grid
137: metal silicide layer 139: clearance wall
140,240: the second conductivity type source electrode/drain region 140a: the light doped region of first conductivity type
145: 150: the first conduction type ions of metal oxide semiconductor transistor inject
160: the first conductivity type doped regions 163: interlayer dielectric layer
165: 170: the second conductivity type contact areas in contact hole
245: high voltage device 260: doped region
Embodiment
Figure 1A to Fig. 1 C is the manufacturing process profile that illustrates a kind of metal oxide semiconductor transistor of one embodiment of the invention.
Please refer to Figure 1A, substrate 100 at first is provided, substrate 100 for example is silicon base, SOI (siliconon insulator) substrate or three-five families semiconductor-based ends.Substrate 100 for example is substrate of P type or the substrate of N type.Then, in substrate 100, form isolation structure 110.Isolation structure 110 for example is fleet plough groove isolation structure (STI).Certainly, isolation structure 110 also can be a field oxide (FOX).It is known that the formation method of isolation structure 110 should be those skilled in the art institute, repeats no more in this.Then, form the first conductivity type well region 120 in the substrate between isolation structure 110 100.The formation method of the first conductivity type well region 120 for example is thermal diffusion method or ion implantation technology.The first conductivity type well region 120 for example is to contain boron, BF
2Or the P type doped region of indium, also can be the N type doped region that contains phosphorus, arsenic.
Then, please refer to Figure 1B, form a high voltage device in the substrate 100 of the first conductivity type well region 120, this high voltage device for example is can tolerate between 20～200 volts.In the present embodiment, high voltage device herein for example is a metal oxide semiconductor transistor 145.For example be to form grid structure 130 earlier in the step of formation metal oxide semiconductor transistor 145.Grid structure 130 from bottom to top for example is made up of gate dielectric layer 133 and grid 135.Grid 135 for example is prior to forming one deck gate dielectric layer material layer (not illustrating) and one deck gate material layers (not illustrating) in the substrate 100, forming with the etched mode patterning of photoetching above-mentioned material layer then with the formation method of gate dielectric layer 133.Wherein the material of gate dielectric layer 133 for example is a silica, and the material of grid 135 for example is a doped polycrystalline silicon.Grid 135 tops more can be to be formed with layer of metal silicide layer 137, to reduce the resistance of grid 135.The formation method of metal silicide layer 137 can be a chemical vapour deposition technique, or aims at metal silicide (self-aligned silicide) technology voluntarily, and its material for example is titanium silicide, cobalt silicide, tungsten silicide or tantalum silicide etc.Afterwards, can also form clearance wall 139 in grid structure 130 both sides, the material of clearance wall 139 for example is dielectric materials such as silica, its formation method for example is prior to forming the spacer material layer of a whole layer in the substrate 100, utilize the dry-etching method then, remove part spacer material layer, form clearance wall 139 in grid structure 130 both sides.
Next, please refer to Fig. 1 C, in the first conductivity type well region 120 of grid structure 130 both sides substrates 100, form second conductivity type source electrode/drain region 140.Metal oxide semiconductor transistor 145 has been formed in grid structure 130 and second conductivity type source electrode/drain region 140.Metal oxide semiconductor transistor 145 for example is to tolerate about high voltage more than 20 volts.The method that forms second conductivity type source electrode/drain region 140 for example is to carry out the multiple tracks ion implantation technology, utilizes different implantation concentrations, different inject energy and form dense doped region with the first conductivity type well region, 120 different conductivity types.Second conductivity type source electrode/drain region 140 for example is the doped region of N type or P type, and is opposite with the conductivity type of the first conductivity type well region 120.For instance, the first conductivity type well region 120 is the P type, and 140 of second conductivity type source electrode/drain regions are the N type, if the first conductivity type well region 120 is the N type, then second conductivity type source electrode/drain region 140 is exactly the P type.In one embodiment, second conductivity type source electrode/drain region 140 for example is a N type doped region, and its formation method for example is that concentration 10 is provided earlier
12Ions/cm
2Phosphonium ion, with energy 70keV ion is carried out in substrate 100 and injects.Then with concentration 10
15Ions/cm
2Nitrogen molecular, under the condition of injecting energy 20keV, substrate 100 is injected.Be energy 50keV, concentration 10 afterwards again with the injection condition
15Ions/cm
2Phosphonium ion, flow in the substrate 100.An injection condition carries out the ion injection on the triplicate then.Afterwards then to inject energy 35keV, implantation concentration 2.5 * 10
12Ions/cm
2Arsenic ion ions are injected in substrate 100, finish this second conductivity type source electrode/drain region 140.
What pay special attention to is in the process that forms second conductivity type source electrode/drain region 140, can also add first conduction type ion injection together, the light doped region 140a of formation first conductivity type among second conductivity type source electrode/drain region 140.For instance, in above-mentioned concentration 10
12Ions/cm
2, energy 70keV phosphonium ion inject after, with concentration 10
12Ions/cm
2, energy 80keV BF
2Ion carries out ion and injects, and forms the light doped region 140a of first conductivity type among second conductivity type source electrode/drain region 140, just carries out then.The light doped region 140a of first conductivity type can produce the face that connects of different conductivity type among second conductivity type source electrode/drain region 140, and then can reach suppressor grid and bring out drain leakage (GIDL) effect, and the effect that improves metal oxide semiconductor transistor 145 puncture voltages.
Then, please refer to Fig. 1 C, the first conduction type ion injection technology 150 is carried out in substrate 100, these ion penetrations grid structure 130 (perhaps also can be described as and penetrate whole metal oxide semiconductor transistor 145), in the substrate 100 of 140 belows, second conductivity type source electrode/drain region, form the first conductivity type doped region 160.The injection condition of the first conduction type ion injection technology 150 for example is that the injection energy is between 100～150keV, and implantation concentration is 10
11～10
12Ions/cm
2Between, for example be 2.5 * 10
11～7.5 * 10
11Ions/cm
2Between.In one embodiment, the first conduction type ion injection technology 150 for example is with concentration 5 * 10
11The boron ion, under the condition of injecting energy 100keV, substrate 100 is injected.The injection energy of the first conduction type ion injection technology can be according to the height of grid structure 130 and substrate 100 isolation structures, 110 degree of depth and decide
When carrying out the first conduction type ion injection technology, carry out owing to penetrating whole metal oxide semiconductor transistor 145, and the material of grid structure 130 includes conductor material, therefore, the ion that penetrates grid structure 130 and inject, the ion that injects with penetrating second conductivity type source electrode/drain region 140, the zone that both distribute is difference to some extent.Wherein, the ion that penetrates grid structure 130 can be injected in the raceway groove of grid structure 130 below substrates 100.And be not subjected to ion that grid structure 130 stops (that is, penetrate second conductivity type source electrode/drain region 140) then can be distributed in substrate 100 than the depths.In one embodiment, the degree of depth of the first conductivity type doped region 160 for example is the degree of depth greater than the first conductivity type well region 120.The first conductivity type doped region 160 more can be to extend to isolation structure 110 belows.
Please refer to Fig. 1 D, form after the first conductivity type doped region 160, can also be to form one deck interlayer dielectric layer 163 in substrate 100 earlier.The material of interlayer dielectric layer 163 for example is to be gas source with tetraethyl silane (TEOS), utilizes the formed silica of chemical vapour deposition technique, boron-phosphorosilicate glass (BPSG) or fluorine silex glass etc.Then, utilize the photoetching etching method to remove part interlayer dielectric layer 163, form the contact hole 165 that exposes part second conductivity type source electrode/drain region 140.
Then, can carry out second conduction type ion and inject, form the second conductivity type contact areas 170 at 140 tops, second conductivity type source electrode/drain region that expose.It for example is to inject energy 30keV, concentration 10 that second conduction type ion that forms the second conductivity type contact areas 170 injects
14Phosphonium ion carry out.The ion concentration of the second conductivity type contact areas 170 for example is the ion concentration greater than second conductivity type source electrode/drain region.As for the follow-up intraconnections of finishing, the method for grid structure 130, second conductivity type source electrode/drain region 140 that connects metal oxide semiconductor transistor 145 is known by those skilled in the art, does not give unnecessary details in this.
Said method is forming grid structure with after second conductivity type source electrode/drain region, penetrates grid structure 130 and has carried out first conduction type ion injection 150, and formed the first conductivity type doped region 160 in 140 belows, second conductivity type source electrode/drain region.This first conductivity type doped region 160 can extend to isolation structure 110 belows, but the first conductivity type doped region 160 can't extend to grid structure 130 belows, thus, reduce the influence that bulk effect caused with helping, make the threshold voltage of metal oxide semiconductor transistor 145 can maintain the following of control, and improve the yield of product.
In addition, the light doped region 140a of formed first conductivity type among second conductivity type source electrode/drain region 140 can produce exhaustion region among second conductivity type source electrode/drain region 140, thereby suppressor grid brings out drain leakage (GIDL) effect.In other words, the highfield that high pressure caused that puts on metal oxide semiconductor transistor 145 can be suppressed, the puncture voltage of metal oxide semiconductor transistor 145 also can promote thereupon, and then improves the reliability of metal oxide semiconductor transistor 145.
Certainly, though present embodiment is to be that example is done explanation with the metal oxide semiconductor transistor, but the method that raceway groove proposed by the invention blocks is not limited to be used in the manufacturing process of metal oxide semiconductor transistor, other high voltage devices such as memory component or other logic elements equally also can use method of the present invention, and reach the effect that reduces bulk effect.The method that formation raceway groove proposed by the invention blocks after forming high voltage device, penetrates high voltage device and has carried out the ion injection, and has formed light doping section in the source/drain regions below of high voltage device.Because the conductivity type of light doping section is opposite with source/drain regions, and light doping section only is formed on source/drain regions and isolation structure below, rather than one whole layer be formed on below the high voltage device, both can take into account the advantage of isolating adjacent high voltage device, can reduce bulk effect again, and then control saturation current effectively, and obtain preferred threshold voltage.This is for the power consumption of the yield that improves high voltage device, minimizing element, and it is also very helpful to reduce its mortality (failure rate).
The invention allows for a kind of semiconductor element.Please refer to Fig. 1 C, element includes substrate 100, grid structure 145, second conductivity type source electrode/drain region 140 and the first conductivity type doped region 160.A plurality of isolation structures 110 have been formed with in the substrate 100.Isolation structure 110 for example is fleet plough groove isolation structure (STI), or field oxide (FOX).For example be to be provided with the first conductivity type well region 120 between the isolation structure 110.The first conductivity type well region 120 for example is a P type doped region, contains boron, BF
2Or P type admixture such as indium.The first conductivity type well region 120 also can be a N type doped region, contains N type admixtures such as phosphorus, arsenic.In one embodiment, the first conductivity type well region 120 for example is to contain BF
2, concentration is 10
12Ions/cm
2P type doped region.
Second conductivity type source electrode/drain region 140 is arranged at grid structure 145 both sides.Second conductivity type source electrode/drain region 140 can be P type or N type.If the first conductivity type well region 120 is the P type, 140 of second conductivity type source electrode/drain regions are the N type, if the first conductivity type well region 120 is the N type, then second conductivity type source electrode/drain region 140 is exactly the P type.In one embodiment, second conductivity type source electrode/drain region 140 for example is the N type doped region that is doped with arsenic, and dopant concentration is 10
15Ions/cm
2
The first conductivity type doped region 160 is arranged in the substrate 100.The degree of depth of the first conductivity type doped region 160 is greater than the degree of depth of second conductivity type source electrode/drain region 140, and the degree of depth of the first conductivity type doped region 160 is also greater than the degree of depth of the first conductivity type well region 120.And be noted that especially 160 of the first conductivity type doped regions are arranged in the substrate 100 of 145 belows, second conductivity type source electrode/drain region, and can not be arranged at the below of grid structure 145
The first conductivity type doped region 160 can be the below that extends to isolation structure 110 more, makes the different elements of isolation structure 110 left and right sides, can isolate mutually, avoids electric leakage or situation of short circuit between the element.The first conductivity type doped region 160 can be P type doped region or N type doped region.In one embodiment, the first conductivity type doped region 160 for example is the P type doped region of boron ion of having mixed, and the concentration of boron ion for example is 10
11Ions/cm
2
In the above-mentioned semiconductor element, in the substrate below source/drain regions doped region is set, and extends to the isolation structure below at the most, and can not be arranged at below the grid structure.Thus, not only can reach the function of isolating adjacent elements, avoid electric leakage or situation of short circuit, also can reduce the influence of bulk effect, and then reduce the power consumption of element, improve the usefulness of element.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; technical staff in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (20)
1. the manufacture method of a metal oxide semiconductor transistor comprises:
One substrate is provided;
In this substrate, form one first conductivity type well region;
In this substrate of this first conductivity type well region, form a grid structure;
In this substrate of these grid structure both sides, form one second conductivity type source electrode/drain region; And
The first conduction type ion injection technology is carried out in this substrate, this first conduction type ion injection technology penetrates this grid structure, form one first conductivity type doped region in this substrate below this second conductivity type source electrode/drain region, wherein the degree of depth of this first conductivity type doped region is greater than the degree of depth of this first conductivity type well region.
2. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1 wherein has been formed with a plurality of isolation structures in this substrate, and this first conductivity type well region is arranged in this substrate between the described isolation structure.
3. the manufacture method of metal oxide semiconductor transistor as claimed in claim 2, wherein this first conductivity type doped region extends in this substrate of this isolation structure below.
4. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1, wherein the implantation concentration of this first conduction type ion injection technology is between 10
11～10
12Between the ions/cm2.
5. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1, wherein the injection energy of this first conduction type ion injection technology is according to this gate structure height and this isolation structure degree of depth of this substrate and decide.
6. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1 also comprises, in the process that forms this second conductivity type source electrode/drain region, forms the light doped region of one first conductivity type among this second conductivity type source electrode/drain region.
7. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1 also comprises, after carrying out this first conduction type ion injection technology, forms one second conductivity type contact areas at this second conductivity type source electrode/top, drain region.
8. the manufacture method of metal oxide semiconductor transistor as claimed in claim 7, wherein the ion concentration of this second conductivity type contact areas is greater than the ion concentration of this second conductivity type source electrode/drain region.
9. the manufacture method of metal oxide semiconductor transistor as claimed in claim 1, wherein this first conductivity type is the P type, this second conductivity type is the N type.
10. one kind forms the method that raceway groove blocks, and is applicable to a substrate, has been formed with a plurality of isolation structures in this substrate, and is formed with a high voltage device between the described isolation structure, and this high voltage device comprises source, and this method comprises:
An ion implantation technology is carried out in this substrate, penetrate this high voltage device, form a light doping section below this source/drain regions, wherein, the conductivity type of this ion implantation technology is opposite with the conductivity type of this source/drain regions.
11. as the method that the formation raceway groove of claim 10 blocks, wherein this light doping section also extends in this substrate of this isolation structure below.
12. as the method that the formation raceway groove of claim 10 blocks, wherein the degree of depth of this light doping section is greater than the degree of depth of this source/drain regions.
13. the method as the formation raceway groove of claim 10 blocks also comprises, before forming this high voltage device, forms a well region in this substrate between described isolation structure, this well region has identical conductivity type with this light doping section.
14. as the method that the formation raceway groove of claim 13 blocks, wherein the degree of depth of this well region is less than the degree of depth of this light doping section.
15. as the method that the formation raceway groove of claim 10 blocks, wherein this high voltage device comprises high voltage most.
16. a semiconductor element comprises:
One substrate has been formed with a plurality of isolation structures in this substrate;
One well region is arranged in this substrate between the described isolation structure;
One grid structure is arranged in this substrate between the described isolation structure;
Source is arranged in this well region of these grid structure both sides; And
One doped region, only be arranged in this substrate of this source/drain regions below, the degree of depth of this doped region is greater than the degree of depth of this source/drain regions, this well region, and this doped region has identical conductivity type with this well region, then has opposite conductivity type with this source/drain regions.
17. as the semiconductor element of claim 16, wherein this doped region extends in this substrate of this isolation structure below.
18. as the semiconductor element of claim 16, wherein this grid structure from bottom to top comprises a gate dielectric layer and a grid.
19. as the semiconductor element of claim 18, wherein the material of this grid comprises polysilicon.
20. as the semiconductor element of claim 18, wherein this grid structure also comprises a metal silicide layer, is arranged on this grid.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100054491A CN101504916A (en) | 2008-02-04 | 2008-02-04 | Production method for transistor, method for forming channel stop and semi-conductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100054491A CN101504916A (en) | 2008-02-04 | 2008-02-04 | Production method for transistor, method for forming channel stop and semi-conductor element |
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| CN101504916A true CN101504916A (en) | 2009-08-12 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106562767A (en) * | 2016-11-04 | 2017-04-19 | 深圳大学 | Sweat detection system and manufacturing method therefor |
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
-
2008
- 2008-02-04 CN CNA2008100054491A patent/CN101504916A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106562767A (en) * | 2016-11-04 | 2017-04-19 | 深圳大学 | Sweat detection system and manufacturing method therefor |
| CN113540223A (en) * | 2020-04-22 | 2021-10-22 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
| CN113540223B (en) * | 2020-04-22 | 2023-11-10 | 力晶积成电子制造股份有限公司 | Insulated gate field effect bipolar transistor and manufacturing method thereof |
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