CN105979174B - A kind of filter network system and image processing system - Google Patents
A kind of filter network system and image processing system Download PDFInfo
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- CN105979174B CN105979174B CN201610293859.5A CN201610293859A CN105979174B CN 105979174 B CN105979174 B CN 105979174B CN 201610293859 A CN201610293859 A CN 201610293859A CN 105979174 B CN105979174 B CN 105979174B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
The invention discloses a kind of filter network system and image processing system, which includes：Several Gauss multipliers；Output circuit, output circuit is separately connected with several Gauss multipliers, wherein, Gauss multiplier includes the first differential pair tube and the second differential pair tube and third differential pair tube that are separately connected with the first differential pair tube, the output end of the first transistor is separately connected the input terminal of two transistor in the second differential pair tube in first differential pair tube, the output end of second transistor is separately connected the input terminal of two transistor in third differential pair tube in first differential pair tube, the input terminal of the first transistor and the input terminal of second transistor are in parallel, the output end of two transistor is connect with output circuit respectively in the output end of two transistor and third differential pair tube in second differential pair tube.The present invention realizes Gaussian convolution filtering processing by simulation Gauss multiplier, and Gaussian convolution filtering speed can be improved, and reduces circuit power consumption.
Description
Technical field
The present invention relates to technical field of image processing, specifically, being related to a kind of filter network system and image procossing system
System.
Background technique
In Digital Signal Processing, convolutional filtering is a very important step in Signal Pretreatment.In image procossing
Field, Gaussian convolution filter are a kind of smoothing filters, and effect is to obtain the higher image of Signal to Noise Ratio (SNR), and avoid figure
The ringing of picture.In traditional digital image processing system, imaging sensor acquired image information passes through simulation number
Word converter ADC is converted to digital signal, carries out subsequent filtering processing using Digital Signal Processing DSP technology.
But with the development of image sensing technology, acquired image resolution ratio is significantly promoted, so that multiple dimensioned
The continuous scale of gaussian filtering, which is expanded, leads to sharply increasing for data volume and operand, and conventional digital system is increasingly difficult to meet
Demand of the image processing system for real-time and power consumption.The especially embedded systems such as portable equipment and wearable device,
At high speed, miniaturization and super low-power consumption in terms of design requirement it is higher, be more difficult to meet demand index.
In real image processing, gaussian filtering is to carry out convolution realization by image data and Gaussian template.Convolution
Operation is actually a series of multiplication and add operation.But due to each of image pixel and its particular size
Neighborhood will all participate in multiply-add operation, therefore when picture size is big, clarity is high, it is necessary to carry out a large amount of duplicate Gaussian convolutions
Operation.And this operation is indispensable a part in many image processing algorithms, such as Image Edge-Detection and enhancing,
Spot detection and scale invariant feature extraction algorithm etc. require to carry out certain scale to input picture in pretreatment stage
Or multiple dimensioned gaussian filtering.
By taking SIFT algorithm the most classical in image characteristics extraction algorithm as an example, which realizes the main bottle of real-time operation
Neck is that the foundation of gaussian pyramid, i.e., the part of multiple dimensioned Gaussian filter operation.Experiment shows that the algorithm is realized in FPGA
In, the time of gaussian filtering expensive component accounts for the 85.63% of total algorithm operation time.Therefore, for scan picture system
System, especially for Embedded Image Processing System, effectively accelerates multiple dimensioned gaussian filtering and reduces power consumption to be very necessary.
Summary of the invention
In order to solve the above problem, the present invention provides a kind of filter network system and image processing systems, to accelerate height
This filters and reduces circuit power consumption.
According to an aspect of the present invention, the present invention provides a kind of filter network systems, including：
Several Gauss multipliers；
Output circuit, the output circuit are separately connected with several Gauss multipliers,
Wherein, the Gauss multiplier include the first differential pair tube and be separately connected with first differential pair tube second
Differential pair tube and third differential pair tube, it is poor to be separately connected described second for the output end of the first transistor in first differential pair tube
Divide the input terminal to two transistor in pipe, the output end of second transistor is separately connected the third in first differential pair tube
The input terminal of the input terminal of two transistor in differential pair tube, the input terminal of the first transistor and the second transistor is simultaneously
Join, the output end of two transistor is distinguished in the output end and the third differential pair tube of two transistor in second differential pair tube
It is connect with the output circuit.
According to one embodiment of present invention, in second differential pair tube and the third differential pair tube in two transistor
The switch terminals of one transistor are connect with the switch terminals of the first transistor respectively, the switch terminals of another transistor respectively with it is described
The switch terminals of second transistor connect, the control voltage of the switch terminals by controlling the second transistor, so that described first
Differential pair tube, second differential pair tube and third differential pair tube work are in sub-threshold region.
According to one embodiment of present invention, the output circuit includes the mirror being made of the two transistor of switch terminals connection
Image current source, the input terminal of a transistor of the mirror current source respectively in second differential pair tube with described second
The switch terminals with the first transistor in the output end of transistor of transistor switch end connection, the third differential pair tube
The output end of the transistor of connection is connected with the switch terminals of two transistor in the mirror current source.
According to one embodiment of present invention, the output circuit further includes a symmetrical transistor, the symmetrical transistor
Respectively with the output end of the transistor being connect with the first transistor switch terminals in second differential pair tube and described
The output end of the transistor connecting with the switch terminals of the second transistor in three differential pair tubes connects.
According to another aspect of the present invention, a kind of image processing system is additionally provided, including：
Filter network system described in any of the above item；
Cmos image sensor, the photoelectric current of each pixel unit output passes through in corresponding first differential pair tube thereon
The input terminal of the first transistor and the second transistor enters the filter network system.
According to one embodiment of present invention, described image processing system further includes template storage and deposits with the template
The digital analog converter of reservoir connection, template, filter scale and the Gauss multiplier based on template storage storage
Transfer function calculates the control voltage of the switch terminals of the second transistor, and the control voltage is converted through the analog-digital converter
It is output after analog signal to the Gaussian convolution filter network system.
According to one embodiment of present invention, the quantity of Gauss multiplier is equal to the template in the filter network system
Number of pixel cells needed for the template stored in memory.
According to one embodiment of present invention, described image processing system further includes sensing respectively with the cmos image
The input terminal and second crystal of the first transistor in first differential pair tube described in device, the filter network system
The read-out control circuit of the input terminal connection of pipe, is flowed into the photoelectricity exported to pixel unit each in the cmos image sensor
The serial filtering of row.
According to one embodiment of present invention, the filter network system integration is in the cmos image sensor.
According to one embodiment of present invention, the filter network system is arranged outside the cmos image sensor, and
Photooptical data is read by the output port of the cmos image sensor.
Beneficial effects of the present invention：
The present invention realizes Gaussian convolution filtering processing by simulation Gauss multiplier, and Gaussian convolution filtering speed can be improved
Degree reduces circuit power consumption.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can be by specification, right
Specifically noted structure is achieved and obtained in claim and attached drawing.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is required attached drawing in technical description to do simple introduction：
Fig. 1 is a kind of filter network system structure diagram according to an embodiment of the invention；
Fig. 2 a is the connection schematic diagram of a Gauss multiplier and output circuit according to an embodiment of the invention；
Fig. 2 b is the contrast schematic diagram of the transfer function of Gauss multiplier and Gaussian function in Fig. 2 a；
Fig. 3 is that the image processing system according to an embodiment of the invention using one-dimensional filtering network system shows
It is intended to；
The company of cmos image sensor and filter network system when Fig. 4 is for using one-dimensional filtering network shown in Fig. 3
Connect schematic diagram；
Fig. 5 is the image signal process of the 2-d gaussian filters circuit according to an embodiment of the invention using 3x3
Schematic diagram；And
Fig. 6 is image processing system schematic diagram according to another embodiment of the present invention.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to apply to the present invention whereby
Technological means solves technical problem, and the realization process for reaching technical effect can fully understand and implement.It needs to illustrate
As long as not constituting conflict, each feature in each embodiment and each embodiment in the present invention can be combined with each other,
It is within the scope of the present invention to be formed by technical solution.
As shown in Figure 1 it is a kind of filter network system structure diagram according to one embodiment of the present of invention, joins below
Examining Fig. 1, the present invention is described in detail.
The filter network system includes several Gauss multipliers 10 and the output being separately connected with several Gauss multipliers electricity
Road 20.Wherein, the Gauss multiplier 10 include the first differential pair tube 11 and be separately connected with the first differential pair tube 11 it is second poor
Point to pipe 12 and third differential pair tube 13, it is poor to be separately connected second for the output end of the first transistor 111 in the first differential pair tube 11
Divide the input terminal to two transistor in pipe 12, the output end of second transistor 112 is separately connected third in the first differential pair tube 11
The input terminal of the input terminal of two transistor in differential pair tube 13, the input terminal of the first transistor 111 and second transistor 112 is simultaneously
Connection, in the second differential pair tube 12 in the output end and third differential pair tube 13 of two transistor the output end of two transistor respectively with it is defeated
Circuit 20 connects out.
As shown in Figure 2 a for according to the company of a Gauss multiplier 10 and output circuit 20 of one embodiment of the present of invention
Connect schematic diagram.In circuit work, by controlling the voltage V+ and V- of three differential pair tube switch terminals, so that tail current IinIt is logical
The input terminal for the first transistor 111 crossed in the first differential pair tube 11 and the input terminal of second transistor 112 enter the Gauss and multiply
Musical instruments used in a Buddhist or Taoist mass exports after Gauss multiplier processing to output circuit 20, and exports electric current Iout through output circuit 20.
By Fig. 2 a it is found that in the Gauss multiplier 10, the first differential pair tube 11 and 12 head and the tail phase of the second differential pair tube
Connect, the first differential pair tube 11 and third differential pair tube 13 it is end to end, the second differential pair tube 12 and third differential pair tube 13 export
End is in parallel.The nearly Gauss transfer characteristic function that Gauss multiplier 10 is generated using MOS differential pair tube, can be with as gaussian kernel function
Being multiplied for tail current and gaussian kernel function is realized in analog domain.Specifically, the Gauss multiplier is using work in sub-threshold region
The Sigmoid transfer characteristic that MOS differential pair tube generates, differential pair tube as two groups is end to end, so that two centers pair
The Sigmoid function of title is multiplied, and obtains hyperbolic secant chi square function.The hyperbolic secant chi square function is very close high in shape
This function, as shown in Figure 2 b.Therefore, the not instead of standard gaussian characteristic which is constituted, a kind of nearly Gauss transfer characteristic should
Function is very close with Gaussian function in mathematical property, i.e., meets Gauss from the result still approximation of convolution sum Fourier transformation
Characteristic.It, can as long as the output of several Gauss mlultiplying circuits is connected directly since the Gauss multiplier is current analog circuit
Realize the add operation in Gaussian convolution filtering operation.As shown in Figure 1, by tail current I-2、I-1、I0、I1, I2Corresponding Gauss multiplies
Musical instruments used in a Buddhist or Taoist mass output end is connected in parallel, and output electric current is：
Add operation then may be implemented.Therefore, Gaussian convolution filtering may be implemented in filter network system described in Fig. 1.
It is using the advantage that the analog filtering network system of Fig. 1 carries out image filtering, since original analog information
Carry out the signal processing of analog domain, perception and calculating process closer and similar to organism itself.This process avoids
Conversion process from analog to digital domain, but spontaneous physical computing is carried out using the stabilization process of establishing of physical device.Phase
It is this especially in terms of the complicated calculations process such as multiplication and division operation, exponent arithmetic and floating-point operation than in Digital Signal Processing
Physical computing mode realizes in speed to be surmounted.
In one embodiment of the invention, the second differential pair tube 12 and third differential pair tube 13 the two in pipe respectively
Two transistor in the switch terminals of a transistor connect respectively with the switch terminals of the first transistor 111, the switch of another transistor
End is connect with the switch terminals of second transistor 112 respectively, and the control voltage of the switch terminals by controlling second transistor 112 makes
The first differential pair tube 11, the second differential pair tube 12 and the work of third differential pair tube 13 are obtained in sub-threshold region.Due to MOS in circuit
Pipe works in sub-threshold region, so that the circuit power consumption is relatively small, is applied to the super of the built-in fields such as portable equipment realizing
Low consumption circuit design aspect has very big advantage.
In filter network system work, the switch terminals by controlling second transistor 112 control the size of voltage, just
It can control the shape of Sigmoid function, change gaussian filtering scale, and then realize multiple dimensioned gaussian filtering process.Specifically,
For tail current after differential pair tube 11 and 12, it is the equal of to tail current that two electric currents of output, which are all sigmod function currents,
It is weighted.Also, according to Kirchhoff's current law (KCL), it is two complementary that two output ends, which are just reverse phases,
Sigmod function.The output function on the differential pair tube left side is known as s1, the output function on the right is known as s2, then, tail current warp
The first differential pair tube 11 is crossed, left output is Iin*s1, and right output is Iin*s2.According to circuit diagram, a left side for the first differential pair tube 11
Output by a differential pair tube 13 and takes right output again, so obtaining Iin*s1*s2.Similarly, the right side of the first differential pair tube 11
Output also again passes by a differential pair tube 12 and takes left output, obtains Iin*s2*s1.At this point, we obtain two symmetrically
Class Gaussian function Iin*s1*s2 and Iin*s2*s1.Due to error, the two class Gaussian functions may have slight asymmetry.
After output end is collaborated, asymmetry can be eliminated, obtains full symmetric class Gaussian function.
By deriving, the output electric current of available filter network system is：
Wherein, I0Indicate that the tail current of input, Sech indicate that hyperbolic secant function, Δ V indicate differential voltage input, n table
Show thermodynamic voltage (being constant under given technique), VT indicates thermal voltage (being determining value=kT/q under fixed temperature).It is practical
Upper sech chi square function is very close with Gaussian function, then has：
γ indicates Gauss scale coefficient (related to circuit structure and technique).So changing two switch terminals of differential pair tube
Voltage difference be can reach modification Gaussian function scale purpose.
In addition, user can also add peripheral control circuits and control input voltage, thus to circuit network according to demand
Filter scale carries out Programmable Design, can also construct multilayer circuit network, establish multi-scale image gaussian pyramid, Ke Yiying
For in high-level image procossing, such as SIFT, SURF image characteristics extraction algorithm.Meanwhile passing through different control voltage
Input, the circuit can also realize the real-time adjustment of filter scale.
In one embodiment of the invention, output circuit 20 includes the mirror image being made of the two transistor of switch terminals connection
Current source 21, the input terminal of a transistor of the mirror current source 21 respectively in the second differential pair tube 12 with second transistor
The crystalline substance being connect in the output end of transistor of 112 switch terminals connection, third differential pair tube 13 with the switch terminals of the first transistor 111
The output end of body pipe is connected with the switch terminals of two transistor in mirror current source.The input terminal introduces input current, passes through the mirror
Another transistor in image current source 21 exports.
In one embodiment of the invention, which further includes a symmetrical transistor 22, the symmetrical transistor
22 is poor with the output end of transistor and third connecting in the second differential pair tube 12 with the switch terminals of the first transistor 111 respectively
Divide and the output end for the transistor connecting in pipe 13 with the switch terminals of second transistor 112 is connected.The symmetrical transistor 22 to
It realizes that circuit structure is symmetrical, is conducive to circuit stability.
According to another aspect of the present invention, a kind of image processing system is additionally provided, is illustrated in figure 3 according to the present invention
One embodiment the image processing system schematic diagram using one-dimensional filtering network system.The system includes the above
Gaussian convolution filter network system and cmos image sensor, wherein each pixel unit includes on CMOS imaging sensor
One processing unit.Processing unit is driven by the control signal that control circuit issues, so that photosensitive part acquisition light letter thereon
Number, processing unit converts optical signals to photoelectric current again.Photoelectric current passes through the first transistor in corresponding first differential pair tube 11
111 and the input terminal of second transistor 112 enter Gaussian convolution filter network system.In each of cmos image sensor
In pixel unit, can integrating filtering network system circuit, enable sensor obtain analog signal directly in analog domain
Gaussian filtering process, the data then completed by AD readout process are carried out, then carry out subsequent high-level image procossing.In height
When this filtering processing, the signal processing of analog domain is carried out since original analog information, is avoided from analog to digital domain
Conversion process is conducive to improve arithmetic speed.
In one embodiment of the invention, the image processing system further include template storage and with the template storage
The transfer function of the digital analog converter of connection, template, filter scale and Gauss multiplier based on template storage storage calculates
The control voltage of the switch terminals of second transistor 112, the control voltage are defeated after analog-digital converter DAC is converted to analog signal
Gaussian convolution filter network system is given out.
When the template storage carries out gaussian filtering process for storing, pixel unit to be processed and neighborhood pixels unit
Weighted value, the weighted value are used to generate the brightness of pixel unit to be processed.Such as the Gauss power of 3x3,5x5 generallyd use etc.
Molality plate.Cmos image sensor and filter network when being illustrated in figure 4 using one-dimensional filtering network system shown in Fig. 3
The connection schematic diagram of system, the filter network system use 5 Gauss multipliers, illustrate the Gauss weight template used for
1x5, the corresponding pixel unit used includes pixel unit 1 to be processed (with tail current I0It is corresponding) and its left 2 and 2, the right side
(with tail current I-2, I-1, I1, I2It is corresponding, I-1And I1、I-2And I2In position about pixel symmetry arrangement to be processed, apart from phase
Deng), 5 pixel units in total.That is, the quantity of Gauss multiplier is equal to template in Gaussian convolution filter network system
Number of pixel cells needed for the template stored in memory.According to the difference of application demand, integrated multiplication can be accordingly adjusted
Device quantity carries out the filtering processing of different templates size.
It is below that the 2-d gaussian filters circuit that 3 × 3, corresponding gaussian filtering network system is 3x3 is with template size
Example is illustrated, as shown in Figure 5.It is as follows that process is filtered in it：The image information that mos image sensor acquires camera turns
It is changed to electric signal, i.e., Optic flow information is converted into the tail current input terminal that electric current is input to each Gauss multiplier.Based on template
One group of control can be calculated in the transfer function that template, filter scale and the Gauss multiplier itself of memory storage are fitted
Voltage (V0, V1, V2), wherein V0 corresponds to intermediate pixel unit in the template to be processed, and V1 is corresponded on pixel unit to be processed
4 pixel units of lower left and right, V2 correspond to other pixel units in the template, are based on distance in this way for pixel list to be processed
The pixel unit of member and surrounding is divided into 3 groups and is handled, and the weight of different pixels unit is embodied based on the control voltage.Work as template
When variation, Gauss number of multipliers and control voltage amount are both needed to adjust accordingly.Corresponding input connection finishes, circuit stability
Afterwards, the electric current output of output end had both been the convolutional calculation result of corresponding position.Simulating, verifying shows the settling time of the circuit
It in hundred picosecond magnitudes, is compared with digital circuit, Gaussian convolution can be carried out with the frequency of the 10GHz order of magnitude by being equivalent to, and can be seen
The circuit has very big advantage in speed out.
In one embodiment of the invention, which can be schemed with large-scale integrated in CMOS
As in sensor, it might even be possible to be integrated in inside each pixel, carry out MPP.
It is required to the pixel value of current location and the pixel value of adjacent position due to each convolutional calculation, is advised greatly
When mould parallel computation, the syntople between pixel is complex, and user can be reduced according to application demand and integrated technique
The quantity of convolution algorithm unit, and add corresponding Peripheral digital circuit and carry out serial parallel architecture design, meeting application demand
Simplify circuit design under conditions of technological design rule, as shown in Figure 6.Since the circuit input and output are electric current, consider
To simplifying circuit design and reducing power consumption, circuit network can be multiplexed, to reduce the circuit number of plies, improve efficiency.Convolution
The output result of filtering can directly be read by AD.
Compared to digital display circuit, which in conjunction with sensor, is carrying out simulation numeral for sensing data for calculating process
Before conversion, the calculating process of entire complexity is completed in analog domain, and operation time can be ignored substantially compared with the AD time,
Surmounted conventional digital system from operation framework and speed, and due in arithmetic element circuit metal-oxide-semiconductor all work in subthreshold
It is worth area, therefore its power consumption also may remain in reduced levels.The simulation gaussian filtering module that this patent proposes can be according to subsequent
Different application demands and design specification, user are customized design, can carry out different scales in cmos image sensors
It is integrated, to meet the demand of different filtering bandwidths.Meanwhile user can also add Peripheral digital control circuit, constitute mixed
Close signal processing circuit, increase its programmability, enable the circuit it is more flexible applied to field of image processing.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But scope of patent protection of the invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (10)
1. a kind of filter network system, including：
Several Gauss multipliers；
Output circuit, the output circuit are separately connected with several Gauss multipliers,
Wherein, the Gauss multiplier includes the first differential pair tube and the second difference for being separately connected with first differential pair tube
To pipe and third differential pair tube, the output end of the first transistor is separately connected second differential pair in first differential pair tube
The input terminal of two transistor in pipe, the output end of second transistor is separately connected the third difference in first differential pair tube
To the input terminal of two transistor in pipe, the input terminal of the input terminal of the first transistor and the second transistor is in parallel, institute
State the output end of two transistor in the output end of two transistor and the third differential pair tube in the second differential pair tube respectively with institute
State output circuit connection.
2. filter network system according to claim 1, which is characterized in that second differential pair tube and the third are poor
Divide and the switch terminals of a transistor in two transistor in pipe are connect with the switch terminals of the first transistor respectively, another transistor
Switch terminals connect respectively with the switch terminals of the second transistor, pass through the control of the switch terminals of the control second transistor
Voltage, so that first differential pair tube, second differential pair tube and third differential pair tube work are in sub-threshold region.
3. filter network system according to claim 2, which is characterized in that the output circuit includes being connected by switch terminals
Two transistor constitute mirror current source, the input terminal of a transistor of the mirror current source respectively with second difference
To in the output end of the transistor being connect with the second transistor switch terminals in pipe, the third differential pair tube with it is described
The output end of the transistor of the switch terminals connection of the first transistor is connected with the switch terminals of two transistor in the mirror current source.
4. filter network system according to claim 3, which is characterized in that the output circuit further includes an assymetric crystal
Pipe, the symmetrical transistor respectively with the transistor being connect with the first transistor switch terminals in second differential pair tube
Output end and the transistor being connect with the switch terminals of the second transistor in the third differential pair tube output end connect
It connects.
5. a kind of image processing system, including：
Filter network system of any of claims 1-4；
Cmos image sensor, the photoelectric current of each pixel unit output passes through described in corresponding first differential pair tube thereon
The input terminal of the first transistor and the second transistor enters the filter network system.
6. image processing system according to claim 5, which is characterized in that described image processing system further includes that template is deposited
Reservoir and the digital analog converter being connect with the template storage, template, filter scale based on template storage storage
The control voltage of the switch terminals of the second transistor, the control voltage warp are calculated with the transfer function of the Gauss multiplier
Output is to the filter network system after the digital analog converter is converted to analog signal.
7. image processing system according to claim 6, which is characterized in that Gauss multiplier in the filter network system
Quantity be equal to the number of weight in the template that stores in the template storage.
8. image processing system according to claim 7, which is characterized in that described image processing system further include respectively with
The input of the first transistor in first differential pair tube described in the cmos image sensor, the filter network system
The read-out control circuit connected with the input terminal of the second transistor is held, to pixel list each in the cmos image sensor
The photoelectric current of member output is serially filtered.
9. image processing system according to claim 7, which is characterized in that the filter network system integration is described
In cmos image sensor.
10. image processing system according to claim 7, which is characterized in that the filter network system is arranged described
Outside cmos image sensor, and photooptical data is read by the output port of the cmos image sensor.
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| CN107766932B (en) * | 2017-10-19 | 2021-06-04 | 珠海格力电器股份有限公司 | Image processing method and device based on neural network |
| CN113189634B (en) * | 2021-03-02 | 2022-10-25 | 四川新先达测控技术有限公司 | Gaussian-like forming method |
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