CN105979174A - Filtering network and image processing system - Google Patents
Filtering network and image processing system Download PDFInfo
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- CN105979174A CN105979174A CN201610293859.5A CN201610293859A CN105979174A CN 105979174 A CN105979174 A CN 105979174A CN 201610293859 A CN201610293859 A CN 201610293859A CN 105979174 A CN105979174 A CN 105979174A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
The invention discloses a filtering network and an image processing system. The filtering network comprises a plurality of gauss multipliers, and an output circuit respectively connected with the gauss multipliers, wherein each gauss multiplier comprises a first differential pair transistor which is respectively connected with a second differential pair transistor and a third differential pair transistor. The output end of the first transistor of each first differential pair transistor is respectively connected with the input ends of the two transistors of the second differential pair transistor, and the output end of the second transistor of each first differential pair transistor is respectively connected with the input ends of the two transistors of the third differential pair transistor. The input end of the first transistor is parallelly connected with the input end of the corresponding second transistor. The output ends of the two transistors of each second differential pair transistor and the output ends of the two transistors of each third differential pair transistor are respectively connected with the output circuit. Gauss convolution filtering processing is realized through simulated gauss multipliers, the gauss convolution filtering speed can be accelerated, and the circuit power consumption is reduced.
Description
Technical field
The present invention relates to technical field of image processing, specifically, relate to a kind of filter network and image procossing system
System.
Background technology
In Digital Signal Processing, convolutional filtering is a very important step in Signal Pretreatment.At image
Process field, Gaussian convolution wave filter is a kind of smoothing filter, and its effect is that acquisition signal to noise ratio snr is higher
Image, and avoid the ringing of image.In traditional digital image processing system, imageing sensor collection
To image information be converted to digital signal by analog-digital converter ADC, use Digital Signal Processing DSP
Technology carries out follow-up Filtering Processing.
But, along with the development of image sensing technology, the image resolution ratio collected significantly promotes so that
The continuous yardstick of multiple dimensioned gaussian filtering is expanded and is caused sharply increasing of data volume and operand, conventional digital system
It is increasingly difficult to meet image processing system for real-time and the demand of power consumption.Especially portable equipment and can wearing
Wearing the embedded systems such as equipment, the design in terms of high speed, miniaturization and super low-power consumption requires higher, more
It is difficult to meet demand parameter.
In real image processes, gaussian filtering carries out convolution realization by view data and Gaussian template.
Convolution algorithm is actually a series of multiplication and additive operation.But, due to each pixel in image and
The neighborhood of its particular size all will participate in multiply-add operation, therefore when picture size is big, definition height time, it is necessary to
The Gaussian convolution computing repeated in a large number.And this operation is indispensable in many image processing algorithms
A part, such as Image Edge-Detection and enhancing, spot detection and scale invariant feature extraction algorithm etc.,
It is required for, at pretreatment stage, input picture carries out certain yardstick or multiple dimensioned gaussian filtering.
As a example by SIFT algorithm the most classical in image characteristics extraction algorithm, this algorithm realizes real-time operation
Main Bottleneck is that the foundation of gaussian pyramid, the part of the most multiple dimensioned Gaussian filter operation.Experiment shows,
This algorithm is in FPGA realizes, and the time of gaussian filtering expensive component accounts for total algorithm operation time
85.63%.Therefore, for real time image processing system, especially for Embedded Image Processing System, effectively add
The multiple dimensioned gaussian filtering of speed to reduce power consumption be the most necessary.
Summary of the invention
For solving problem above, the invention provides a kind of filter network and image processing system, in order to accelerate height
This filters and reduces circuit power consumption.
According to an aspect of the present invention, the invention provides a kind of filter network, including:
Some Gauss multipliers；
Output circuit, described output circuit is connected respectively with some described Gauss multipliers,
Wherein, described Gauss multiplier includes the first differential pair tube and is connected respectively with described first differential pair tube
Second differential pair tube and the 3rd differential pair tube, in described first differential pair tube, the outfan of the first transistor connects respectively
Connecing the input of two transistor in described second differential pair tube, in described first differential pair tube, transistor seconds is defeated
Go out end and connect the input of two transistor, the input of described the first transistor in described 3rd differential pair tube respectively
In parallel with the input of described transistor seconds, the outfan of two transistor and described in described second differential pair tube
In 3rd differential pair tube, the outfan of two transistor is connected with described output circuit respectively.
According to one embodiment of present invention, two crystal in described second differential pair tube and described 3rd differential pair tube
The switch terminals of Guan Zhongyi transistor switch terminals with described the first transistor respectively is connected, the switch of another transistor
End switch terminals with described transistor seconds respectively is connected, by the control of the switch terminals of the described transistor seconds of control
Voltage processed so that described first differential pair tube, described second differential pair tube and described 3rd differential pair tube are operated in
Sub-threshold region.
According to one embodiment of present invention, described output circuit includes that the two transistor connected by switch terminals is constituted
Mirror current source, the input of a transistor of described mirror current source respectively with in described second differential pair tube
The outfan of the transistor being connected with described transistor seconds switch terminals, in described 3rd differential pair tube with institute
State two transistor in the outfan of transistor and described mirror current source that the switch terminals of the first transistor connects
Switch terminals connects.
According to one embodiment of present invention, described output circuit also includes a symmetrical transistor, described symmetrical brilliant
Body pipe defeated with the transistor being connected with described the first transistor switch terminals in described second differential pair tube respectively
Go out the output of the transistor that the switch terminals with described transistor seconds in end and described 3rd differential pair tube is connected
End connects.
According to another aspect of the present invention, additionally provide a kind of image processing system, including:
Filter network described in any of the above item；
Cmos image sensor, on it, the photoelectric current of each pixel cell output is by corresponding described first difference
The input of the first transistor described in pipe and described transistor seconds is entered described filter network.
According to one embodiment of present invention, described image processing system also include template storage and with described mould
The digital to analog converter that board memory connects, the template stored based on described template storage, filter scale and described
The transfer function of Gauss multiplier calculates the control voltage of the switch terminals of described transistor seconds, described control voltage
Export after described digital to analog converter is converted to analogue signal to described Gaussian convolution filter network.
According to one embodiment of present invention, in described filter network, the quantity of Gauss multiplier is equal to described template
The number of weights in the template of storage in memorizer.
According to one embodiment of present invention, described image processing system also include respectively with described cmos image
The input of the described the first transistor in the first differential pair tube described in sensor, described filter network and described
The read-out control circuit that the input of transistor seconds connects, with to pixel each in described cmos image sensor
The photoelectric current of unit output carries out serial filtering.
According to one embodiment of present invention, in described filter network is integrated in described cmos image sensor.
According to one embodiment of present invention, described filter network is arranged on outside described cmos image sensor,
And read photooptical data by the output port of described cmos image sensor.
Beneficial effects of the present invention:
The present invention realizes Gaussian convolution Filtering Processing by simulation Gauss multiplier, can improve Gaussian convolution filtering
Speed, reduces circuit power consumption.
Other features and advantages of the present invention will illustrate in the following description, and, partly from description
In become apparent, or by implement the present invention and understand.The purpose of the present invention and other advantages can be passed through
Structure specifically noted in description, claims and accompanying drawing realizes and obtains.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment
Or the accompanying drawing required in description of the prior art does and simply introduces:
Fig. 1 is a kind of filter network structural representation according to an embodiment of the invention；
Fig. 2 a is the connection signal of a Gauss multiplier according to an embodiment of the invention and output circuit
Figure；
Fig. 2 b is transfer function and the contrast schematic diagram of Gaussian function of Gauss multiplier in Fig. 2 a；
Fig. 3 is that the image processing system of employing one-dimensional filtering network according to an embodiment of the invention shows
It is intended to；
Fig. 4 is cmos image sensor during for using the one-dimensional filtering network shown in Fig. 3 and filter network
Connection diagram；
Fig. 5 is the picture signal of the 2-d gaussian filters circuit of employing 3x3 according to an embodiment of the invention
Process schematic diagram；And
Fig. 6 is image processing system schematic diagram according to another embodiment of the present invention.
Detailed description of the invention
Embodiments of the present invention are described in detail, whereby to the present invention how below with reference to drawings and Examples
Application technology means solve technical problem, and the process that realizes reaching technique effect can fully understand and real according to this
Execute.As long as it should be noted that do not constitute conflict, in each embodiment in the present invention and each embodiment
Each feature can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
It is illustrated in figure 1 a kind of filter network structural representation according to an embodiment of the invention, below joins
The present invention is described in detail to examine Fig. 1.
This filter network includes some Gauss multipliers 10 and the output electricity being connected respectively with some Gauss multipliers
Road 20.Wherein, this Gauss multiplier 10 includes the first differential pair tube 11 and distinguishes with the first differential pair tube 11
The second differential pair tube 12 and the 3rd differential pair tube 13 connected, the first transistor 111 in the first differential pair tube 11
Outfan connect the input of two transistor in the second differential pair tube 12 respectively, in the first differential pair tube 11
The outfan of two-transistor 112 connects the input of two transistor in the 3rd differential pair tube 13 respectively, and first is brilliant
The input of body pipe 111 and the input of transistor seconds 113 are in parallel, two crystal in the second differential pair tube 12
In the outfan of pipe and the 3rd differential pair tube 13, the outfan of two transistor is connected with output circuit 20 respectively.
It is the Gauss multiplier 10 according to one embodiment of the present of invention and output circuit 20 as shown in Figure 2 a
Connection diagram.When this circuit works, by controlling voltage V+ and V-of three differential pair tube switch terminals,
Make tail current IinBy input and the transistor seconds of the first transistor 111 in the first differential pair tube 11
The input of 112 enters this Gauss multiplier, after this Gauss multiplier processes, exports to output circuit 20,
And export electric current Iout through output circuit 20.
From Fig. 2 a, in this Gauss multiplier 10, the first differential pair tube 11 and the second differential pair tube 12
End to end, the first differential pair tube 11 is end to end with the 3rd differential pair tube 13, the second differential pair tube 12 He
3rd differential pair tube 13 outfan is in parallel.Gauss multiplier 10 utilizes the nearly Gauss that MOS differential pair tube produces
Transfer characteristic function as gaussian kernel function, can realize being multiplied of tail current and gaussian kernel function at analog domain.
Concrete, this Gauss multiplier utilizes the Sigmoid that the MOS differential pair tube being operated in sub-threshold region produces
Transfer characteristic, by end to end for two groups of such differential pair tubes so that two centrosymmetric Sigmoid functions
It is multiplied, it is thus achieved that hyperbolic secant chi square function.This hyperbolic secant chi square function the most closely Gaussian function,
As shown in Figure 2 b.Therefore, what this circuit was constituted is not standard gaussian characteristic, but a kind of nearly Gauss shifts spy
Property, this function in mathematical property with Gaussian function closely, i.e. from the result of convolution and Fourier transformation still
So approximation meets Gaussian characteristics.Owing to this Gauss multiplier is current analog circuit, as long as by some Gauss multiplication
Circuit output is joined directly together, and just can realize the additive operation in Gaussian convolution filtering operation.As it is shown in figure 1,
By tail current I-2、I-1、I0、I1, I2Corresponding Gauss multiplier outputs is connected in parallel, and output electric current is:
Then can realize additive operation.Therefore, the filter network described in Fig. 1 can realize Gaussian convolution filtering.
The analog filtering network utilizing Fig. 1 carries out the advantage of image filtering and is, from the beginning of original analog information
Be simulated territory signal processing, closer to perception and the calculating process being similar to organism itself.This mistake
Journey avoids the transformation process from analog to digital territory, but utilizes the stable process of setting up of physical device to carry out certainly
The physical computing sent out.Compared to Digital Signal Processing, especially transport at multiplication and division computing, exponent arithmetic and floating-point
The complicated calculations process aspects such as calculation, this physical computing pattern achieves in speed and surmounts.
In one embodiment of the invention, the second differential pair tube 12 and the 3rd differential pair tube 13 the two are to pipe
In in respective two transistor the switch terminals of transistor switch terminals with the first transistor 111 respectively be connected, separately
The switch terminals of one transistor switch terminals with transistor seconds 112 respectively is connected, by controlling transistor seconds 112
The control voltage of switch terminals so that the first differential pair tube the 11, second differential pair tube 12 and the 3rd differential pair tube
13 are operated in sub-threshold region.Owing in circuit, metal-oxide-semiconductor is operated in sub-threshold region so that this circuit power consumption is relative
Less, have the biggest in terms of realization is applied to the super low-power consumption circuit design of the built-in fields such as portable equipment
Advantage.
When this filter network works, controlled the size of voltage by the switch terminals controlling transistor seconds 112,
Just can control the shape of Sigmoid function, change gaussian filtering yardstick, and then realize multiple dimensioned gaussian filtering
Process.Concrete, tail current is after differential pair tube 11 and 12, and two electric currents of output are all sigmod
Function current, is the equal of to be weighted tail current.Further, according to Kirchhoff's current law (KCL), two
Outfan is the most anti-phase, is i.e. two complementary sigmod functions.Output function by the differential pair tube left side
Being referred to as s1, the output function on the right is referred to as s2, then, tail current is through the first differential pair tube 11, left output
For Iin*s1, the right side is output as Iin*s2.According to circuit diagram, the left output of the first differential pair tube 11 is again through one
Differential pair tube 13 also takes right output, so obtaining Iin*s1*s2.In like manner, the right output of the first differential pair tube 11
Also again pass by a differential pair tube 12 and take left output, obtaining Iin*s2*s1.Now, we obtain two
Symmetrical class Gaussian function Iin*s1*s2 and Iin*s2*s1.Due to error, the two class Gaussian function may have
Slight unsymmetry.After outfan collaborates, unsymmetry can be eliminated, obtain full symmetric class
Gaussian function.
Through deriving, the output electric current that can obtain filter network is:
Wherein, I0Representing the tail current of input, Sech represents that hyperbolic secant function, Δ V represent that differential voltage is defeated
Entering, n represents the non-ideal factor (for constant under given technique), and VT represents that thermal voltage (is true under fixed temperature
Fixed value=kT/q).Actually sech chi square function with Gaussian function closely, then has:
γ represents Gauss scale coefficient (relevant to circuit structure and technique).So, change differential pair tube two switch
The voltage difference of end i.e. can reach the purpose of amendment Gaussian function yardstick.
It addition, user can also add peripheral control circuits and control input voltage according to demand, thus to circuit
The filter scale of network carries out Programmable Design, it is also possible to builds multilayer circuit network, sets up multi-scale image
Gaussian pyramid, can apply in high-level image procossing, as the image characteristics extractions such as SIFT, SURF are calculated
Method.Meanwhile, by the different inputs controlling voltage, this circuit can also realize the real-time adjustment of filter scale.
In one embodiment of the invention, output circuit 20 includes that the two transistor connected by switch terminals is constituted
Mirror current source 21, the input of a transistor 211 of this mirror current source 21 respectively with the second differential pair
In the outfan of transistor that is connected with transistor seconds 112 switch terminals in pipe 12, the 3rd differential pair tube 13 with
The switch of two transistor in the outfan of the transistor that the switch terminals of the first transistor 111 connects and mirror current source
End connects.This input introduces input current, is exported by another transistor 212 of this mirror current source 21.
In one embodiment of the invention, this output circuit 20 also includes a symmetrical transistor 22, this symmetry
Transistor 22 respectively with the transistor being connected with the switch terminals of the first transistor 11 in the second differential pair tube 12
The outfan of the transistor being connected with the switch terminals of transistor seconds 12 in outfan and the 3rd differential pair tube 13 is even
Connect.This symmetrical transistor 22 is symmetrical in order to realize circuit structure, beneficially circuit stability.
According to another aspect of the present invention, additionally provide a kind of image processing system, as shown in Figure 3 according to
The image processing system schematic diagram using one-dimensional filtering network of one embodiment of the present of invention.This system bag
Include above-described Gaussian convolution filter network and cmos image sensor, wherein, cmos image sensor
Upper each pixel cell all includes a processing unit.The control signal that processing unit is sent by control circuit drives,
Making photosensitive part thereon gather optical signal, processing unit converts optical signals to photoelectric current again.Photoelectricity circulates
Cross the input of the first transistor 111 and transistor seconds 113 in the first differential pair tube 11 of correspondence and enter height
This convolutional filtering network.In each pixel cell of cmos image sensor, all can integrating filtering network
Circuit so that the analogue signal that sensor obtains directly can carry out gaussian filtering process at analog domain, then leads to
Cross the data that AD readout process completes, then carry out follow-up high-level image procossing.When gaussian filtering processes,
The signal processing of analog domain is proceeded by, it is to avoid converted from analog to digital territory from original analog information
Journey, is conducive to improving arithmetic speed.
In one embodiment of the invention, this image processing system also include template storage and with this template at
The digital to analog converter that reason device connects, template, filter scale and Gauss multiplier of based on template storage storage
Transfer function calculates the control voltage of the switch terminals of transistor seconds 112, and this control voltage is through analog-digital converter
DAC exports to Gaussian convolution filter network 10 after being converted to analogue signal.
This template storage for storage carry out gaussian filtering process time, pending pixel cell and neighborhood pixels list
The weighted value of unit, this weighted value is for generating the brightness of pending pixel cell.The 3x3 that such as generally uses,
The Gauss weight template of 5x5 etc..It is illustrated in figure 4 the CMOS during one-dimensional filtering network used shown in Fig. 3
Imageing sensor and the connection diagram of filter network, this filter network have employed 5 Gauss multipliers, explanation
The Gauss weight template used is 1x5, the corresponding pixel cell used include pending pixel cell 1 (with
Tail current I0Corresponding) and left 2 and right 2 (with tail current I-2, I-1, I1, I2Correspondence, I-1And I1、I-2
And I2In position about pending pixel symmetry arrangement, apart from equal), 5 pixel cells altogether.The most just
It is to say, needed in Gaussian convolution filter network, the quantity of Gauss multiplier is equal to the template of storage in template storage
Number of pixel cells.According to the difference of application demand, integrated number of multipliers can be adjusted accordingly, carry out not
Filtering Processing with template size.
Below with template size be 3 × 3, the corresponding gaussian filtering network 2-d gaussian filters circuit as 3x3 be
Example illustrates, as shown in Figure 5.Its Filtering Processing flow process is as follows: mos image sensor is by camera collection
Image information be converted to the signal of telecommunication, electric current will be converted into be input to the tail of each Gauss multiplier by Optic flow information
Current input terminal.Template, filter scale and the matching of Gauss multiplier own of based on template storage storage
Transfer function can calculate one group and control voltage (V0, V1, V2), and wherein, V0 is corresponding pending
Intermediate pixel unit in this template, corresponding pending pixel cell 4 pixel cells up and down of V1, V2
To should other pixel cell in template, so based on distance by pending pixel cell and pixel list around
Unit is divided into 3 groups to process, and embodies the weight of different pixels unit based on this control voltage.When template changes,
Gauss number of multipliers and control voltage amount are both needed to adjust accordingly.Corresponding input connects complete, circuit stability
After, the electric current output of its outfan had both been the convolutional calculation result of correspondence position.Simulating, verifying shows this circuit
Time of setting up, at hundred picosecond magnitudes, contrasts with digital circuit, is equivalent to enter with the frequency of the 10GHz order of magnitude
Row Gaussian convolution, it can be seen that this circuit has the biggest advantage in speed.
In one embodiment of the invention, this Gaussian convolution filter network can be schemed at CMOS with large-scale integrated
As in sensor, it might even be possible to be integrated in inside each pixel, carry out MPP.
It is required to pixel value and the pixel value of adjacent position of current location due to each convolutional calculation, therefore carries out
During Large-scale parallel computing, the syntopy between pixel is complex, user can according to application demand and
Integrated technique, reduces the quantity of convolution algorithm unit, and adds corresponding Peripheral digital circuit and carry out serial parallel frame
Structure designs, and simplifies circuit design, as shown in Figure 6 under conditions of meeting application demand and technological design rule.
Owing to these circuit input and output are electric current, it is contemplated that simplify circuit design and reduce power consumption, can be by circuit network
Network carries out multiplexing, to reduce the circuit number of plies, improves efficiency.The output result of convolutional filtering can be straight by AD
Connect reading.
Compared to digital display circuit, calculating process is combined by this circuit with sensor, is being simulated by sensing data
Before numeral conversion, complete the calculating process of whole complexity at analog domain, and operation time and AD time phase
Can ignore than substantially, from computing framework and speed, surmount conventional digital system, and due to arithmetic element
In circuit, metal-oxide-semiconductor is all operated in sub-threshold region, and therefore its power consumption can also be kept low.This patent
The simulation gaussian filtering module proposed can be according to follow-up different application demand and design specification, and user carries out fixed
Set up meter, the integrated of different scales can be carried out in cmos image sensors, to meet different cake resistancet
Wide demand.Meanwhile, user can also add Peripheral digital control circuit, constitutes mixed signal and processes circuit,
Increase its programmability, make what this circuit can be more flexible to be applied to image processing field.
While it is disclosed that embodiment as above, but described content is only to facilitate understand the present invention
And the embodiment used, it is not limited to the present invention.Technology people in any the technical field of the invention
Member, on the premise of without departing from spirit and scope disclosed in this invention, can be in the formal and details implemented
On make any amendment and change, but the scope of patent protection of the present invention, still must be with appending claims institute
Define in the range of standard.
Claims (10)
1. a filter network, including:
Some Gauss multipliers；
Output circuit, described output circuit is connected respectively with some described Gauss multipliers,
Wherein, described Gauss multiplier includes the first differential pair tube and is connected respectively with described first differential pair tube
Second differential pair tube and the 3rd differential pair tube, in described first differential pair tube, the outfan of the first transistor connects respectively
Connecing the input of two transistor in described second differential pair tube, in described first differential pair tube, transistor seconds is defeated
Go out end and connect the input of two transistor, the input of described the first transistor in described 3rd differential pair tube respectively
In parallel with the input of described transistor seconds, the outfan of two transistor and described in described second differential pair tube
In 3rd differential pair tube, the outfan of two transistor is connected with described output circuit respectively.
Filter network the most according to claim 1, it is characterised in that described second differential pair tube and institute
State in the 3rd differential pair tube the switch terminals of a transistor in two transistor respectively with the switch of described the first transistor
End connects, and the switch terminals of another transistor switch terminals with described transistor seconds respectively is connected, by control institute
State the control voltage of the switch terminals of transistor seconds so that described first differential pair tube, described second differential pair tube
It is operated in sub-threshold region with described 3rd differential pair tube.
Filter network the most according to claim 2, it is characterised in that described output circuit includes by opening
The mirror current source that the two transistor that Guan Duan connects is constituted, the input of a transistor of described mirror current source divides
Not with the outfan of transistor being connected with described transistor seconds switch terminals in described second differential pair tube, institute
State the outfan of the transistor that the switch terminals with described the first transistor in the 3rd differential pair tube is connected and described
In mirror current source, the switch terminals of two transistor connects.
Filter network the most according to claim 3, it is characterised in that described output circuit also includes one
Symmetrical transistor, described symmetrical transistor respectively with opening with described the first transistor in described second differential pair tube
The switch with described transistor seconds in the outfan of the transistor that Guan Duan connects and described 3rd differential pair tube
The outfan of the transistor that end connects connects.
5. an image processing system, including:
Filter network according to any one of claim 1-4；
Cmos image sensor, on it, the photoelectric current of each pixel cell output is by corresponding described first difference
The input of the first transistor described in pipe and described transistor seconds is entered described filter network.
Image processing system the most according to claim 5, it is characterised in that described image processing system
Also include template storage and the digital to analog converter being connected with described template storage, based on described template storage
The transfer function of template, filter scale and the described Gauss multiplier of storage calculates the switch of described transistor seconds
The control voltage of end, described control voltage exports to described height after described digital to analog converter is converted to analogue signal
This convolutional filtering network.
Image processing system the most according to claim 6, it is characterised in that high in described filter network
The quantity of this multiplier is equal to the number of weights in the template of storage in described template storage.
Image processing system the most according to claim 7, it is characterised in that described image processing system
Also include respectively with the institute in the first differential pair tube described in described cmos image sensor, described filter network
The read-out control circuit that the input of the input and described transistor seconds of stating the first transistor connects, with to institute
State the photoelectric current of each pixel cell output in cmos image sensor and carry out serial filtering.
Image processing system the most according to claim 7, it is characterised in that described filter network is integrated
In described cmos image sensor.
Image processing system the most according to claim 7, it is characterised in that described filter network is arranged
Outside described cmos image sensor, and read light by the output port of described cmos image sensor
Electricity data.
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| CN108513042A (en) * | 2017-02-24 | 2018-09-07 | 清华大学 | Device for image procossing |
| US10827102B2 (en) | 2017-02-24 | 2020-11-03 | Huawei Technologies Co., Ltd | Image processing apparatus |
| CN108475426A (en) * | 2017-06-30 | 2018-08-31 | 深圳市大疆创新科技有限公司 | Optical flow tracking device and method |
| WO2019000396A1 (en) * | 2017-06-30 | 2019-01-03 | 深圳市大疆创新科技有限公司 | Optical flow tracking device and method |
| US11024005B2 (en) | 2017-06-30 | 2021-06-01 | SZ DJI Technology Co., Ltd. | Optical flow tracking device and method |
| CN107766932A (en) * | 2017-10-19 | 2018-03-06 | 珠海格力电器股份有限公司 | Image processing method and device based on neutral net |
| CN113189634A (en) * | 2021-03-02 | 2021-07-30 | 四川新先达测控技术有限公司 | Gaussian-like forming method |
| CN113189634B (en) * | 2021-03-02 | 2022-10-25 | 四川新先达测控技术有限公司 | Gaussian-like forming method |
| CN113365007A (en) * | 2021-05-28 | 2021-09-07 | 浙江大学 | Neural network image sensor array architecture based on two-dimensional material |
| CN113365007B (en) * | 2021-05-28 | 2022-07-19 | 浙江大学 | Neural network image sensor array architecture based on two-dimensional material |
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