CN101848319B - Fractional calculus filter of digital images of high-precision computation - Google Patents

Abstract

The invention provides a fractional calculus filter of digital images of high-precision computation, which is a circuit device for fractionally enhancing or smoothing complex texture detail characteristics of digital images at high precision. The filter is formed by connecting a RGB-to-HSI converter, a line memory group, a phase locking/shift circuit group, a fractional calculus mask convolution circuit, a maximum comparator and an HSI-to-RGB converter in cascade. Special fractional calculus mask convolution algorithms are used by a first algorithm unit circuit to an eighth algorithm unit circuit in the fractional calculus mask convolution circuit to realize high-precision computation of fractional calculus. The fractional calculus filter of digital images of high-precision computation, which is provided by the invention, is especially suitable for application occasions for fractionally enhancing or smoothing complex texture detail characteristics of high-definition digital televisions, biomedical images, bank bills, satellite remote sensing images, biological characteristic patterns and the like at high precision.

Description

The fractional calculus filter of the digital picture of high precision computation

Affiliated field

The fractional calculus filter of the digital picture of high precision computation proposed by the invention is a kind ofly digital picture complex texture minutia to be carried out the high accuracy fractional order strengthens or level and smooth circuit arrangement.The order of the fractional calculus that the present invention relates to is not traditional integer rank, but non-integral order is generally got mark or reasonable decimal in the practical applications.See Fig. 1, the fractional calculus filter of the digital picture of this high precision computation is to adopt RGB to constitute with cascade system to RGB transducer 14 with HSI to HSI transducer 9, line storage group 10, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12, maximum comparator 13.The first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 in the fractional calculus mask convolution circuit 12 adopts distinctive fractional calculus mask convolution algorithm to realize the high precision computation of fractional calculus.The fractional calculus filter of the digital picture of this high precision computation have can fractional order strengthen again can fractional order level and smooth, computational accuracy is high, the distortionless remarkable advantage of color.The fractional calculus filter of the digital picture of high precision computation proposed by the invention is specially adapted to that the complex texture minutia of HD digital TV, biomedical image, bank money, satellite remote sensing images and biometric image etc. is carried out the high accuracy fractional order to be strengthened or level and smooth application scenario.The invention belongs to the technical field of applied mathematics, Digital Image Processing and digital circuit cross discipline.

Background technology

At present, traditional image grain details signature analysis scheme be divided into statistical analysis scheme, structural analysis scheme, based on four types of model scheme and frequency spectrum schemes.In digital picture; Gray value between neighborhood interior pixel and the pixel has very strong correlation; This correlation normally shows with the grain details characteristic of complicacy, and the image texture minutia analytical plan of above-mentioned four quasi-traditions is all unsatisfactory to the result of the complex texture minutia that texture image was rich in.

Since nearly 300 years, fractional calculus had become an important branch of mathematical analysis already, but it is also rarely known by the people for the physicist of lot of domestic and foreign mathematician and even engineering circle.How this brand-new mathematical method of fractional calculus being applied among modern signal analysis and the processing, particularly Digital Image Processing, all still is a new branch of science branch that research is very few in the world.Applicant of the present invention is to fractional calculus Digital Signal Analysis and Processing in modern times, and particularly should be used as comparatively in Digital Image Processing goed deep into and systematic research.Applicant of the present invention is as independent inventor and the patentee fractional order differential filter (patent No.: ZL200610021702.3) obtain the authorization on September 2nd, 2009 in the patent of invention digital picture of application on August 30th, 2006.Applicant's of the present invention further research shows: though the fractional order differential filter of above-mentioned digital picture has the low frequency contour feature that can keep in the image smoothing zone as far as possible; Simultaneously again can fractional order, the relatively large high frequency edge characteristic of gray value transition amplitude in non-linear, the multiple dimensioned enhancing image; And can also fractional order, the remarkable advantage of the little relatively high frequency grain details characteristic of gray value transition amplitude and frequency change in non-linear, the multiple dimensioned enhancing image; But also existing following three big shortcomings to be further improved and improve: I. the fractional order differential filter of this digital picture can only be accomplished the fractional order differential computing, can not utilize same circuit structure to accomplish the fractional order integration computing.Therefore this filter can only carry out the fractional order enhancement process to the complex texture minutia of digital picture, and can not carry out the fractional order smoothing processing; II. advantages such as it is real-time, easy, efficient that this filter had are to be cost with the computational accuracy of sacrificing the fractional order differential computing, and its relative error is bigger, needing to be not suitable for the application scenario of the high precision computation of fractional order differential; III. since when the order of fractional order differential is big correlation between destruction digital color image R, G, three color components of B easily; So when the fractional order differential order was big, this filter was easy to generate color distortion to the result of digital color image.

To above-mentioned three big shortcomings; Applicant of the present invention has further furtherd investigate basic principle and the operation rule thereof with fractional calculus enhancing or level and smooth digital image texture minutia; On this basis according to the input characteristics of the character of digital image fractional order calculus and Digital Image Processing, digital circuit, serial digital video code stream; New departure of the circuit arrangement of a kind of high accuracy fractional order enhancing or level and smooth digital picture complex texture minutia has been proposed, i.e. the fractional calculus filter of the digital picture of high precision computation.The fractional calculus filter of the digital picture of this high precision computation have can fractional order strengthen again can fractional order level and smooth, computational accuracy is high, the distortionless remarkable advantage of color.Its popularization will to fractional calculus in modern times signal analysis with handle among, particularly produce far-reaching influence in the analysis of data image signal and application among handling.

Summary of the invention

The objective of the invention is to construct a kind of fractional calculus filter of digital picture of high precision computation, this filter can carry out that the high accuracy fractional order strengthens or level and smooth to digital picture complex texture minutia.Applicant of the present invention has furtherd investigate basic principle and the operation rule thereof with fractional calculus enhancing or level and smooth digital image texture minutia; On this basis according to the input characteristics of the character of digital image fractional order calculus and Digital Image Processing, digital circuit, serial digital video code stream; New departure of the circuit arrangement of a kind of high accuracy fractional order enhancing or level and smooth digital picture complex texture minutia has been proposed, i.e. the fractional calculus filter of the digital picture of high precision computation.The fractional calculus filter of the digital picture of this high precision computation have can fractional order strengthen again can fractional order level and smooth, computational accuracy is high, the distortionless remarkable advantage of color.See Fig. 1, the fractional calculus filter of the digital picture of this high precision computation is to adopt RGB to constitute with cascade system to RGB transducer 14 with HSI to HSI transducer 9, line storage group 10, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12, maximum comparator 13.The first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 in the fractional calculus mask convolution circuit 12 adopts distinctive fractional calculus mask convolution algorithm to realize the high precision computation of fractional calculus.

Before specifying content of the present invention; Be necessary used symbol connotation of this specification and span thereof are carried out 3 explanations: the 1st point; Continue to use the longitudinal axis and the transverse axis coordinate (different with the general mathematical notation of Euclidean space, its custom is represented transverse axis and ordinate of orthogonal axes respectively with x and y coordinate) be accustomed in the traditional images processing with x and y coordinate difference presentation video pixel, with S (x; Y) denotation coordination (x, the gray value or the rgb value of the pixel on y); When x and y get the continuous analogue value, S (x, y) expression analog image; When x and y got discrete digital value, (it was a picture element matrix to S for x, y) expression digital picture (x and y represent row-coordinate and row coordinate respectively); The 2nd point; In order to make fractional calculus mask (it is the square formation of (n+2) * (n+2)) that clear and definite axial symmetry center arranged; The minimum value of n is 3, the maximum occurrences of n+2 less than the size number N of the digital picture of pending fractional calculus (if (x y) is the picture element matrix of L * H to the digital picture S of pending fractional calculus; When L=H, its size number N=L; When L ≠ H, its size number N is the minimum value among L and the H, i.e. N=min (L, H)), n get any odd number between [3, min (L, H)-2], and (L H) gets minimum value among L and the H to min; The 3rd point, in practical engineering application, the digital picture S (x of pending processing; Y) (it is the picture element matrix of a L * H, and L representes S (x, line number y); H representes that (promptly every row has H pixel to S for x, columns y); X gets the integer between 0～(L-1), and y gets the integer between 0～(H-1)) gray value or the rgb value of the capable pixel of L generally be not parallel input (input simultaneously of each row of the gray value of the capable pixel of L or rgb value), but the serial input (gray value of the capable pixel of L or rgb value one-row pixels connect the one-row pixels input; The gray value or the rgb value of H pixel of every row input form the serial digital video code stream) image processing apparatus; According to the input characteristics of serial digital video code stream, use S _x(k) (subscript x representes each frame of digital image S (x to the pixel in the expression serial digital video code stream; Y) be to form the serial digital video code stream with the mode that one-row pixels connects one-row pixels input; (x is y) from its nethermost delegation (L is capable) beginning input from bottom to up, k remarked pixel S for S _x(k) the pixel sequence number in the serial digital video code stream, k begins counting from L * H-1, subtracts one by pixel input k value, until being zero); If S _x(k) coordinate before the corresponding serial input (x, the pixel S on y) (x, y), S then _x(coordinate before the corresponding serial input of k ± aH ± b) (the pixel S on the x ± a, y ± b) (x ± a, y ± b).

See Fig. 1, the fractional calculus filter of the digital picture of high precision computation of the present invention is to be formed to 14 cascades of RGB transducer with HSI to HSI transducer 9, line storage group 10, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12, maximum comparator 13 by RGB; Serial digital video code stream S _x(k) behind the fractional calculus filter of the digital picture of input high precision computation; Process RGB is divided into three the tunnel with gray value or brightness I component after HSI transducer 9 is handled: after the first via is handled through line storage group 10, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12 in proper order, and difference output pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side; After handling through maximum comparator 13, the value of exporting the mould value maximum in above-mentioned 8 approximations is as pixel S again _xThe v rank fractional calculus value approximation of (k+n (H+1))

The second the tunnel triggers sequential control circuit produces corresponding timing control signal; The output of Third Road and line storage group 10 together the feed-in lock mutually/shift circuit group 11 generates the pel array of (2n+1) * (2n+1).Wherein, the order v of the fractional calculus mask convolution circuit 12 in the fractional calculus filter of the digital picture of this high precision computation can-m～+ (m is any positive integer to get mark or reasonable fractional value between the m.Because the computational length of digital circuit is limited, when v is unreasonable decimal, can approximate approximate reasonable decimal); According to the demands of different of engineering precision, order v is divided into three types floating data, and the calculated data type of its first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 also is divided into corresponding three types: the 1st type; Single (accounts for 4 byte of memorys; Computational length 32bit, 6～7 of significant digits, evaluation scope 10 ^-37～10 ³⁸); The 2nd type, double (accounts for 8 byte of memorys, computational length 64bit, 15～16 of significant digits, evaluation scope 10 ^-307～10 ³⁰⁸); The 3rd type, long double (accounts for 16 byte of memorys, computational length 128bit, 18～19 of significant digits, evaluation scope 10 ^-4931～10 ⁴⁹³²).The fractional calculus filter of the digital picture of the high precision computation that the present invention proposes comprises following circuit block, its concrete structure as follows:

See Fig. 1, according to the different in kind of processing digital images, when handling gray level image, RGB cuts little ice to RGB transducer 14 with HSI to HSI transducer 9, directly the gray value of output digital video image; When handling digital color image, among RGB is transformed into the HSI color space with digital video image from rgb color space to HSI transducer 9.Among HSI is transformed into rgb color space with digital video image from the HSI color space to RGB transducer 14.

See Fig. 1, line storage group 10 is made up of sequential control circuit, read/write address generator and two-port RAM group; Sequential control circuit produces control corresponding read/write address generator, two-port RAM group, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12 down in the triggering of the row of input digit video flowing, a useful signal and operates required timing control signal with maximum comparator 13; The read/write address generator produces the read/write address of two-port RAM under the effect of timing control signal, and is responsible for handling read/write address initialization and rotating problem; Line storage group 10 is according to the input characteristics of serial digital video code stream; Utilize current input pixel; According to the different in kind of processing digital images, line storage group 10 adopts 2n line storage to accomplish the gray value of 2n+1 line of numbers video image or obtaining of the luminance component I value in the HSI color space.

See Fig. 1, lock phase/shift circuit group 11 is utilized current input pixel according to the input characteristics of serial digital video code stream, and according to the different in kind of the digital picture of handling, lock phase/shift circuit group 11 adopts 3n altogether ²+ 3n d type flip flop carries out a time-delay through the luminance component I to gray level image or digital color image and produces required (2n+1) * (2n+1) pel array of calculating digital image fractional order calculus; (2n+1) * (2n+1) the 1st of pel array the row adopts 2n d type flip flop, and the 2nd row adopts 2n-1 d type flip flop, all is to subtract n+1 d type flip flop of the capable employing of one, the n line by line until the capable every row of n adopts the number of d type flip flop; (2n+1) * (2n+1) 2n d type flip flop of the capable employing of the n+1 of pel array; (2n+1) * (2n+1) n+1 d type flip flop of the capable employing of the n+2 of pel array, n+2 d type flip flop of the capable employing of n+3 all is to add 2n d type flip flop of the capable employing of one, the 2n+1 line by line until the capable every row of 2n+1 adopts the number of d type flip flop.

See Fig. 1; Fractional calculus mask convolution circuit 12 is circuit blocks of realizing the fractional calculus most critical of digital picture in all forming circuit parts of fractional calculus filter of digital picture of high precision computation of the present invention, also is the core content of fractional calculus filter new departure of the present invention's digital picture of proposing this high precision computation.For the circuit that clearly demonstrates fractional calculus mask convolution circuit 12 constitutes, be necessary that elder generation carries out following brief description to the operation rule of fractional calculus mask convolution circuit:

Estimate down at Euclidean, what fractional calculus was the most frequently used is Gr ü mwald-Letnikov definition: $D_{G-L}^{v}s\left(x\right)=\frac{d^v}{{\left[d(x-a)\right]}^v}s\left(x\right){|}_{G-L}=\underset{N\→\∞}{\mathrm{Lim}}\left\{\frac{{\left(\frac{x-a}{N}\right)}^{-v}}{\mathrm{\Γ}(-v)}\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}\frac{\mathrm{\Γ}(k-v)}{\mathrm{\Γ}(k+1)}s(x-k\left(\frac{(x-a)}{N}\right))\right\}.$ Wherein, the duration of signal s (x) is x ∈ [a, x].V can be any plural number, and it is any real number (comprising mark) that the present invention gets v.

expression is based on the fractional order differential operator of Gr ü mwald-Letnikov definition.When v is that is the fractional order integration operator when bearing real number; When v is zero;

is the all-pass wave filtering operator, neither also integration not of differential; When v was arithmetic number,

was the fractional order differential operator.The Gr ü mwald-Letnikov of fractional calculus is defined in the integer step that Euclidean estimates down integer rank calculus and is generalized to the mark step-length, thereby the integer rank of calculus are generalized to fractional order.The calculating of the Gr ü mwald-Letnikov definition of fractional calculus is simple and easy to do; It only need be relevant with signal s (x) self the discrete sampling value of , and derivative and the integrated value of undesired signal s (x).

Be without loss of generality, the present invention makes a=0, and the duration x ∈ [0, x] of signal s (x) is carried out the N five equilibrium, total N+1 node.The value of this N+1 cause and effect pixel is respectively s _N≡ s (0), s _N-1≡ s (x/N) ..., s _k≡ s (x-kx/N) ..., s ₀≡ s (x).Wherein, k gets the integer between 0～N.Because Digital Image Processing is stored in the medium and carries out, in addition, owing to the border of image can be expanded it through the mode of cycle developing, so we can also handle the non-causal pixel in the digital picture.The value of this N+1 non-causal pixel is respectively s ₀≡ s (x), s _-1≡ s (x+x/N) ..., s _-k≡ s (x+kx/N) ..., s _-N≡ s (2x).Gr ü mwald-Letnikov definition based on fractional calculus; When enough big of N; Can remove limit symbol, so can derive to such an extent that sets up.Wherein,

expression Gamma function.In order to improve convergence rate and convergence precision; The present invention

is improved to

so; Except v=0; ± 2; ± 4; Outside, also introduced the signal value of signal s (x) in at non-node place.Three adjacent segments point values of the present invention's number of winning the confidence s (x)

means of Lagrange three point interpolation formula, so can derive:

$s\left(\mathrm{\ξ}\right)\≅\frac{(\mathrm{\ξ}-x+\frac{\mathrm{kx}}{N})(\mathrm{\ξ}-x+\frac{x}{N}+\frac{\mathrm{kx}}{N})}{2x^2/N^2}s(x+\frac{x}{N}-\frac{\mathrm{kx}}{N})\frac{(\mathrm{\ξ}-x-\frac{x}{N}+\frac{\mathrm{kx}}{N})(\mathrm{\ξ}-x+\frac{x}{N}+\frac{\mathrm{kx}}{N})}{x^2/N^2}s(x-\frac{\mathrm{kx}}{N})+\frac{(\mathrm{\ξ}-x-\frac{x}{N}+\frac{\mathrm{kx}}{N})(\mathrm{\ξ}-x+\frac{\mathrm{kx}}{N})}{{2x}^2/N^2}s(x-\frac{x}{N}-\frac{\mathrm{kx}}{N}).$

Then; The present invention makes

that signal s (x) is carried out the mark interpolation, can derive:

$s(x+\frac{\mathrm{Vx}}{2N}-\frac{\mathrm{Kx}}{N})\&cong;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})s(x+\frac{x}{N}-\frac{\mathrm{Kx}}{N})+(1-\frac{v^2}{4})s(x-\frac{\mathrm{Kx}}{N})+(\frac{v^2}{8}-\frac{v}{4})s(x-\frac{x}{N}-\frac{\mathrm{Kx}}{N})=(\frac{v}{4}+\frac{v^2}{8})s_{k-1}+(1-\frac{v^2}{4})s_k+(\frac{v^2}{8}-\frac{v}{4})s_{k+1}.$ And then can derive:

Be an approximate formula, it is summed up as simple multiplication and add operation with the fractional calculus of signal s (x), and it has also relaxed the condition restriction of N → ∞ in the fractional calculus Gr ü mwald-Letnikov definition simultaneously.

Because what computer or digital filter were handled is digital quantity, its value is limited; In addition; Because the gray value of picture signal or the maximum variable quantity of luminance component I value are limited; It is between two neighbors that the gray value of digital picture or luminance component I value change the beeline that takes place; So two-dimensional digital image s (x, y) duration on x and y direction of principal axis (size of image array) possibly be that unit measures with the pixel only, the minimum range between the neighbor only possibly be a pixel.(x, branches such as minimum y) possibly be pixel units only to s at interval.If s (x; Y) duration of variable x and y is respectively [0 in; X] and [0; Y]; Then the branches such as unit on x and y direction of principal axis be respectively at interval

and

its maximum isodisperse be respectively

and

visible; For Digital Image Processing; Even fractional calculus means of mask dimensions number is big to equaling digital picture s (x; Y) size number (is n+2=N=min (L; H)); Possibly be that the maximum of its fractional calculus analytic value is approached only also, and can not be equal to the analytic value of its fractional calculus.When k=n≤N-1, the s that can derive (x, y) the approximate backward difference of the preceding n+2 item of the inclined to one side calculus of fractional order is respectively on x and y reference axis negative direction:

$\frac{{\&PartialD;}^{v}s(x,y)}{{\&PartialD;x}^v}\&cong;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})s(x+1,y)+(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{2}-\frac{{\mathrm{<figure-callout\; id="3"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}^3}{8})s(x,y)$

$+\frac{1}{\mathrm{\&Gamma;}(-v)}\underset{k=1}{\overset{n-2}{\mathrm{\&Sigma;}}}[\frac{\mathrm{\&Gamma;}(k-v+1)}{(k+1)!}\&CenterDot;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})+\frac{\mathrm{\&Gamma;}(k-v)}{k!}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(k-v-1)}{(k-1)!}(-\frac{v}{4}+\frac{v^2}{8})\&CenterDot;]s(x-k,y)$ With

$+[\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(n-v-2)}{(n-2)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{\mathrm{<figure-callout\; id="4"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})]s(x-n+1,y)+\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})s(x-n,y)$

$\frac{{\&PartialD;}^{v}s(x,y)}{{\&PartialD;y}^v}\&cong;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})s(x,y+1)+(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{2}-\frac{{\mathrm{<figure-callout\; id="3"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}^3}{8})s(x,y)$

$+\frac{1}{\mathrm{\&Gamma;}(-v)}\underset{k=1}{\overset{n-2}{\mathrm{\&Sigma;}}}[\frac{\mathrm{\&Gamma;}(k-v+1)}{(k+1)!}\&CenterDot;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})+\frac{\mathrm{\&Gamma;}(k-v)}{k!}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(k-v-1)}{(k-1)!}\&CenterDot;(-\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})]s(x,y-k).$

$+[\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(n-v-2)}{(n-2)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{\mathrm{<figure-callout\; id="4"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})]s(x,y-n+1)+\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})s(x,y-n)$

See Fig. 1; Because in digital picture; Has very big correlation between neighborhood interior pixel and the pixel; In order to strengthen the anti-image rotatory of fractional calculus mask convolution circuit 12; Make it can on 8 symmetry directions, accomplish (x respectively to image s; Y) fractional calculus computing; (the present invention constructs the fractional calculus mask (expression with on x axle negative direction respectively for x, y) the approximate backward difference of the preceding n+2 item of the inclined to one side calculus of fractional order on x and y reference axis negative direction to utilize s; See Fig. 2), the fractional calculus mask on the y axle negative direction (Fig. 4 is seen in expression with

).In addition, the fractional calculus mask on the x axle positive direction (is used

Fig. 3 is seen in expression), the fractional calculus mask on the y axle positive direction (uses

Fig. 5 is seen in expression), a left side down the fractional calculus mask on the diagonal (use W _LDDFig. 6 is seen in expression), the fractional calculus mask on the upper right diagonal (uses W _RUDFig. 7 is seen in expression), the fractional calculus mask on the upper left diagonal (uses W _LUDFig. 8 is seen in expression), the fractional calculus mask on the diagonal line direction (uses W _RDDFig. 9 is seen in expression) with

With

Aufbauprinciple and method similar, repeat no more here.The present invention utilizes the fractional calculus mask on above-mentioned 8 directions can calculate s (x, y) approximation of the v rank fractional calculus on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side respectively.For computing easy, the present invention with s (x, y) in the approximation of the maximum v rank fractional calculus of above-mentioned 8 direction patrix values as s (x, the approximation of v rank fractional calculus y).

See Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9,

Be to cover s on the non-causal pixel _-1The fractional calculus mask numerical value of=s (x+x/N).

Be to cover point-of-interest s ₀Fractional calculus mask numerical value on the=s (x).When k → n=1, the present invention can construct 3 * 3 fractional calculus mask; When k → n=3, the present invention can construct 5 * 5 fractional calculus mask; When k → n=2m-1, the present invention can construct the fractional calculus mask of (n+2) * (n+2)=(2m+1) * (2m+1), and wherein n gets odd number, and m gets natural number.Fractional calculus mask numerical value of the present invention is respectively:

$C_{s_{-1}}=\frac{v}{4}+\frac{v^2}{8},$ $C_{s_0}=1-\frac{v^2}{2}-\frac{v^3}{8},$ $C_{s_1}=-\frac{5v}{4}+\frac{5v^3}{16}+\frac{v^4}{16},...,$

$C_{s_k}=\frac{1}{\mathrm{\&Gamma;}(-v)}[\frac{\mathrm{\&Gamma;}(k-v+1)}{(k+1)!}\&CenterDot;(\frac{v}{4}+\frac{v^2}{8})+\frac{\mathrm{\&Gamma;}(k-v)}{k!}\&CenterDot;(1-\frac{v^2}{4})+\frac{\mathrm{\&Gamma;}(k-v-1)}{(k-1)!}\&CenterDot;(-\frac{v}{4}+\frac{v^2}{8})],...,$

$C_{s_{n-2}}=\frac{1}{\mathrm{\&Gamma;}(-v)}[\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!}\&CenterDot;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})+\frac{\mathrm{\&Gamma;}(n-v-2)}{(n-2)!}\&CenterDot;(1-\frac{v^2}{4})+\frac{\mathrm{\&Gamma;}(n-v-3)}{(n-3)!}\&CenterDot;(-\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})],$

$C_{s_{n-1}}=\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(n-v-2)}{(n-2)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8}),$ $C_{s_n}=\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!\mathrm{\&Gamma;}(-v)}\&CenterDot;(-\frac{\mathrm{<figure-callout\; id="4"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})$ (n+2) * (n+2) of the present invention fractional calculus mask is a sparse matrix, and its mask coefficient is a n+2 nonzero value, and they all are the functions of fractional order differential order v.Can prove that said n+2 a fractional calculus mask coefficient sum is not equal to zero, this is one of image fractional calculus mask and the remarkable difference on characteristic of image integer rank calculus mask.

Because the Digital Image Processing of computer or digital filter is directly to be treated to the basis to discrete pixel; So the numerical operation rule of fractional calculus mask adopts the airspace filter scheme of fractional calculus mask convolution too, the mode of this space filtering be exactly in pending digital picture pointwise move and corresponding long-pending and fractional calculus mask.The operation rule of fractional calculus mask convolution circuit 12 is airspace filters that the scheme of employing fractional calculus mask convolution realizes digital image fractional order calculus, is fit to realize data image signal is carried out handled with hardware circuit.Fractional calculus mask convolution circuit 12 to the operation rule of gray level image and digital color image is:

A. fractional calculus mask convolution circuit 12 is to the operation rule of gray level image.The gray level image s of L * H (x, y) in, on above-mentioned 8 directions, carry out convolutional filtering with the fractional calculus mask of (n+2) * (n+2)=(2m+1) * (2m+1) of the present invention,

W _LDD, W _RUD, W _LUDAnd W _RDDThe numerical operation rule be respectively:

$s_{x^{-}}^{\left(v\right)}(x,y)=\underset{i=-2m}{\overset{1}{\mathrm{\&Sigma;}}}\underset{j=-m}{\overset{m}{\mathrm{\&Sigma;}}}{W}_x^{-}(i,j)s(x+i,y+j),$ $s_{x^{+}}^{\left(v\right)}(x,y)=\underset{i=-1}{\overset{2m}{\mathrm{\&Sigma;}}}\underset{j=-m}{\overset{m}{\mathrm{\&Sigma;}}}{W}_x^{+}(i,j)s(x+i,y+j),$

$s_{y^{-}}^{\left(v\right)}(x,y)=\underset{i=-m}{\overset{m}{\mathrm{\&Sigma;}}}\underset{j=-2m}{\overset{1}{\mathrm{\&Sigma;}}}{W}_y^{-}(i,j)s(x+i,y+j),$ $s_{y^{+}}^{\left(v\right)}(x,y)=\underset{i=-m}{\overset{m}{\mathrm{\&Sigma;}}}\underset{j=-1}{\overset{2m}{\mathrm{\&Sigma;}}}{W}_y^{+}(i,j)s(x+i,y+j),$

$s_{\mathrm{LDD}}^{\left(v\right)}(x,y)=\underset{i=-1}{\overset{2m}{\mathrm{\&Sigma;}}}\underset{j=-2m}{\overset{1}{\mathrm{\&Sigma;}}}{W}_{\mathrm{LDD}}(i,j)s(x+i,y+j),$ $s_{\mathrm{RUD}}^{\left(v\right)}(x,y)=\underset{i=-2m}{\overset{1}{\mathrm{\&Sigma;}}}\underset{j=-1}{\overset{2m}{\mathrm{\&Sigma;}}}{W}_{\mathrm{RUD}}(i,j)s(x+i,y+j),$

$s_{\mathrm{LUD}}^{\left(v\right)}(x,y)=\underset{i=-2\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="HSA00000051205500021.png,HSA00000051205500022.png"\; state="\{\{state\}\}">m</figure-callout>}}{\overset{1}{\mathrm{\&Sigma;}}}\underset{j=-2m}{\overset{1}{\mathrm{\&Sigma;}}}{W}_{\mathrm{LUD}}(i,j)s(x+i,y+j),$ $s_{\mathrm{RDD}}^{\left(v\right)}(x,y)=\underset{i=-1}{\overset{2m}{\mathrm{\&Sigma;}}}\underset{j=-1}{\overset{2m}{\mathrm{\&Sigma;}}}{W}_{\mathrm{RDD}}(i,j)s(x+i,y+j).$

B. fractional calculus mask convolution circuit 12 is to the operation rule of digital color image.Because digital color image s (x; Y) there is correlation between each component of the RGB of each pixel in; And its value generally is limited between [0,255], therefore; Fractional calculus can destroy the correlation of R, G, three components of B, and color distortion possibly appear in the coloured image of handling through fractional calculus.For these reasons, the present invention only handles the fractional calculus of the luminance component I value of digital color image in the HSI color space.Fractional calculus mask convolution circuit 12 is identical with its operation rule and parameter to gray level image to the operation rule of the luminance component I value of digital color image.

Specify the circuit structure of fractional calculus mask convolution circuit 12 below: see Fig. 1, fractional calculus mask convolution circuit 12 is made up of the specific first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 of 8 parallel computations; The first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 calculates the approximation of the gray value of each pixel of digital video image or the v rank fractional calculus of the luminance component I value in the HSI color space on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side respectively.

See Fig. 1 and Figure 10, each algorithm unit circuit is made up of the n+2 identical with fractional calculus mask size number first multiplier to the, seven multipliers 15～21 and an adder 22; The non-zero weights of this n+2 multiplier are respectively in order:

$...,\frac{1}{\mathrm{\&Gamma;}(-v)}[\frac{\mathrm{\&Gamma;}(k-v+1)}{(k+1)!}\&CenterDot;(\frac{v}{4}+\frac{v^2}{8})+\frac{\mathrm{\&Gamma;}(k-v)}{k!}\&CenterDot;(1-\frac{v^2}{4})+\frac{\mathrm{\&Gamma;}(k-v-1)}{(k-1)!}\&CenterDot;(-\frac{v}{4}+\frac{v^2}{8})],$ ,

$\frac{1}{\mathrm{\&Gamma;}(-v)}[\frac{\mathrm{\&Gamma;}(n-v-1)}{(n-1)!}\&CenterDot;(\frac{v}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})+\frac{\mathrm{\&Gamma;}(n-v-2)}{(n-2)!}\&CenterDot;(1-\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{4})+\frac{\mathrm{\&Gamma;}(n-v-3)}{(n-3)!}\&CenterDot;(-\frac{\mathrm{<figure-callout\; id="4"\; label="v"\; filenames="HSA00000051205500011.png"\; state="\{\{state\}\}">v</figure-callout>}}{4}+\frac{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="HSA00000051205500011.png,HSA00000051205500021.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}{8})],$

With The output valve feed-in maximum comparator 13 of adder 22.

See Fig. 1, fractional calculus mask convolution circuit 12 is made up of the specific first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 of following 8 parallel computations:

The first algorithm unit circuit, 1 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on x axle negative direction; Pixel S _x(gray value of k+n (H+1)+H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The second algorithm unit circuit, 2 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on x axle positive direction; Pixel S _x(gray value of k+n (H+1)-H) or luminance component I value and the weights in the HSI color space Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

Algorithm element circuit 3 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on y axle negative direction; Pixel S _xThe gray value of (k+n (H+1)+1) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-1) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i) or luminance component I value and the weights in the HSI color space Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1)) or luminance component I value and the weights in the HSI color space Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-n) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The 4th algorithm unit circuit 4 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on y axle positive direction; Pixel S _xThe gray value of (k+n (H+1)-1) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+1) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+n) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The 5th algorithm unit circuit 5 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order under a left side on the diagonal; Pixel S _x(gray value of k+n (H+1)+1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)+(n-2) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1)+(n-1) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-n+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The 6th algorithm unit circuit 6 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on upper right diagonal; Pixel S _x(gray value of k+n (H+1)-1+H) or luminance component I value and the weights in the HSI color space Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+1-H) or luminance component I value and the weights in the HSI color space Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i-iH) or luminance component I value and the weights in the HSI color space Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)-(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)-(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+n-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The 7th algorithm unit circuit 7 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on upper left diagonal; Pixel S _x(gray value of k+n (H+1)+1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-1-H) or luminance component I value and the weights in the HSI color space Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i-iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)-(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1)-(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)-n-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

The 8th algorithm unit circuit 8 calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on diagonal line direction; Pixel S _x(gray value of k+n (H+1)-1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier 15, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier 16, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier 17, back feed-in adder 22 multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier 18, back feed-in adder 22 multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)+(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier 19, back feed-in adder 22 multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)+(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier 20, back feed-in adder 22 multiplies each other; Pixel S _x(gray value of k+n (H+1)+n+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier 21, back feed-in adder 22 multiplies each other.

See Fig. 1, maximum comparator 13 value that mould value in the first algorithm unit circuit, 1 to the 8th algorithm unit circuit, 8 output valves of fractional calculus mask convolution circuit 12 is maximum is as pixel S _xThe approximation of the v rank fractional calculus of (k+n (H+1)).Maximum comparator 13 has 8 tunnel inputs, 1 tunnel output, and the output valve of the feed-in first algorithm unit circuit 1 to the 8th algorithm unit circuit 8 is exported the maximum value of mould value in above-mentioned 8 feed-in values respectively.

New departure below in conjunction with the fractional calculus filter of the digital picture of accompanying drawing and the high precision computation of the present invention of circuit arrangement example in detail:

Description of drawings

Fig. 1 is the electrical block diagram of fractional calculus filter of the digital picture of high precision computation of the present invention.

Fig. 2 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on x axle negative direction of the first algorithm unit circuit 1.

Fig. 3 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on x axle positive direction of the second algorithm unit circuit 2.

Fractional calculus mask (n+2) * (n+2) the square formation sketch map on y axle negative direction of Fig. 4 algorithm element circuit 3.

Fig. 5 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on y axle positive direction of the 4th algorithm unit circuit 4.

Fig. 6 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on the diagonal under a left side of the 5th algorithm unit circuit 5.

Fig. 7 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on upper right diagonal of the 6th algorithm unit circuit 6.

Fig. 8 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on upper left diagonal of the 7th algorithm unit circuit 7.

Fig. 9 is fractional calculus mask (n+2) * (n+2) the square formation sketch map on the diagonal line of the 8th algorithm unit circuit 8.

Figure 10 is the common electrical block diagram of the first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8.

Figure 11 is the fractional calculus filter circuit diagram of the digital picture of the high precision computation when the v rank fractional order differential mask on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, a left side all is 5 * 5 square formation.

Wherein, 1 is the first algorithm unit circuit; 2 is second algorithm unit circuit; 3 is algorithm element circuits; 4 is the 4th algorithm unit circuit; 5 is the 5th algorithm unit circuit; 6 is the 6th algorithm unit circuit; 7 is the 7th algorithm unit circuit; 8 is the 8th algorithm unit circuit; The 9th, RGB is to the HSI transducer; The 10th, the line storage group; The 11st, lock phase/shift circuit group; The 12nd, fractional calculus mask convolution circuit; The 13rd, the maximum comparator; The 14th, HSI is to the RGB transducer; 15 is first multipliers; 16 is second multipliers; 17 is the 3rd multipliers; 18 is the 4th multipliers; 19 is the 5th multipliers; 20 is the 6th multipliers; 21 is the 7th multipliers; The 22nd, adder; 23～28th, the line storage that function is identical with parameter; The 29th, the maximum comparator identical with parameter with 13 functions; The A point is the serial digital video code stream S of fractional calculus filter of the digital picture of high precision computation _x(k) input point; The B point is weights

Input point; The C point is weights Input point; The E point is weights

Input point; The F point is weights

Input point; The G point is weights

Input point; The H point is pixel S _xThe output point of the luminance component I value in gray value (k+3H+3) or the HSI color space.The above-mentioned first algorithm unit circuit to the, eight algorithm unit circuit are output pixel S respectively _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side.

Embodiment

Now be described below for example:

See Fig. 1 and Figure 11; In the engineering practical application; The scheme of the fractional calculus mask convolution of the normal employing 5 * 5 of the operation rule of the fractional calculus mask convolution circuit 12 in the fractional calculus filter of the digital picture of high precision computation realizes the pixel S (x to digital picture; Y) the inclined to one side calculus of v rank fractional order; Order v generally gets mark or reasonable fractional value between-2～+ 2, can be known by above-mentioned explanation: the v rank fractional calculus mask on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side (

W _LDD, W _RUD, W _LUDAnd W _RDD) size number n+2=5,5 zero coefficient values in the v rank fractional calculus mask on above-mentioned 8 directions are respectively in order:

With

Wherein line storage group 10 adopts 2n| _N=3=6 line storages are accomplished 2n+1| _N=3Obtaining of the gray value of=7 line of numbers video images or luminance component I value; Wherein lock phase/shift circuit group 11 and adopt 3n altogether ²+ 3n| _N=3=36 d type flip flops, carry out a time-delay through the luminance component I to gray level image or digital color image and produce required (2n+1) * (2n+1) of calculating digital image fractional order calculus | _N=3=7 * 7 pel arrays; Wherein the first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 has 8 * (n+2)-7| _N=3=33 multipliers, in each algorithm unit circuit (n+2) | _N=3The non-zero weights of=5 multipliers are respectively in order:

With

So; Shown in figure 11; The cascade circuit structure of the fractional calculus filter of the digital picture of the high precision computation of the present invention that is specified in the summary of the invention according to this specification and RGB thereof particular circuit configurations and the circuit parameter to HSI transducer 9, line storage group 10, lock phase/shift circuit group 11, fractional calculus mask convolution circuit 12, maximum comparator 13 and HSI to RGB transducer 14 just can construct the physical circuit of fractional calculus filter of the digital picture of this high precision computation easily.Under the prerequisite that does not influence accurate statement, in order to describe the physical circuit of the first algorithm unit circuit, 1 to the 8th algorithm unit circuit 8 wherein more clearly, Figure 11 do not draw sequential control circuit wherein and the timing control signal that is triggered and produces thereof.

Claims (6)

1. the fractional calculus filter of the digital picture of a high precision computation is characterized in that: it is to be formed to RGB transducer (14) cascade with HSI to HSI transducer (9), line storage group (10), lock phase/shift circuit group (11), fractional calculus mask convolution circuit (12), maximum comparator (13) by RGB; Serial digital video code stream S _x(k) behind the fractional calculus filter of the digital picture of input high precision computation; After HSI transducer (9) is handled, gray value or brightness I component are divided into three the tunnel through RGB: after the first via is passed through line storage group (10), lock phase/shift circuit group (11), fractional calculus mask convolution circuit (12) processing in proper order, difference output pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on diagonal, upper right diagonal, upper left diagonal and 8 directions of diagonal line under x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, the left side; After passing through maximum comparator (13) processing again, the value of exporting the mould value maximum in above-mentioned 8 approximations is as pixel S _xThe v rank fractional calculus value approximation S of (k+n (H+1)) _x ^(v)(k+n (H+1)); The second the tunnel triggers sequential control circuit produces corresponding timing control signal; The output of Third Road and line storage group (10) together the feed-in lock mutually/shift circuit group (11) generates the pel array of (2n+1) * (2n+1).Wherein, the value of k subtracts one one by one by L * H-1, until being zero; The value of L equals the positive integer of the digital picture line number of pending fractional calculus; The value of H equals the positive integer of the digital picture columns of pending fractional calculus; N gets any odd number between [3, min (L, H)-2], and (L H) gets minimum value among L and the H to min; V gets any mark or the reasonable fractional value between [m, m], and m gets any positive integer.

2. the fractional calculus filter of the digital picture of a kind of high precision computation according to claim 1; It is characterized in that: when handling gray level image; RGB wherein cuts little ice to RGB transducer (14) to HSI transducer (9) and HSI, directly the gray value of output digital video image; When handling digital color image; Among RGB wherein is transformed into the HSI color space with digital video image from rgb color space to HSI transducer (9), among HSI is transformed into rgb color space with digital video image from the HSI color space to RGB transducer (14).

3. the fractional calculus filter of the digital picture of a kind of high precision computation according to claim 1, it is characterized in that: line storage group (10) wherein is made up of sequential control circuit, read/write address generator and two-port RAM group; Sequential control circuit produces control corresponding read/write address generator, two-port RAM group, lock phase/shift circuit group (11), fractional calculus mask convolution circuit (12) down in the triggering of the row of input digit video flowing, a useful signal and operates required timing control signal with maximum comparator (13); The read/write address generator produces the read/write address of two-port RAM under the effect of timing control signal, and is responsible for handling read/write address initialization and rotating problem; Line storage group (10) is according to the input characteristics of serial digital video code stream; Utilize current input pixel; According to the different in kind of processing digital images, line storage group (10) adopts 2n line storage to accomplish the gray value of 2n+1 line of numbers video image or obtaining of the luminance component I value in the HSI color space.

4. the fractional calculus filter of the digital picture of a kind of high precision computation according to claim 1; It is characterized in that: lock phase wherein/shift circuit group (11) is according to the input characteristics of serial digital video code stream; Utilize current input pixel; According to the different in kind of the digital picture of handling, lock phase/shift circuit group (11) adopts 3n altogether ²+ 3n d type flip flop carries out a time-delay through the luminance component I to gray level image or digital color image and produces required (2n+1) * (2n+1) pel array of calculating digital image fractional order calculus; (2n+1) * (2n+1) the 1st of pel array the row adopts 2n d type flip flop, and the 2nd row adopts 2n-1 d type flip flop, all is to subtract n+1 d type flip flop of the capable employing of one, the n line by line until the capable every row of n adopts the number of d type flip flop; (2n+1) * (2n+1) 2n d type flip flop of the capable employing of the n+1 of pel array; (2n+1) * (2n+1) n+1 d type flip flop of the capable employing of the n+2 of pel array, n+2 d type flip flop of the capable employing of n+3 all is to add 2n d type flip flop of the capable employing of one, the 2n+1 line by line until the capable every row of 2n+1 adopts the number of d type flip flop.

5 according to claim 1, wherein a high-precision digital image calculated fractional calculus filter, wherein: one of the fractional calculus mask convolution circuit (12) by the eight parallel computing specific first algorithm unit circuit (1) to the eighth arithmetic unit circuit (8) form; first algorithm unit circuit (1) to the eighth arithmetic unit circuit (8) were calculated for each pixel of the digital video image gray value or HSI color space values of the luminance component I in the x-axis negative direction, x-axis positive direction, y-axis negative direction, y-axis positive direction, left diagonal, diagonal right, upper left diagonal and lower right diagonal 8 direction v order approximation of fractional calculus; each algorithm unit circuit consists of fractional calculus with the same number of mask size n +2 a first multiplier to seventh multiplier (15 to 21) and an adder (22) composition; these n +2 th multipliers in order nonzero weights are:

and

adder (22) fed into the maximum output value of the comparator (13); fractional calculus mask convolution circuit (12) by the following eight specific first parallel computing algorithm unit circuit (1) to eighth arithmetic unit circuit (8) composition:

First algorithm unit circuit (1) the calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on x axle negative direction; Pixel S _x(gray value of k+n (H+1)+H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (n+1)-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

Second algorithm unit circuit (2) the calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on x axle positive direction; Pixel S _x(gray value of k+n (H+1)-H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

Algorithm element circuit (3) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on y axle negative direction; Pixel S _xThe gray value of (k+n (H+1)+1) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-1) or luminance component I value and the weights in the HSI color space Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)) or luminance component I value and the weights in the HSI color space Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-n) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

The 4th algorithm unit circuit (4) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on y axle positive direction; Pixel S _xThe gray value of (k+n (H+1)-1) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+1) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+n) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

The 5th algorithm unit circuit (5) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order under a left side on the diagonal; Pixel S _x(gray value of k+n (H+1)+1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)+(n-2) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _zThe gray value of (k+n (H+1)-(n-1)+(n-1) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-n+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

The 6th algorithm unit circuit (6) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on upper right diagonal; Pixel S _x(gray value of k+n (H+1)-1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i-iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)-(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)-(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+n-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

The 7th algorithm unit circuit (7) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on upper left diagonal; Pixel S _x(gray value of k+n (H+1)+1+H) or luminance component I value and the weights in the HSI color space Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)-i-iH) or luminance component I value and the weights in the HSI color space Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)-(n-2)-(n-2) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)-(n-1)-(n-1) H) or luminance component I value and the weights in the HSI color space Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)-n-nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other;

The 8th algorithm unit circuit (8) calculating pixel S _xThe approximation of (k+n (H+1)) inclined to one side calculus of v rank fractional order on diagonal line direction; Pixel S _x(gray value of k+n (H+1)-1-H) or luminance component I value and the weights in the HSI color space

Difference feed-in first multiplier (15), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)) or luminance component I value and the weights in the HSI color space

Difference feed-in second multiplier (16), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+1+H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 3rd multiplier (17), back feed-in adder (22) multiplies each other; By that analogy, if 1≤i≤n+2, pixel S _x(gray value of k+n (H+1)+i+iH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 4th multiplier (18), back feed-in adder (22) multiplies each other; By that analogy, pixel S _xThe gray value of (k+n (H+1)+(n-2)+(n-2) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 5th multiplier (19), back feed-in adder (22) multiplies each other; Pixel S _xThe gray value of (k+n (H+1)+(n-1)+(n-1) H) or luminance component I value and the weights in the HSI color space

Difference feed-in the 6th multiplier (20), back feed-in adder (22) multiplies each other; Pixel S _x(gray value of k+n (H+1)+n+nH) or luminance component I value and the weights in the HSI color space

Difference feed-in the 7th multiplier (21), back feed-in adder (22) multiplies each other.

6. the fractional calculus filter of the digital picture of a kind of high precision computation according to claim 1 is characterized in that: the value that mould value in the first algorithm unit circuit (1) to the 8th algorithm unit circuit (8) output valve of fractional calculus mask convolution circuit (12) is maximum of maximum comparator (13) wherein is as pixel S _xThe approximation of the v rank fractional calculus of (k+n (H+1)).Maximum comparator (13) has 8 tunnel inputs, 1 tunnel output, and the output valve of the feed-in first algorithm unit circuit (1) to the 8th algorithm unit circuit (8) is exported the maximum value of mould value in above-mentioned 8 feed-in values respectively.

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