CN103369326B

CN103369326B - Be suitable to the transform coder of high-performance video coding standard HEVC

Info

Publication number: CN103369326B
Application number: CN201310283390.3A
Authority: CN
Inventors: 李甫; 樊春晓; 牛毅; 石光明; 齐飞; 周蕾蕾; 张犁; 宋晓丹; 焦丹丹
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2013-07-05
Filing date: 2013-07-05
Publication date: 2016-06-29
Anticipated expiration: 2033-07-05
Also published as: CN103369326A

Abstract

The invention discloses a kind of transform coder being suitable to high-performance video coding standard HEVC, mainly solve multiplier in prior art and use too much, the problem that circuit is complicated.Comprising: one-dimensional DCT module (1), transposition buffer module (2) and top layer control module (3), wherein one-dimensional DCT module (1) adopts the various dct transforms that multiple butterfly processing element and multiple strange coefficient processing unit complete in HEVC standard, this strange coefficient processing unit, by complicated multiplication operation being decomposed to multi-level pmultistage circuit and using shift unit, adder and subtractor to realize, namely stages shift device, adder and subtractor is used to substitute matrix multiplier, to simplify circuit structure.It is regular that the present invention has simple in construction, and reusing degree is high, and critical path is short, and clock frequency is high, it is easy to integrated advantage, can realize the transition coding to video residual error data efficiently when not using multiplier.

Description

Be suitable to the transform coder of high-performance video coding standard HEVC

Technical field

The invention belongs to electronic circuit technology field, be specifically related to the transform coder structure in video compression coding standard HEVC, can be applicable to VLSI designs.

Background technology

It is known that along with the development of electronics and information industry, the application of digital video technology has become increasingly extensive.But, along with the continuous lifting of image resolution ratio, the data volume of its correspondence also increases therewith.Contradiction between these mass data and hard-disk capacity and channel capacities also seems and becomes increasingly conspicuous.Thus, existing compression algorithm is proposed huge challenge by High Data Rate, big data quantity problem, becomes a big bottleneck of extension high-resolution video application.How to reduce data volume when not losing or do not lose information as far as possible and have become as the problem that people are studying.Therefore, many image/video compression algorithms are proposed in succession by people.

Wherein, HEVC, as up-to-date video compression coding standard, which employs a lot of efficient image compression algorithm.Relative to H.264 video compression coding standard, it have employed finer tree-shaped partitioned organization so that the piecemeal of image is finer；And the size of basic block is also increased to 64 × 64 by the 16 × 16 of H.264 middle employing so that it is be more suitable for the compression of big image.But while obtaining higher compression efficiency, the computational complexity of its correspondence is also greatly increased.Lifting along with basic block size, the size of HEVC converter unit also increases therewith, and it need to support 4 × 4,8 × 8,16 × 16 and 32 × 32 4 kinds of dct transforms so that the multiplier number in its corresponding circuits sharply increases, translation circuit becomes sufficiently complex, becomes a hard-wired difficult point.Thus, design an efficient transform coder and seem particularly significant.

So far, in order to reduce the multiplier number in transition coding module, reduce transition coding module complexity, it has been suggested that transition coding structure mainly have following two:

The first is the structure that the part butterfly adopted in HEVC test model combines with matrix multiplier, it makes use of the symmetry of basic matrix in transition coding, decreases the multiplier number of 3 times.This structure is made up of four butterfly structures and four matrix multipliers.Wherein, butterfly structure is made up of a series of adders and subtractor, after butterfly structure, computing is divided into two parts, even segments and odd number part, this odd number part completes to calculate by the translation circuit that multiplexing transform block size is less, and this even segments is then use matrix multiplier to be calculated.Although this structure passes through optimization, but in its matrix multiplier, the number of multiplier is still a lot, and not easily hardware realizes.

The second is the patent application " being suitable to the transform coder of HEVC standard " (number of patent application 201210251115.9, publication number CN102857756A) that Xian Electronics Science and Technology University proposes.A kind of transform coder being suitable to HEVC standard of this Invention Announce, is mainly used in solving part butterfly and uses too much problem with multiplier in matrix multiplier combined structure.This structure includes one-dimensional DCT/DST module, transposition buffer module and topside control unit.Wherein, one-dimensional DCT/DST module, in conjunction with butterfly structure and matrix multiplication array, completes the various transition codings of HEVC；Transposition buffer module utilizes the storage different with memorizer in the path delay between depositor and reading order, completes the transposition operation of transform data；Topside control unit produces the reset of one-dimensional DCT/DST module and transposition buffer module and enables signal, controls the work of each module coordination.But the one-dimensional transform module in this structure still to use 48 multipliers, and its circuit structure is more complicated, is unfavorable for that hardware-efficient realizes, and its clock cycle required when realizing relatively large transition coding is also long.

Summary of the invention

Present invention aims to the deficiency of above-mentioned prior art, a kind of transform coder being suitable to high-performance video coding standard HEVC is proposed, to reduce the complexity of circuit structure, reduce the clock cycle required during transition coding, being prone to hardware realize, the high-performance meeting HEVC coding standard realizes requirement.

Realizing the object of the invention technical thought is: by part butterfly is decomposed with the matrix multiplication operation in matrix multiplier combined structure, the operation of the multiplication of its complexity is decomposed to multi-level pmultistage circuit complete, namely operation is completed by simple shift unit and adder, the computational complexity making every stage circuit is substantially reduced, thus shortening critical path, improve clock frequency and the code efficiency of transition coding circuit, finally give a transform coder being suitable to high-performance video coding standard HEVC not comprising multiplier.

According to above-mentioned thinking, the transform coder of the present invention includes: one-dimensional DCT module, transposition buffer module and top layer control module, the data output end of this one-dimensional DCT module is connected with the data input pin of transposition buffer module, and data input pin is connected with the data output end of transposition buffer module；This top layer controls module and is connected with the reset terminal of one-dimensional DCT module, Enable Pin and the reset terminal of transposition buffer module, Enable Pin respectively, it is characterised in that:

Described one-dimensional DCT module, including:

32 butterfly processing elements, for completing the operation coefficient to be transformed of input being added between two and subtracting each other between two, and will add up 16 data obtaining of operation and input to 16 butterfly processing elements, 16 data phase reducing obtained input to 32 strange coefficient processing unit；

16 butterfly processing elements, for completing the operation that 16 data of 32 butterfly processing element inputs are added between two and are subtracted each other between two, and will add up 8 data obtained and input to 8 butterfly processing elements, input to 16 strange coefficient processing unit by subtracting each other 8 data obtained；

32 strange coefficient processing unit, for obtain 16 data by the input of 32 butterfly processing elements and these 16 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 16 groups different, be added, subtract each other, try to achieve 16 transform datas, and input to transposition buffer module；

8 butterfly processing elements, for completing the operation that 8 data of 16 butterfly processing element inputs are added between two and are subtracted each other between two, and will add up 4 data obtained and input to 4 butterfly processing elements, input to 8 strange coefficient processing unit by subtracting each other 4 data obtained；

16 strange coefficient processing unit, for obtain 8 data by the input of 16 butterfly processing elements and these 8 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 8 groups different, be added, subtract each other, try to achieve 8 transform datas, and input to transposition buffer module；

4 butterfly processing elements, for completing 4 data of 8 butterfly processing element inputs are added between two and are subtracted each other between two, and will add up 2 data obtained and input to 4 even coefficient processing unit, input to 4 strange coefficient processing unit by subtracting each other 2 data obtained；

8 strange coefficient processing unit, for obtain 4 data by the input of 8 butterfly processing elements and these 4 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 4 groups different, be added, subtract each other, try to achieve 4 transform datas and input to transposition buffer module；

4 even coefficient processing unit, have been used for 2 data of 4 butterfly processing elements input are postponed, and shifter-adder, the operation subtracted each other, try to achieve 2 transform datas and input to transposition buffer module；

4 strange coefficient processing unit, for obtain 2 data by the input of 4 butterfly processing elements and these 2 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 2 groups different, be added, subtract each other, try to achieve 2 transform datas and input to transposition buffer module；

Reset and enable control unit, control module with top layer and be connected, control the reset of module output for receiving top layer and enable signal, and according to the reset of unit resetted and enable in the signal one-dimensional DCT module of control and enable.

The present invention compared with prior art has the advantage that

First, present invention employs unified conversion and realize structure, it is possible to use same encoder circuit completes the dct transform of 4 kinds of different masses sizes, thus improve the extent for multiplexing of circuit, being greatly reduced circuit scale；

Second, the one-dimensional DCT module that the present invention adopts, complete by complicated multiplying is assigned in multi-level pmultistage circuit, the strange coefficient processing unit not comprising multiplier is used to complete the multiplication operation of complexity, reduce the complexity in every stage circuit, improve system clock frequency, be more suitable for hardware and realize；

Accompanying drawing explanation

Fig. 1 is the population structure block diagram of transform coder of the present invention；

Fig. 2 is transposition buffer module structural representation of the present invention；

Fig. 3 is the structured flowchart of one-dimensional DCT module in the present invention；

Fig. 4 is structure and the connection diagram of 32 butterfly processing elements, 16 butterfly processing elements, 8 butterfly processing elements and 4 butterfly processing elements in the present invention；

Fig. 5 is the structure chart of 4 even coefficient processing unit in the present invention；

Fig. 6 is the structure chart of 4 strange coefficient processing unit in the present invention；

Fig. 7 is the structure chart that in the present invention, 8 dot factors are added subelement；

Fig. 8 is the structure chart that in the present invention, 16 dot factors are added subelement；

Fig. 9 is the structure chart that in the present invention, 32 dot factors are added subelement.

Detailed description of the invention

The present invention is to the improvement of one-dimensional transform structure in existing HEVC standard, it is possible to reduce the computational complexity of every grade of flowing water, improves system clock, and is easier to the Parallel Implementation of hardware.

Below in conjunction with drawings and Examples, the present invention is described in detail.

With reference to Fig. 1, the transform coder of the high-performance video coding standard HEVC of the present invention, controlled module 3 by one-dimensional DCT module 1, transposition buffer module 2 and top layer to constitute, wherein the output of top layer control module 3 is divided into two-way, the first via is connected with one-dimensional DCT module 1, and the second tunnel is connected with transposition buffer module 2；The input of the data input pin of one-dimensional DCT module 1 is divided into two-way, the first via and outside input data cube computation, and the second tunnel is connected with the data output end of transposition buffer module 2；The data output end of one-dimensional DCT module 1 is connected with the data input pin of transposition buffer module 2；The data input pin of transposition buffer module 2 is connected with the data output end of one-dimensional DCT module 1, and the output of the data output end of transposition buffer module 2 is divided into two-way, and the first via is connected with the data input pin of one-dimensional DCT module 1, and the second tunnel is connected with outside outfan.Wherein:

Described top layer controls module 3, module 30 and data flow control module 31 is enabled including resetting, the enable that resets module 30 enables unit 20 with the transposition reset enabling control unit 19 and transposition buffer module 2 that resets of one-dimensional DCT module 1 respectively and is connected, and enables and reset signal for the offer of the two module；Data flow control module 31 is connected with the address control unit 22 of transposition buffer module 2, is used for producing control signal, controls read-write mode and the read-write order of transposition buffer module 2.This reset enables module 30 and data flow control module 31 and constitutes by enumerator and logic circuit, for the count status according to enumerator and the alternative types that currently carries out, the reset of one-dimensional DCT module 1 is produced by logic circuit, enable the reset with transposition buffer module 2, enable, data flow con-trol signal, control the one-dimensional DCT module 1 input data to transform coder and carry out one-dimensional line translation, and produce control signal and control transposition buffer module 2 and receive the line translation result of one-dimensional DCT module 1, after All Datarows has processed, control transposition buffer module 2 and the line translation result output after transposition is carried out one-dimensional rank transformation to one-dimensional DCT module 1.

With reference to Fig. 2, described transposition buffer module 2, reset including transposition and enable unit 20, RAM memory 21 and address control unit 22, transposition reset enables unit 20 and is made up of logic circuit, control, for receiving top layer, reset, the enable signal that module 3 sends, and produce reset and the enable of control signal control RAM memory 21 and address control unit 22；RAM memory 21 is made up of 8 memory arrays, and each memory array is all connected with one-dimensional DCT module 1；Address control unit 22 is connected with the address end of each memory array in RAM memory 21, for producing input and output enable and the I/O Address of each memorizer, realize being stored in 8 memory arrays the dct transform result that one-dimensional DCT module 1 inputs respectively, then the operation exported row wise or column wise.

Described one-dimensional DCT module 1, has been used for 4 DCT in HEVC standard, 8 DCT, 16 DCT and 32 DCT one-dimensional transforms, and its structure is as shown in Figure 3.

With reference to Fig. 3, one-dimensional DCT module 1, including 32 butterfly processing elements 10,16 butterfly processing elements 11,32 strange coefficient processing unit, 13,16 strange coefficient processing unit 14 of 12,8 butterfly processing elements, 4 butterfly processing elements 15,8 strange coefficient processing unit, 17,4 strange coefficient processing unit 18 of 16,4 even coefficient processing unit, reset and enable control unit 19, wherein:

Described reset enables control unit 19, it is made up of logic circuit, its unit enabling unit 30 and one-dimensional DCT module 1 that resets controlling module 3 with top layer is connected, control the reset of module 3 output for receiving top layer and enable signal, and controlling reset and the enable of unit in whole one-dimensional DCT module 1 according to resetting and enabling signal.

Described 32 butterfly processing elements 10, are made up of 16 adders and 16 subtractors, and these 16 adders are connected with 16 butterfly processing elements 11, and these 16 subtractors and 32 strange coefficient processing unit 12 are connected, as shown in Figure 4.

32 data inputted from one-dimensional DCT module 1 input are carried out head and the tail and sue for peace between two by these 16 adders, namely try to achieve the 1st data and the 32nd data sum E₀, then ask the 2nd data and the 31st data sum E₁, and so on, try to achieve the 16th data and the 17th data sum E₁₅, and 16 the addition result E that will try to achieve₀～E₁₅Input to 16 butterfly processing elements 11；

32 coefficients inputted from one-dimensional DCT module 1 input are carried out head and the tail and ask poor between two by these 16 subtractors, namely try to achieve the difference O of the 1st data and the 32nd data₀, then try to achieve the difference O of the 2nd data and the 31st data₁, and so on, try to achieve the difference O of the 16th data and the 17th data₁₅, and subtract each other result O by try to achieve 16₀～O₁₅Input to 32 strange coefficient processing unit 12.

Described 16 butterfly processing elements 11, are made up of 8 adders and 8 subtractors, and these 8 adders are connected with 8 butterfly processing elements 13, and these 8 subtractors and 16 strange coefficient processing unit 14 are connected, as shown in Figure 4.

These 8 adders data E to being inputted by 32 butterfly processing elements 10₀～E₁₅Carry out head and the tail to sue for peace between two, namely try to achieve E₀With E₁₅Sum EE₀, then try to achieve E₁With E₁₄Sum EE₁, and so on, try to achieve E₇With E₈Sum EE₇, and 8 the addition result EE that will try to achieve₀～EE₇Input to 8 butterfly processing elements 13；

These 8 subtractors are to data E₀～E₁₅Carry out head and the tail and ask poor between two, namely try to achieve E₀With E₁₅Difference EO₀, then try to achieve E₁With E₁₄Difference EO₁, and so on, try to achieve E₇With E₈Difference EO₇, and subtract each other result EO by try to achieve 8₀～EO₇Input to 16 strange coefficient processing unit 14.

Described 8 butterfly processing elements 13, are made up of 4 adders and 4 subtractors, and these 4 adders and 4 butterfly processing elements 15, these 4 subtractors and 8 strange coefficient processing unit 16 are connected, as shown in Figure 4.

These 4 adders data EE to being inputted by 16 butterfly processing elements 11₀～EE₇Carry out head and the tail to sue for peace between two, namely try to achieve EE₀With EE₇Sum EEE₀, then try to achieve EE₁With EE₆Sum EEE₁, and so on, try to achieve and EE₃With EE₄Sum EEE₃, 4 addition result EEE will trying to achieve₀～EEE₃Input to 4 butterfly processing elements 15；

These 4 subtractors are to data EE₀～EE₇Carry out head and the tail and ask poor between two, namely try to achieve EE₀With EE₇Difference EEO₀, then try to achieve EE₁With EE₆Difference EEO₁, and so on, try to achieve also, and EE₃With EE₄Difference EEO₃Result EEO is subtracted each other by try to achieve 4₀～EEO₃Input to 8 strange coefficient processing unit 16.

Described 4 butterfly processing elements 15, are made up of 2 adders and 2 subtractors, and these 2 adders and 4 even coefficient processing unit 17, these 2 subtractors and 4 strange coefficient processing unit 18 are connected, as shown in Figure 4.

These 2 adder data EEE in the hope of being inputted by 8 butterfly processing elements 13₀With EEE₃Sum EEEE₀, and the data EEE of input₁With EEE₂Sum EEEE₁, and these 2 the addition result EEEE that will try to achieve₀、EEEE₁Input to 4 even coefficient processing unit 17；

These 2 subtractors data EEE in the hope of input₀With EEE₃Difference EEEO₀, and the data EEE of input₁With EEE₂Difference EEEO₁, and subtract each other result EEEO by try to achieve 2₀、EEEO₁Input to 4 strange coefficient processing unit 18.

With reference to Fig. 5, described 4 even coefficient processing unit 17, constituted by postponing subelement 170,2 butterfly computation subelements 171 and displacement subelement 172；

This delay subelement 170, to the data EEEE inputted by 4 butterfly processing elements 15₀With EEEE₁Carry out the delay of 2 clock cycle, obtain delayed data EEEE_{0_0}With EEEE_{1_0}, and these 2 data are sent into 2 butterfly computation subelements 171；

These 2 butterfly computation subelements 171, are made up of 1 adder and 1 subtractor, for the delayed data EEEE postponing subelement 170 input_{0_0}With EEEE_{1_0}Carry out respectively being added and subtracting each other, obtain summarized information EEEEE and subtract each other data EEEEO feeding displacement subelement 172；

This displacement subelement 172, is made up of 2 shift units, for data EEEEE and the EEEEO inputted by 2 butterfly computation subelements 171 is moved to left 6, and by 2 Fruiting coefficient tried to achieve output to transposition buffer module 2.

With reference to Fig. 6, described 4 strange coefficient processing unit 18, it is added subelement 181 is constituted by 14 dot factor operator unit 180 and 24 dot factors；

This 4 dot factor operator unit 180, is made up of depositor, shift unit and adder cascade, has been used for the data EEEO inputted by 4 butterfly processing elements 15₀、EEEO₁Postpone, obtain retardation coefficient EEEO_{0_0}、EEEO_{1_0}, and try to achieve EEEO respectively₀With EEEO₀, and EEEO₁With EEEO₁Self move to left the data sum after not coordination, it may be assumed that

Try to achieve EEEO₀With EEEO₀Self move to left the data sum after 1, obtain the first summation coefficient EEEO of 4_{0_1},

Try to achieve EEEO₁With EEEO₁Self move to left the data sum after 1, obtain the second summation coefficient EEEO of 4_{1_1},

Try to achieve EEEO₀With EEEO₀Self move to left the data sum after 2, obtain the 3rd summation coefficient EEEO of 4_{0_2},

Try to achieve EEEO₁With EEEO₁Self move to left the data sum after 2, obtain the 4th summation coefficient EEEO of 4_{1_2},

Again these retardation coefficients and summation coefficient are inputed to each 4 dot factors and be added subelement 181；

Each 4 dot factors are added subelement 181, are made up of shift unit, adder and subtractor cascade, for trying to achieve a Fruiting coefficient of dct transform, namely divide 3 grades of two retardation coefficient EEEO to 4 dot factor operator unit 180 inputs_{0_0}, EEEO_{1_0}, and four summation coefficient EEEO_{0_1}, EEEO_{0_2}, EEEO_{1_1}, EEEO_{1_2}Merge, wherein:

1st grade, be carry out respectively following three system numbers once merging simultaneously:

First group is by EEEO_{0_0}And EEEO_{1_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 4 the 1st grade merges coefficient COE_{4_101}；

Second group is by EEEO_{0_1}And EEEO_{1_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 4 the 1st grade merges coefficient COE_{4_102}；

3rd group is by EEEO_{0_2}And EEEO_{1_2}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 4 the 1st grade merges coefficient COE_{4_103}；

2nd grade is that three the merging coefficients simultaneously tried to achieve the 1st grade carry out secondary merging respectively:

By first merging coefficient COE of the 1st grade of 4_{4_101}With second merging coefficient COE of the 1st grade of 4_{4_102}After moving to left respectively, then carrying out being added or subtracting each other, first of obtain at 4 the 2nd grade merges coefficient COE_{4_201}；

By the 3rd the merging coefficient COE of the 1st grade of 4_{4_103}Moving to left, second of obtain at 4 the 2nd grade merges coefficient COE_{4_202}；

3rd level is that two the merging coefficients tried to achieve the 2nd grade merge, by first merging coefficient COE of the 2nd grade of 4_{4_201}With second merging coefficient COE of the 2nd grade of 4_{4_202}After moving to left respectively, then carry out being added or subtracting each other, obtain the Fruiting coefficient COEFF of 4₄, and by this Fruiting coefficient COEFF of 4₄Output is to transposition buffer module 2.

Described 8 strange coefficient processing unit 16, are added subelement 161 are constituted by 18 dot factor operator unit 160 and 48 dot factors；

This 8 dot factor operator unit 160, is made up of depositor, shift unit and adder cascade, for the data EEO to 8 butterfly processing element 13 inputs₀～EEO₃Postpone respectively, obtain retardation coefficient EEO_{0_0}～EEO_{3_0}, and try to achieve data EEO respectively₀～EEO₃With this data EEO₀～EEO₃Self move to left the data sum after not coordination, it may be assumed that

Try to achieve EEO₀With EEO₀Self move to left the data sum after 1, obtain the first summation coefficient EEO of 8_{0_1}；

Try to achieve EEO₁With EEO₁Self move to left the data sum after 1, obtain the second summation coefficient EEO of 8_{1_1}；

Try to achieve EEO₂With EEO₂Self move to left the data sum after 1, obtain the 3rd summation coefficient EEO of 8_{2_1}；

Try to achieve EEO₃With EEO₃Self move to left the data sum after 1, obtain the 4th summation coefficient EEO of 8_{3_1}；

Try to achieve EEO₀With EEO₀Self move to left the data sum after 2, obtain the 5th summation coefficient EEO of 8_{0_2}；

Try to achieve EEO₁With EEO₁Self move to left the data sum after 2, obtain the 6th summation coefficient EEO of 8_{1_2}；

Try to achieve EEO₂With EEO₂Self move to left the data sum after 2, obtain the 7th summation coefficient EEO of 8_{2_2}；

Try to achieve EEO₃With EEO₃Self move to left the data sum after 2, obtain the 8th summation coefficient EEO of 8_{3_2}；

Coefficient of suing for peace these eight is sent into and is added subelement 161 to each 8 dot factors；

Each 8 dot factors are added subelement 161, are made up of shift unit, adder and subtractor cascade, for trying to achieve a Fruiting coefficient of dct transform, namely divide 4 grades of coefficient EEO to being inputted by 8 dot factor operator unit 160_{0_0}～EEO_{3_0}、EEO_{0_1}～EEO_{3_1}And EEO_{0_2}～EEO_{3_2}Carry out shifter-adder or displacement is subtracted each other, wherein:

1st grade, be carry out respectively following six system numbers once merging simultaneously:

First group is by EEO_{0_0}And EEO_{1_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, first that obtains 8: 0 1st grades merges coefficient COE_{8_101}；

Second group is by EEO_{2_0}And EEO_{3_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, second that obtains 8: 0 1st grades merges coefficient COE_{8_102}；

3rd group is by EEO_{0_1}And EEO_{1_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd that obtains 8: 0 1st grades merges coefficient COE_{8_103}；

4th group is by EEO_{2_1}And EEO_{3_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 4th that obtains 8: 0 1st grades merges coefficient COE_{8_104}；

5th group is by EEO_{0_2}And EEO_{1_2}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 5th that obtains 8: 0 1st grades merges coefficient COE_{8_105}；

6th group is by EEO_{2_2}And EEO_{3_2}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 6th that obtains 8: 0 1st grades merges coefficient COE_{8_106}；

2nd grade, be simultaneously the 1st grade is tried to achieve three combination and coefficient carry out secondary merging respectively:

First group is by COE_{8_101}And COE_{8_102}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first that obtains 8: 0 2nd grades merges coefficient COE_{8_201}；

Second group is by COE_{8_103}And COE_{8_104}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second that obtains 8: 0 2nd grades merges coefficient COE_{8_202}；

3rd group is by COE_{8_105}And COE_{8_106}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd that obtains 8: 0 2nd grades merges coefficient COE_{8_203}；

3rd level is that three the merging coefficients simultaneously tried to achieve the 2nd grade carry out three merging respectively:

By first merging coefficient COE of 8: 0 2nd grades_{8_201}With second merging coefficient COE of 8: 0 2nd grades_{8_202}After moving to left respectively, then carrying out being added or subtracting each other, first that obtains 8 3rd levels merges coefficient COE_{8_301}；

By the 3rd the merging coefficient COE of 8: 0 2nd grades_{8_203}Moving to left, second that obtains 8 3rd levels merges coefficient COE_{8_302}；

4th grade is that two merging coefficients that 3rd level is tried to achieve merge, by first merging coefficient COE of 8 3rd levels_{8_301}Coefficient COE is merged with the second of 8 3rd levels_{8_302}After moving to left respectively, then carry out being added or subtracting each other, obtain the Fruiting coefficient COEFF of 8₈, and by this Fruiting coefficient COEFF of 8₈Output is to transposition buffer module 2, as shown in Figure 7.

Described 16 strange coefficient processing unit 14, are added subelement 141 are constituted by 1 16 dot factor operator unit 140 and 8 16 dot factors；

This 16 dot factor operator unit 140, is made up of depositor, shift unit and adder cascade, for the data EO to 16 butterfly processing element 11 inputs₀～EO₇Postpone respectively, obtain retardation coefficient EO_{0_0}～EO_{7_0}, and try to achieve retardation coefficient EO respectively₀～EO₇With EO₀～EO₇Self move to left the data sum after not coordination, it may be assumed that

Try to achieve data EO₀With EO₀Self move to left the data sum after 1, obtain the first summation coefficient EO of 16_{0_1}；

Try to achieve data EO₁With EO₁Self move to left the data sum after 1, obtain the second summation coefficient EO of 16_{1_1}；

And so on；

Try to achieve data EO₇With EO₇Self move to left the data sum after 1, obtain the 8th summation coefficient EO of 16_{7_1}；

Try to achieve data EO₀With EO₀Self move to left the data sum after 2, obtain the 9th summation coefficient EO of 16_{0_2}；

Try to achieve data EO₁With EO₁Self move to left the data sum after 2, obtain the tenth summation coefficient EO of 16_{1_2}；

And so on；

Try to achieve data EO₇With EO₇Self move to left the data sum after 2, obtain the 16th summation coefficient EO of 16_{7_2}；

Coefficient of suing for peace these 16 is sent into and is added subelement 141 to each 16 dot factors；

Described 16 dot factors are added subelement 141, are made up of shift unit, adder and subtractor cascade, for trying to achieve a Fruiting coefficient of dct transform, namely divide 5 grades of coefficient EO to being inputted by 16 dot factor operator unit 140_{0_0}～EO_{7_0}、EO_{0_1}～EO_{7_1}And EO_{0_2}～EO_{7_2}Carry out shifter-adder or displacement is subtracted each other, wherein:

1st grade, be carry out respectively following 12 system numbers once merging simultaneously:

First group is by EO_{0_0}And EO_{1_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 16 the 1st grade merges coefficient COE_{16_101}；

Second group is by EO_{2_0}And EO_{3_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 16 the 1st grade merges coefficient COE_{16_102}；

3rd group is by EO_{4_0}And EO_{5_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 16 the 1st grade merges coefficient COE_{16_103}；

4th group is by EO_{6_0}And EO_{7_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 4th of obtain at 16 the 1st grade merges coefficient COE_{16_104}；

5th group is by EO_{0_1}And EO_{1_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 5th of obtain at 16 the 1st grade merges coefficient COE_{16_105}；

6th group is by EO_{2_1}And EO_{3_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 6th of obtain at 16 the 1st grade merges coefficient COE_{16_106}；

And so on；

11st group is by EO_{4_2}And EO_{5_2}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 11st of obtain at 16 the 1st grade merges coefficient COE_{16_111}；

12nd group is by EO_{6_2}And EO_{7_2}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 12nd of obtain at 16 the 1st grade merges coefficient COE_{16_112}；

2nd grade, be that following six system numbers are carried out secondary merging respectively simultaneously:

First group is by COE_{16_101}And COE_{16_102}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 16 the 2nd grade merges coefficient COE_{16_201}；

Second group is by COE_{16_103}And COE_{16_104}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 16 the 2nd grade merges coefficient COE_{16_202}；

3rd group is by COE_{16_105}And COE_{16_106}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 16 the 2nd grade merges coefficient COE_{16_203}；

4th group is by COE_{16_107}And COE_{16_108}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 4th of obtain at 16 the 2nd grade merges coefficient COE_{16_204}；

5th group is by COE_{16_109}And COE_{16_110}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 5th of obtain at 16 the 2nd grade merges coefficient COE_{16_205}；

6th group is by COE_{16_111}And COE_{16_112}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 6th of obtain at 16 the 2nd grade merges coefficient COE_{16_206}；

3rd level, is following three combinations coefficient are carried out three times respectively merge simultaneously:

First group is by COE_{16_201}And COE_{16_202}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first of the 3rd level obtaining at 16 merges coefficient COE_{16_301}；

Second group is by COE_{16_203}And COE_{16_204}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second of the 3rd level obtaining at 16 merges coefficient COE_{16_302}；

3rd group is by COE_{16_205}And COE_{16_206}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of the 3rd level obtaining at 16 merges coefficient COE_{16_303}；

4th grade is that three the merging coefficients simultaneously 3rd level tried to achieve carry out four merging respectively:

Coefficient COE is merged by the first of the 3rd levels of 16_{16_301}Second of 3rd level with 16 merges coefficient COE_{16_302}After moving to left respectively, then carrying out being added or subtracting each other, first of obtain at 16 the 4th grade merges coefficient COE_{16_401}；

Coefficient COE is merged by the 3rd of the 3rd levels of 16 the_{16_303}Moving to left, second of obtain at 16 the 4th grade merges coefficient COE_{16_402}；

5th grade is that two the merging coefficients tried to achieve the 4th grade merge, by first merging coefficient COE of the 4th grade of 16_{16_401}With second merging coefficient COE of the 4th grade of 16_{16_402}After moving to left respectively, then carry out being added or subtracting each other, obtain the Fruiting coefficient COEFF of 16₁₆, and by this Fruiting coefficient COEFF of 16₁₆Output is to transposition buffer module 2, as shown in Figure 8.

Described 32 strange coefficient processing unit 12, are added subelement 121 are constituted by 1 32 dot factor operator unit 120 and 16 32 dot factors；

This 32 dot factor operator unit 120, is made up of depositor, shift unit and adder cascade, for the data O to 32 butterfly processing element 10 inputs₀～O₁₅Postpone respectively, obtain retardation coefficient O_{0_0}～O_{15_0}, and try to achieve input data O respectively₀～O₁₅With this O₀～O₁₅Self move to left the data sum after not coordination, it may be assumed that

Try to achieve O₀With O₀Self move to left the data sum after 1, obtain the first summation coefficient O of 32_{0_1}；

Try to achieve O₁With O₁Self move to left the data sum after 1, obtain the second summation coefficient O of 32_{1_1}；

And so on；

Try to achieve O₁₅With O₁₅Self move to left the data sum after 1, obtain the 16th summation coefficient O of 32_{15_1}；

Try to achieve O₀With O₀Self move to left the data sum after 2, obtain the 17th summation coefficient O of 32_{0_2}；

Try to achieve O₁With O₁Self move to left the data sum after 2, obtain the 18th summation coefficient O of 32_{1_2}；

And so on；

Try to achieve O₁₅With O₁₅Self move to left the data sum after 2, obtain the 32nd summation coefficient O of 32_{15_2}；

Try to achieve O₀With O₀Self move to left the data sum after 3, obtain the 33rd summation coefficient O of 32_{0_3}；

Try to achieve O₁With O₁Self move to left the data sum after 3, obtain the 34th summation coefficient O of 32_{1_3}；

And so on；

Try to achieve O₁₅With O₁₅Self move to left the data sum after 3, obtain the 48th summation coefficient O of 32_{15_3}；

Coefficient of suing for peace these 48 is sent into and is added subelement 121 to each 32 dot factors；

Each 32 dot factors are added subelement 121, and for trying to achieve a Fruiting coefficient of dct transform, this subelement is made up of shift unit, adder and subtractor cascade, point 6 grades of coefficient O to being inputted by 32 dot factor operator unit 120_{0_0}～O_{15_0}、O_{0_1}～O_{15_1}、O_{0_2}～O_{15_2}And O_{0_3}～O_{15_3}Carry out shifter-adder or displacement subtracted each other,

Wherein:

1st grade, be carry out respectively following 32 system numbers once merging simultaneously:

First group is by O_{0_0}And O_{1_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 32 the 1st grade merges coefficient COE_{32_101}；

Second group is by O_{2_0}And O_{3_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 32 the 1st grade merges coefficient COE_{32_102}；

3rd group is by O_{4_0}And O_{5_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 32 the 1st grade merges coefficient COE_{32_103}；

And so on；

8th group is by O_{14_0}And O_{15_0}After the two retardation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 8th of obtain at 32 the 1st grade merges coefficient COE_{32_108}；

9th group is by O_{0_1}And O_{1_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 9th of obtain at 32 the 1st grade merges coefficient COE_{32_109}；

Tenth group is by O_{2_1}And O_{3_1}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the tenth of obtain at 32 the 1st grade merges coefficient COE_{32_110}；

And so on；

31st group is by O_{12_3}And O_{13_3}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 31st of obtain at 32 the 1st grade merges coefficient COE_{32_131}；

32nd group is by O_{14_3}And O_{15_3}After the two summation coefficient moves to left respectively, then carrying out being added or subtracting each other, the 32nd of obtain at 32 the 1st grade merges coefficient COE_{32_132}；

2nd grade, be that following 16 system numbers are carried out secondary merging respectively simultaneously:

First group is by COE_{32_101}And COE_{32_102}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 32 the 2nd grade merges coefficient COE_{32_201}；

Second group is by COE_{32_103}And COE_{32_104}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 32 the 2nd grade merges coefficient COE_{32_202}；

3rd group is by COE_{32_105}And COE_{32_106}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 32 the 2nd grade merges coefficient COE_{32_203}；

4th group is by COE_{32_107}And COE_{32_108}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 4th of obtain at 32 the 2nd grade merges coefficient COE_{32_204}；

5th group is by COE_{32_109}And COE_{32_110}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 5th of obtain at 32 the 2nd grade merges coefficient COE_{32_205}；

6th group is by COE_{32_110}And COE_{32_111}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 6th of obtain at 32 the 2nd grade merges coefficient COE_{32_206}；

And so on；

15th group is by COE_{32_128}And COE_{32_129}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 15th of obtain at 32 the 2nd grade merges coefficient COE_{32_215}；

16th group is by COE_{32_130}And COE_{32_131}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 16th of obtain at 32 the 2nd grade merges coefficient COE_{32_216}；

3rd level, is following eight system numbers carry out three times respectively merge simultaneously:

First group is by COE_{32_201}And COE_{32_202}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first of the 3rd level obtaining at 32 merges coefficient COE_{32_301}；

Second group is by COE_{32_203}And COE_{32_204}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second of the 3rd level obtaining at 32 merges coefficient COE_{32_302}；

3rd group is by COE_{32_205}And COE_{32_206}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of the 3rd level obtaining at 32 merges coefficient COE_{32_303}；

And so on；

7th group is by COE_{32_213}And COE_{32_214}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 7th of the 3rd level obtaining at 32 merges coefficient COE_{32_307}；

8th group is by COE_{32_215}And COE_{32_216}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 8th of the 3rd level obtaining at 32 merges coefficient COE_{32_308}；

4th grade, be following four combinations coefficient are carried out four times respectively merge simultaneously:

First group is by COE_{32_301}And COE_{32_302}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, first of obtain at 32 the 4th grade merges coefficient COE_{32_401}；

Second group is by COE_{32_303}And COE_{32_304}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, second of obtain at 32 the 4th grade merges coefficient COE_{32_402}；

3rd group is by COE_{32_305}And COE_{32_306}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 3rd of obtain at 32 the 4th grade merges coefficient COE_{32_403}；

4th group is by COE_{32_307}And COE_{32_308}After the two merging coefficient moves to left respectively, then carrying out being added or subtracting each other, the 4th of obtain at 32 the 4th grade merges coefficient COE_{32_404}；

5th grade is that four the merging coefficients simultaneously tried to achieve the 4th grade carry out five merging respectively:

By first merging coefficient COE of the 4th grade of 32_{32_401}With second merging coefficient COE of the 4th grade of 32_{32_402}After moving to left respectively, then carrying out being added or subtracting each other, first of obtain at 32 the 5th grade merges coefficient COE_{32_501}；

By the 3rd the merging coefficient COE of the 4th grade of 32_{32_403}With the 4th the merging coefficient COE of the 4th grade of 32_{32_404}After moving to left respectively, then carrying out being added or subtracting each other, second of obtain at 32 the 5th grade merges coefficient COE_{32_502}；

6th grade is that two the merging coefficients tried to achieve the 5th grade merge, by first merging coefficient COE of the 5th grade of 32_{32_501}With second merging coefficient COE of the 5th grade of 32_{32_502}After moving to left respectively, then carry out being added or subtracting each other, obtain the Fruiting coefficient COEFF of 32₃₂, and by this Fruiting coefficient COEFF of 32₃₂Output is to transposition buffer module 2, as shown in Figure 9.

It is added subelement 181,8 dot factor at above-mentioned each 4 dot factors and is added in the every one-level merging in subelement 161,16 dot factor addition subelement 141 and 32 dot factor addition subelement 121, choosing of shift count and adder or subtractor, is determine according to actual demand and experiment.

Claims

1. the transform coder being suitable to high-performance video coding standard HEVC, including: one-dimensional DCT module (1), transposition buffer module (2) and top layer control module (3), the data output end of this one-dimensional DCT module (1) is connected with the data input pin of transposition buffer module (2), and data input pin is connected with the data output end of transposition buffer module (2)；This top layer controls module (3) and is connected with the reset terminal of one-dimensional DCT module (1), Enable Pin and the reset terminal of transposition buffer module (2), Enable Pin respectively, it is characterised in that:

Described one-dimensional DCT module (1), including:

32 butterfly processing elements (10), it is made up of 16 adders and 16 subtractors, it is respectively utilized to complete the operation that the coefficient to be transformed to input is added between two and subtracts each other between two, and will add up 16 data obtaining of operation and input to 16 butterfly processing elements (11), 16 data phase reducing obtained input to 32 strange coefficient processing unit (12)；

16 butterfly processing elements (11), it is made up of 8 adders and 8 subtractors, it is respectively utilized to complete the operation that 16 data that 32 butterfly processing elements (10) are inputted are added between two and subtract each other between two, and will add up 8 data obtained and input to 8 butterfly processing elements (13), input to 16 strange coefficient processing unit (14) by subtracting each other 8 data obtained；

32 strange coefficient processing unit (12), it is added subelement (121) cascade is constituted by 1 32 dot factor operator unit (120) and 16 32 dot factors, for obtain 16 data being inputted by 32 butterfly processing elements (10) and these 16 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 16 groups different, be added, subtract each other, try to achieve 16 transform datas, then input to transposition buffer module (2)；

8 butterfly processing elements (13), it is made up of 4 adders and 4 subtractors, it is respectively utilized to complete the operation that 8 data that 16 butterfly processing elements (11) are inputted are added between two and subtract each other between two, and will add up 4 data obtained and input to 4 butterfly processing elements (15), input to 8 strange coefficient processing unit (16) by subtracting each other 4 data obtained；

16 strange coefficient processing unit (14), it is added subelement (141) cascade is constituted by 1 16 dot factor operator unit (140) and 8 16 dot factors, for obtain 8 data being inputted by 16 butterfly processing elements (11) and these 8 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 8 groups different, be added, subtract each other, try to achieve 8 transform datas, and input to transposition buffer module (2)；

4 butterfly processing elements (15), it is made up of 2 adders and 2 subtractors, it is respectively utilized to complete 4 data that 8 butterfly processing elements (13) are inputted be added between two and subtract each other between two, and will add up 2 data obtained and input to 4 even coefficient processing unit (17), input to 4 strange coefficient processing unit (18) by subtracting each other 2 data obtained；

8 strange coefficient processing unit (16), it is added subelement (161) cascade is constituted by 18 dot factor operator unit (160) and 48 dot factors, for obtain 4 data being inputted by 8 butterfly processing elements (13) and these 4 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 4 groups different, be added, subtract each other, try to achieve 4 transform datas and input to transposition buffer module (2)；

4 even coefficient processing unit (17), constituted by postponing subelement (170), 2 butterfly computation subelements (171) and displacement subelement (172) cascade, 2 data for completing 4 butterfly processing elements (15) are inputted postpone, and shifter-adder, the operation subtracted each other, try to achieve 2 transform datas and input to transposition buffer module (2)；

4 strange coefficient processing unit (18), it is added subelement (181) is constituted by 14 dot factor operator unit (180) and 24 dot factors, for obtain 2 data being inputted by 4 butterfly processing elements (15) and these 2 data self move to left rear coefficient and, and carry out summed result respectively shifting by shift count 2 groups different, be added, subtract each other, try to achieve 2 transform datas and input to transposition buffer module (2)；

Reset and enable control unit (19), control module (3) with top layer to be connected, control module (3) reset that exports for receiving top layer and enable signal, and controlling reset and the enable of unit in one-dimensional DCT module (1) according to resetting and enabling signal.

2. transform coder according to claim 1, it is characterised in that: input data are carried out head and the tail and sue for peace between two by 16 adders in 32 butterfly processing elements (10), and 16 the addition result E that will try to achieve₀～E₁₅Input to 16 butterfly processing elements (11)；Input coefficient is carried out head and the tail and asks poor between two by 16 subtractors, and subtracts each other result O by try to achieve 16₀～O₁₅Input to 32 strange coefficient processing unit (12).

3. transform coder according to claim 1, it is characterised in that: the data E to being inputted by 32 butterfly processing elements (10) of 8 adders in 16 butterfly processing elements (11)₀～E₁₅Carry out head and the tail to sue for peace between two, and 8 the addition result EE that will try to achieve₀～EE₇Input to 8 butterfly processing elements (13)；8 subtractors are to data E₀～E₁₅Carry out head and the tail and ask poor between two, and subtract each other result EO by try to achieve 8₀～EO₇Input to 16 strange coefficient processing unit (14).

4. transform coder according to claim 1, it is characterized in that: 32 dot factors operator unit (120) described in 32 strange coefficient processing unit (12) are made up of depositor, shift unit and adder cascade, have been used for the data O inputted by 32 butterfly processing elements (10)₀～O₁₅Carry out delay and obtain retardation coefficient O_{0_0}～O_{15_0}, and try to achieve O₀～O₁₅With O₀～O₁₅Self move to left 1,2,3 and O_{0_1}～O_{15_1}、O_{0_2}～O_{15_2}、O_{0_3}～O_{15_3}, these coefficients are sent into and are added subelement (121) to each 32 dot factors；32 described dot factors are added subelement (121), are made up of shift unit, adder and subtractor cascade, have been used for the coefficient O inputted by 32 dot factors operator unit (120)_{0_0}～O_{15_0}、O_{0_1}～O_{15_1}、O_{0_2}～O_{15_2}And O_{0_3}～O_{15_3}Carry out shifter-adder or displacement is subtracted each other, finally try to achieve 1 data and output it to transposition buffer module (2).

5. transform coder according to claim 1, it is characterised in that: the data EE to being inputted by 16 butterfly processing elements (11) of 4 adders in 8 butterfly processing elements (13)₀～EE₇Carry out head and the tail to sue for peace between two, and 4 the addition result EEE that will try to achieve₀～EEE₃Inputing to 4 butterfly processing elements (15), 4 subtractors are to data EE₀～EE₇Carry out head and the tail and ask poor between two, and subtract each other result EEO by try to achieve 4₀～EEO₃Input to 8 strange coefficient processing unit (16).

6. transform coder according to claim 1, it is characterized in that: 16 dot factors operator unit (140) described in 16 strange coefficient processing unit (14), it is made up of depositor, shift unit and adder cascade, has been used for the data EO inputted by 16 butterfly processing elements (11)₀～EO₇Postpone, obtain retardation coefficient EO_{0_0}～EO_{7_0}, and try to achieve EO₀～EO₇Respectively with EO₀～EO₇Self move to left 1 sum coefficient EO_{0_1}～EO_{7_1}And EO₀～EO₇Self move to left 2 sum coefficient EO_{0_2}～EO_{7_2}, these coefficients are sent into and are added subelement (141) to each 16 dot factors；16 described dot factors are added subelement (141), are made up of shift unit, adder and subtractor cascade, have been used for the coefficient EO inputted by 16 dot factors operator unit (140)_{0_0}～EO_{7_0}、EO_{0_1}～EO_{7_1}And EO_{0_2}～EO_{7_2}Carry out shifter-adder or displacement is subtracted each other, finally try to achieve 1 data and export to transposition buffer module (2).

7. transform coder according to claim 1, it is characterised in that: 2 adders data EEE in the hope of being inputted by 8 butterfly processing elements (13) in 4 butterfly processing elements (15)₀With EEE₃Sum EEEE₀, and the data EEE of input₁With EEE₂Sum EEEE₁, and these 2 the addition result EEEE that will try to achieve₀、EEEE₁Input to 4 even coefficient processing unit (17)；2 subtractor data EEE in the hope of input₀With EEE₃Difference EEEO₀, and the data EEE of input₁With EEE₂Difference EEEO₁, and 2 will be tried to achieve subtract each other result EEEO₀、EEEO₁Input to 4 strange coefficient processing unit (18).

8. transform coder according to claim 1, it is characterized in that: 8 dot factors operator unit (160) described in 8 strange coefficient processing unit (16), it is made up of depositor, shift unit and adder cascade, has been used for the data EEO inputted by 8 butterfly processing elements (13)₀～EEO₃Postpone, obtain retardation coefficient EEO_{0_0}～EEO_{3_0}, and try to achieve EEO₀～EEO₃Respectively with EEO₀～EEO₃Self move to left 1 sum coefficient EEO_{0_1}～EEO_{3_1}And EEO₀～EEO₃Self move to left 2 sum coefficient EEO_{0_2}～EEO_{3_2}, these coefficients are sent into and are added subelement (161) to each 8 dot factors；8 described dot factors are added subelement (161), are made up of shift unit, adder and subtractor cascade, have been used for the coefficient EEO inputted by 8 dot factors operator unit (160)_{0_0}～EEO_{3_0}、EEO_{0_1}～EEO_{3_1}And EEO_{0_2}～EEO_{3_2}Carry out shifter-adder or displacement is subtracted each other, finally try to achieve 1 data and export to transposition buffer module (2).

9. transform coder according to claim 1, it is characterised in that: the delay subelement (170) described in 4 even coefficient processing unit (17), to the data EEEE inputted by 4 butterfly processing elements (15)₀With EEEE₁Carry out the delay of 2 clock cycle, obtain delayed data EEEE_{0_0}With EEEE_{1_0}, and these 2 data are sent into 2 butterfly computation subelements (171)；2 described butterfly computation subelements (171), are made up of 1 adder and 1 subtractor, for postponing the delayed data EEEE that subelement (170) inputs_{0_0}With EEEE_{1_0}Carry out respectively being added and subtracting each other, obtain summarized information EEEEE and subtract each other data EEEEO feeding displacement subelement (172)；Described displacement subelement (172), it is made up of 2 shift units, for data EEEEE and the EEEEO inputted by 2 butterfly computation subelements (171) is moved to left, and 2 data will be tried to achieve export to transposition buffer module (2).

10. transform coder according to claim 1, it is characterised in that: 4 strange coefficient processing unit

(18) 4 dot factors operator unit (180) described in, are made up of depositor, shift unit and adder cascade, have been used for the data EEEO inputted by 4 butterfly processing elements (15)₀、EEEO₁Postpone, obtain retardation coefficient EEEO_{0_0}、EEEO_{1_0}, and try to achieve EEEO respectively₀With EEEO₀, and EEEO₁With EEEO₁Self move to left the data sum after not coordination, it may be assumed that

Try to achieve EEEO₀With EEEO₀Self move to left the data sum EEEO after 1_{0_1},

Try to achieve EEEO₁With EEEO₁Self move to left the data sum EEEO after 1_{1_1},

Try to achieve EEEO₀With EEEO₀Self move to left the data sum EEEO after 2_{0_2},

Try to achieve EEEO₁With EEEO₁Self move to left the data sum EEEO after 2_{1_2},

These coefficients are inputed to each 4 dot factors and is added subelement (181)；

4 described dot factors are added subelement (181), are made up of shift unit, adder and subtractor cascade, for the coefficient EEEO that 4 dot factors operator unit (180) are inputted_{0_0}、EEEO_{1_0}、EEEO_{0_1}、EEEO_{1_1}、EEEO_{0_2}And EEEO_{1_2}Carry out shifter-adder or displacement is subtracted each other, finally try to achieve 1 data and export to transposition buffer module (2).