CN109461125A - Point 2-d gaussian filters device and image processing method based on FPGA - Google Patents
Point 2-d gaussian filters device and image processing method based on FPGA Download PDFInfo
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Abstract
The present invention discloses a kind of point 2-d gaussian filters device based on FPGA, including the image data input module for acquiring image pattern, convenient for the clock input module of FPGA internal clocking frequency dividing control；And built by FPGA platform: determining the clock division control module of inter-process timing, ROM module for data storage, for traversing sample and determine 3 × 3 square box generation modules of filter mask size, and to the 2-d gaussian filters module that is handled of storage image information；It further include that treated discrete two-dimensional image is subjected to the data outputting module that terminal is shown.Such technical solution carries out 2-d gaussian filters based on FPGA, by the picture signal of input.Image processing algorithm is realized in FPGA hardware platform, while guaranteeing the real-time of image processing algorithm, and the customization function that the IP kernel of FPGA can be made full use of to have, meet more specific requirements.Invention additionally discloses a kind of point 2-d gaussian filters device image processing method based on FPGA.
Description
Technical field
The invention belongs to technical field of image processing, are related to a kind of point 2-d gaussian filters device image procossing based on FPGA
Method, specifically, it is related to a kind of processing of point two-dimensional convolution more particularly to dimensional Gaussian operation that image is realized using FPGA,
Realize the elimination of picture noise.
Background technique
With being constantly progressive for information digitalization processing technique development, image is more and more extensive as the medium that information is transmitted
Ground is applied in the every field of study, work, scientific research and life.Realize that Digital Image Processing is exactly two schemes nothing but, one
Kind is to be handled with software, such as realized with MATLAB, another is with hardware handles, such as specific integrated circuit, FPGA etc..
Most of uncomplicated image procossing software realizations, because software processing is easy to analogue simulation.
Since image processing techniques constantly develops, the requirement of people's digital image processing technology is also higher and higher.Through
Coordinate indexing investigation, the related system for carrying out image procossing is very big for the demand of data processing amount, and requires cracking processing
Speed, when we handle some real-time pictures or big picture, traditional images noise-removed technology be based in PC machine, although
Denoising effect is good, carries out the rate request that needs may be not achieved in processing using software, because the speed of software processing is slower, so
And current most of algorithms for image procossing can only utilize software go operation, but cost needed for software environment is too at this time
Height, and be on a grand scale, while many algorithms can not be realized really, the analogue simulation stage is only resided within, at this moment selection makes
It is very suitable for reaching the requirement of processing speed with hardware handles image, so being badly in need of that a kind of cost is lower and image procossing
Speed is fast and can guarantee the image processing method based on hardware platform that good picture noise filters out.
Summary of the invention
The purpose of the present invention is to provide a kind of point 2-d gaussian filters device and image processing method based on FPGA,
Based on FPGA, the picture signal of input is subjected to 2-d gaussian filters.By image processing algorithm in FPGA hardware platform reality
It is existing, while guaranteeing the real-time of image processing algorithm, and the customization function that the IP kernel of FPGA can be made full use of to have,
Meet more specific requirements.
In order to achieve the above objectives, solution of the invention is:
A kind of point 2-d gaussian filters device based on FPGA inputs mould including the image data for acquiring image pattern
Block, convenient for the clock input module of FPGA internal clocking frequency dividing control；And whole image processing system is built by FPGA platform
Each internal processing modules: the clock division control module of decision systems inter-process timing, for data storage ROM mould
Block is carried out for traversing 3 × 3 square box generation modules of sample and determining filter mask size, and to storage image information
The 2-d gaussian filters module of processing；It further include that treated discrete two-dimensional image is carried out to the data that terminal is shown to export mould
Block.
A kind of point 2-d gaussian filters device image processing method based on FPGA, includes the following steps:
Step 1, the image pattern information that need to be handled is read in by image data input module, and simultaneously when outside is mirrored
Clock input module, this module is primarily to guarantee that subsequent module of managing everywhere in FPGA is built orderly can work；
Step 2, the clock input module based on step 1, builds clock division control module inside FPGA, module master
If 3 × 3 square box generation modules, 2-d gaussian filters module can be according to corresponding timing by the ROM module inside FPGA
It works, to avoid resource occupation conflict；
It step 3,, will herein first by calling ROM module via step 2 clock division control module inside FPGA
It is stored in step 1 by image data input module acquired image sample；
Step 4, the image pattern that subsequent invocation step 3 stores, then clock signal is issued by clock division control module, lead to
Cross 3 × 3 square box generation modules and generate mask on sample, herein mask primarily to subsequent progress 2-d gaussian filters into
Row prepares, so as to the image pixel point in frame is replaced processing, to realize that image procossing needs the defeated of pixel
Out；
Step 5,2-d gaussian filters module is brought into the mask formed by 3 × 3 square box generation modules, then
The filter module will smoothly traverse sample image with 3 × 3 square boxes, and the mask all pixels successively taken out are filtered place
Reason, exports filtered data；
Step 6, finally by information filtered in above-mentioned steps, serial communication is carried out by data outputting module, and most
Treated at last, and image is shown in computer terminal.
After adopting the above scheme, compared with prior art, the present invention having following technical effect that
(1) image procossing that other function is realized based on FPGA does not need then to redesign square box generation module and row
Column count module can directly use previous module, it is only necessary to after modification because reusable when its module design
Algoritic module be used in conjunction with the two modules, design the sequential relationship of work, so that it may realize other function
Image procossing；
(2) in terms of the timeliness of method, because an of the invention information content needed of setting about is few, the complexity of implementation
It is low, to reduce the processing time of method；
(3) image detecting method based on FPGA is with a wide range of applications, and different IP can be customized by specific requirements
Core, and design result is reusable；
(4) based on the concurrency of FPGA, algorithm can be made to carry out realization of High Speed, complicated treatment process may be implemented；
(5) FPGA has powerful expansion, and FGPA is designed based on hardware language, has outstanding portable
Property；
(6) combination of FPGA and image processing techniques improves the practicality of system design, and not with FPGA performance
Disconnected to improve, processing speed is getting faster, and the functional module being internally integrated is more and more, and the performance of detection method can be increasingly
It is good.
Detailed description of the invention
Fig. 1 is flow diagram of the invention；
Fig. 2 is gaussian filtering template；
Fig. 3 is filter general hardware module frame chart；
Fig. 4 is 3 × 3 square box structure block diagrams；
Fig. 5 is square box hardware pipeline figure；
Fig. 6 is 3 × 3 square box modular simulation waveform diagrams；
Fig. 7 is line count device；
Fig. 8 is line count device simulation waveform；
Fig. 9 is Gaussian filter operation FPGA algorithm circuit；
Figure 10 is adder Module figure；
Figure 11 is shift register module figure；
Figure 12 is tree-shaped shifter-adder multiplier flow chart；
Figure 13 is mean filter schematic diagram three times；
Figure 14 is the simulation waveform of mean filter；
Figure 15 is image processing effect comparison diagram.
Specific embodiment
Below with reference to attached drawing, technical solution of the present invention and beneficial effect are described in detail.
The present invention provides a kind of point 2-d gaussian filters device image processing method based on FPGA comprising the steps of:
Step A): FPGA processor is for constructing internal discrete dimensional Gaussian image filtering module, data memory module, when
Clock frequency division module, and acquire image data provided by image data input module；
Step B): timing control is carried out by introducing external input clock, by designing suitable timing, to generated
Image pixel data is stored in ROM module；
Step C): the image pixel information for being stored in ROM module is called reading, and data are passed to FPGA
In, and call 3 × 3 square box generation modules of traversal sample；
Step D): it is filtered in 2-d gaussian filters module, exports filtered data, on computers finally
Image information after showing filtering noise reduction.
As optimization method of the invention, flow diagram using FPGA piece inner multiplication device, inside as shown in Figure 1, mainly deposited
The resources such as reservoir and logic unit realize to include handling structure based on FPGA under the control of the synchronization signals such as row, the field of vision signal
The discrete two-dimensional gaussian filtering module made acquires the image data input module of image pattern, the ROM mould that image pattern saves
Block, the clock division control module of internal system timing control use, 3 × 3 square box generation modules for traversing sample, show
Show the data outputting module of image after handling.
Gaussian filtering is substantially exactly a kind of application of convolutional filtering, i.e., changes the convolution mask coefficient in convolution algorithm into
The dimensional Gaussian template formed with Gaussian function；Its algorithm is similar with convolution algorithm, all to realize a kind of neighborhood operation, i.e., some
The gray value of pixel is not only related with the gray value of this pixel, at the same with other all pictures in the pixel adjacent area
The gray value of vegetarian refreshments is related；By will smoothly traverse all pixels in the window that 3 × 3 windows take out, with the dimensional Gaussian set
Template carries out convolution algorithm, and operation eligible result is by the gray value as the pixel.
The image for wanting noise reduction is read in by MATLAB using image data input module, is mentioned later by FPGA is ready-made
Memory ROM module in the module of confession stores image data.
Using clock division control module for carrying out frequency dividing setting to externally input clock, so as to obtain FPGA
Clock required for AD control conversion module and 2-d gaussian filters module in system.
3 × 3 square box generation modules of traversal sample are called to realize that image procossing needs the output of pixel, side here
Shape frame generation module is exactly the square box of size required for generating, and exports required pixel to carry out necessary fortune
It calculates.
Data outputting module is used for after data carry out calculation process by 2-d gaussian filters module, utilizes FPGA and computer
Between serial communication, filtered image data is sent to computer and is shown.
Wherein, in the dimensional Gaussian convolution algorithm mapped based on FPGA platform, as dimensional Gaussian image filter is set
Meter is the central part of entire 2-d gaussian filters module, and 2-d gaussian filters are the basic applications of one kind of convolution algorithm,
Filtering essence is exactly pixel and Gaussian template progress convolution algorithm in image output sliding window, and this filtering can be in image procossing
In can eliminate Gaussian noise, to have the function of noise abatement, have a very wide range of applications field in image procossing.According to
The distribution character of Gaussian function, template are exactly to realize the process that the pixel of whole image is weighted.It is two-dimentional high
Process of this filtering is in fact very simple, is exactly each pixel of the first scan image with sliding window line by line, then
The weighted average of the gray value of all pixels point replaces the gray value of central pixel point in sliding window, then according to new pixel
Point gray value exports the new image of a width in order.Its is defined as:
2-d gaussian filters algorithm:
Wherein, f (x, y) is input picture, and g (x, y) is the output image after gaussian filtering.
When carrying out image procossing using 2-d gaussian filters, in order to can be convenient realize hardware design, it is general we
Algorithm can be simplified, output window central pixel point and its field pixel can be rolled up as convolution module
Product module plate operation.Because two-dimensional Gaussian function is a kind of normal distyribution function, the coefficient of Filtering Template is also about center
Point symmetry, the coefficient from central point same distance is all identical.
Fig. 2 is common dimensional Gaussian template, can be found out from dimensional Gaussian template, the coefficient for being in template center is wanted
It is far longer than the coefficient of other points, and distance center point is remoter, coefficient is with regard to smaller and smaller.The size of output window should and template
Therefore matching is in the importance highest of the pixel of output window center, and distance center point is compared compared with the pixel value of distant positions
Under importance with regard to lower.
For the present invention using the 2-d gaussian filters algorithm quickly approached, being mainly based upon 2-d gaussian filters device is one
Low-pass filter has any position i:
A is constant in formula.Since there are exponential functions, complexity is calculated, generally all replaces g with approximate templatea
(i), if mean value template is selected, for n digital signal f (n)={ a1,a2,…,an, by taking window width N=5 as an example, then
Expression formula is after mean filterIt is available by mean algorithm, any position bi(1≤i≤n)
Value be ai-2To ai+2Continuous 5 several mean values, it may be assumed that
bi=aiI=1,2, n-1, n (4)
If the signal after secondary filtering
WhereinWork as i=1, when 2, n-1, n, ci=bi, similarly hereinafter, expansion obtains:
Similarly, pass through filtered signal three times:
Wherein:
Several formulas show any position d after multiple mean filter aboveiValue depend on i front and back data weighting put down
Mean value, and weight data distribution has Gaussian characteristics, that is, meets the distribution character of above-mentioned formula.In conclusion using equal three times
Value filter may be implemented to approach Gaussian filter completely.
And for single mean filter:
Then have:
Above formula both sides are available multiplied by N simultaneously:
Nbi+1=Nbi+ai+1+N/2-ai-N/2 (12)
Wherein N is window width.As can be seen that mean filter is exactly to pass through a sub-addition, a subtraction one more
Division composition.Mean operation is exactly first to add up to data in window, is then added up and divided by N, if the size of window is N=
2k, then division arithmetic can move to right k with shift register to realize.
Realize that the image size that the present invention is handled is the grayscale image for 128 × 128 to be mapped in FPGA platform
Picture, the gray value of each pixel are that 0-255,0 value represents white, and 255 values represent black, 0-255 be exactly it is white to black gradually
The process of change, therefore 8 bits of use represent the gray value of each pixel.As shown in figure 3, D (7:0) is gray level image
8 bits of pixel value improve input data to square box generation module；DOUT (7:0) is the ash of output pixel point
Angle value, that is, the result that 8 data inputted obtain after algoritic module calculates；DV is whether detection output signal is effectively marked
Will, when DV be high level when, show that output signal value is effective, when DV be low level when, show to handle it is wrong, output signal without
Effect, will not be used.
Wherein, it is contemplated that the hardware design of usually most of image processing filter mainly by square box generation module,
Algoritic module and line count device module composition, each module provide different functions for image processing system, they are to make
Realize that image filtering handles essential important component with FPGA, the present invention will first build 3 × 3 square boxes and generate mould
Block wishes the gray scale of 9 pixels in 3 × 3 square boxes in order to which algoritic module is more easily handled output data herein
Value can be exported in the same time, therefore the present embodiment designs 3 × 3 square boxes using two FIFO memories.It is specifically walked
It is rapid as follows:
Step A: the gray scale picture pixel value that the present invention is handled is 128 × 128, therefore sets the address width of FIFO as 128,
FIFO each in this way can store the gray value of a line totally 128 pixels；
Step B: then, therefrom export w11-w33 totally 9 image pixel point datas as 3 × 3 square box generation modules
Data, Fig. 4 are the structural block diagram of 3 × 3 square boxes；
As shown in figure 5, can clearly obtain, data can be through for the hardware pipeline figure of the square box generation module of step C:3 × 3
Cross register R1-R7 and two FIFO memories；
Step D: when each clock arrive when, can export simultaneously w11, w12, w13, w21, w22, w23, w31, w32,
W33 totally 9 image pixel gray level Value Datas, constitute 3 × 3 square box, the data as the processing operation of following algoritic module
Input, Fig. 6 are modular simulation waveform diagram.
The heretofore described main counting locator of line count device module passes through the row and column to processing pixel
Counting the generation of sliding window cross-border phenomenon can be prevented, whenever rectangular to orient the position of the pixel of processing
When frame slides to the right a position, column counter adds one, until all pixels point data of a line all has been processed, then automatically
Line feed, column counter add one, as shown in fig. 7, the definition of its pin is as shown in table 1.In order to make after processing the image size that exports and
The picture size size inputted before processing is consistent, but 3 × 3 simple square boxes can not handle outermost one week
Image pixel point data, also one week pixel of image outermost is handled, therefore there is no pass through to image by the design
The gray value of one week pixel of image outermost, is only both configured to 0 by normal marginalisation processing.Line count device can basis
The one week position of outermost whether the accurate judgement pixel is located at image is come in the position of processing pixel now, if it is image
Outermost one week pixel position, then export 0, is otherwise directly handled according to the algorithm operation of setting.Fig. 8 is ranks meter
8 digits are employed herein for convenience to replace 128 of image in the simulation waveform of number device.
Table 1
| Clk | Clock input |
| En | Enable signal |
| RSTn | Reset signal |
| ColPos | The column mark of currently processed image |
| RowPos | The line flag of pre-treatment image |
The 2-d gaussian filters module main task uses 3 × 3 rectangular frame templates, carries out to each pixel in image
As soon as time Gaussian filter operation is comparable to two 3 × 3 ordered series of numbers and carries out convolution algorithm, operation is 9 multiplyings, 8 times
There are also the combinations of 1 division arithmetic for add operation.In Gaussian filter operation, mainly transported by add operation, multiplying and division
Composition is calculated, therefore hardware design needs the computing circuits such as adder, multiplier and divider module to realize algorithm process.Such as figure
Shown in 9, by w11, w12, w13, w21, w22, w23, w31, w32, w33 totally 9 image pixel gray level value numbers of square box output
According to first totally 9 coefficients are multiplied respectively with K1, K2, K3, K4, K5, K6, K7, K8, K9 of Gaussian template, with accumulator and deposit
Device is summed, and is finally realized division arithmetic with shift register, is obtained final output valve, here it is the gaussian filterings of FPGA
Operational flowchart, each symbol definition are as shown in table 2.
Table 2
| A | Adder | Add operation |
| M | Multiplier | Multiplying |
| R | Register | Caching effect, assists addition |
| Shift register | Shift register | Division arithmetic |
The adder Module, as shown in Figure 10, wherein dataA, dataB are the input of two addends A, B of adder,
Clock is clock signal, and result is the output of A+B, because the gray level of the gray level image handled herein is 0-255,
Input and output use 8.
Shift register module figure as shown in figure 11, wherein clk is clock signal, and din is input signal, and dout is defeated
Signal out, the figure realize the function that input signal moves to right four, that is, realize the calculation function divided by 16；Can therefrom it see,
Output signal ratio input signal has lacked four, this four are right-shifted by and lose, that is, have ignored this four influences to data, because
To become decimal after this four bitwise shift right, to the influence very little of original data, therefore it can be omitted and not remember, so using displacement
Register realizes that division is that there is no problem.For 3 × 3 Gaussian templates, 9 coefficients of template are all 2 integers
Power, and the integral number power that the sum of all weighting coefficients are 16 and 2, so for the Gaussian filter operation of the template, institute
Some multiplyings and division arithmetic can be replaced with shift register, not need to call multiplication or dividing module, so that
Design complexities substantially reduce.For example move to left 2 with shift register and represent multiplied by 4, it moves to right 4 and represents divided by 16, such ten
Divide easily instead of multiplication and division operation.If the value of σ changes, the weighting coefficient and division factor of generated template
May not be 2 integral number power, but if this coefficient and 2 n times power it is similar (n is natural number), still coefficient can be used this
A approximate number replaces.
If the product coefficient in multiplying is not 2 integral number power, cannot directly be carried out by shift register left
It moves and realizes, and call multiplier LMP macroelement module that can then occupy a large amount of hardware resource, be unfavorable at Rapid Implementation image
At this moment reason can shift adder using tree-shaped, multiplier b can be indicated are as follows:
B=b7 × 27+b6×26+...+b2×22+b1×2+b0 (13)
And exporting y can indicate are as follows:
Y=a × b=a × b7 × 128+a × b6 × 64+...+a × b2 × 4+a × b1 × 2+a × b0 (14)
Wherein 8 × 1 multipliers can then be realized by moving to left, as shown in figure 12.
Since the present embodiment uses 3 × 3 gaussian filtering template, it is after normalization
For convenience of calculation, coefficient is made to be converted to integer, it is approximate using pascal's triangle when one-dimensional, when length is 3 [1 2 1]；
Two dimension pattern plate can be obtained by matrix multiple in two one-dimensional templates
It is described to be realized in the algorithm for fast implementing gaussian filtering using mean filter three times, i.e., by connecting three times
A mean filter processing, and mean filter average be exactly multiple add operation and a division arithmetic combination, directly
It calls dividing module too complicated, therefore division arithmetic is realized using shift register, if the size of square box is 9, signal number
It is 8b according to width, 3 can be moved to right using shift register come the approximate operation replaced divided by 9.FPGA is can be with concurrent operation
, in order to make full use of its parallel characteristics, the register of 8 9b is used herein, and FPGA has the reusing of module,
Therefore we first design the functional module once filtered, then call this module three times in principle diagram design platform, according to
Correct sequential relationship is attached, and as shown in figure 13, input signal may be implemented three times into concatenated mean filter three times is crossed
Mean filter, Figure 14 are mean filter simulation waveform.
The data outputting module task mainly after data carry out calculation process by 2-d gaussian filters module, utilizes
Filtered image data is sent to computer, and generates .txt file by the serial communication between FPGA and computer.Finally utilize
Image data in txt file is read out by MATLAB program, to generate filtered image result.As shown in figure 15.
In conclusion practicability is high the present invention is based on the point 2-d gaussian filters device image processing method of FPGA, advantage is prominent
Out, the domestic disadvantage not high in image noise reduction field computational efficiency now is compensated for, and this system hardware itself has simply
Structure also has versatility, while the internal logic circuit by changing FPGA, energy for the otherwise processing of image
Realize the processing requirement different based on dimensional Gaussian algorithm, this locating based on FPGA point dimensional Gaussian image noise reduction system
Reason aspect has greater flexibility and feasibility, is with a wide range of applications.
The above examples only illustrate the technical idea of the present invention, and this does not limit the scope of protection of the present invention, all
According to the technical idea provided by the invention, any changes made on the basis of the technical scheme each falls within the scope of the present invention
Within.
Claims (6)
1. a kind of point 2-d gaussian filters device based on FPGA, it is characterised in that: including the picture number for acquiring image pattern
According to input module, convenient for the clock input module of FPGA internal clocking frequency dividing control；And built by FPGA platform: decision processing
The clock division control module of timing, for the ROM module of data storage, for traversing sample and determining filter mask size
3 × 3 square box generation modules, and to the 2-d gaussian filters module that storage image information is handled；It further include that will handle
Discrete two-dimensional image afterwards carries out the data outputting module that terminal is shown.
2. a kind of point 2-d gaussian filters device image processing method based on FPGA, includes the following steps:
Step 1, the image pattern information that need to handle is read in by image data input module, and it is defeated in outside to mirror clock simultaneously
Enter module；
Step 2, ROM module is called, will be stored in step 1 by image data input module acquired image sample；
Step 3, the image pattern that invocation step 2 stores issues clock signal by clock division control module, rectangular by 3 × 3
Frame generation module generates mask on sample；
Step 4,2-d gaussian filters module is brought into the mask formed by 3 × 3 square box generation modules, the subsequent filter
Wave module will smoothly traverse sample image with 3 × 3 square boxes, and the mask all pixels successively taken out are filtered,
Export filtered data；
Step 5, by information filtered in step 4, serial communication is carried out by data outputting module, and finally by treated
Image is shown in computer terminal.
3. the point 2-d gaussian filters device image processing method based on FPGA as claimed in claim 2, it is characterised in that: described
In step 4, the process of 2-d gaussian filters is: first with each pixel of sliding window scan image line by line, then
The weighted average of the gray value of all pixels point replaces the gray value of central pixel point in sliding window, then according to new pixel
Point gray value exports the new image of a width in order.
4. the point 2-d gaussian filters device image processing method based on FPGA as claimed in claim 3, it is characterised in that: use
The 2-d gaussian filters algorithm quickly approached has any position i:
A is constant in formula；
Gaussian filter is approached using mean filter three times.
5. the point 2-d gaussian filters device image processing method based on FPGA as claimed in claim 2, it is characterised in that: described
In step 3,3 × 3 square box generation modules are designed using two FIFO memories.
6. the point 2-d gaussian filters device image processing method based on FPGA as claimed in claim 2, it is characterised in that: described
In step 5, filtered image data is sent to electricity using the serial communication between FPGA and computer by data outputting module
Brain, and .txt file is generated, MATLAB program is finally utilized, the image data in txt file is read out, to generate filter
Image result after wave.
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Cited By (6)
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|---|---|---|---|---|
| CN110189444A (en) * | 2019-05-28 | 2019-08-30 | 天津城建大学 | A kind of access control system based on wireless network |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110189444A (en) * | 2019-05-28 | 2019-08-30 | 天津城建大学 | A kind of access control system based on wireless network |
| CN110531118A (en) * | 2019-08-01 | 2019-12-03 | 广州晒帝智能科技有限公司 | A kind of multiple stage filtering method and device and equipment based on gyroscope acceleration |
| CN112651895A (en) * | 2020-12-31 | 2021-04-13 | 南京理工大学 | Image Gaussian filtering method based on FPGA |
| CN113766205A (en) * | 2021-09-07 | 2021-12-07 | 上海集成电路研发中心有限公司 | Tone mapping circuit and image processing apparatus |
| CN113766205B (en) * | 2021-09-07 | 2024-02-13 | 上海集成电路研发中心有限公司 | Tone mapping circuit and image processing apparatus |
| CN113822827A (en) * | 2021-09-18 | 2021-12-21 | 凌云光技术股份有限公司 | Mean value filtering method and device based on FPGA external memory |
| CN113822827B (en) * | 2021-09-18 | 2024-03-22 | 凌云光技术股份有限公司 | Average filtering method and device based on FPGA external memory |
| CN116882358A (en) * | 2023-09-07 | 2023-10-13 | 深圳比特微电子科技有限公司 | Filter, filtering method, data processing system and chip |
| CN116882358B (en) * | 2023-09-07 | 2024-05-28 | 深圳比特微电子科技有限公司 | Filter, filtering method, data processing system and chip |
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