CN105977204A - 3D global pixel unit and manufacturing method thereof - Google Patents
3D global pixel unit and manufacturing method thereof Download PDFInfo
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- CN105977204A CN105977204A CN201610478566.4A CN201610478566A CN105977204A CN 105977204 A CN105977204 A CN 105977204A CN 201610478566 A CN201610478566 A CN 201610478566A CN 105977204 A CN105977204 A CN 105977204A
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- 238000004519 manufacturing process Methods 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 238000005070 sampling Methods 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 21
- 238000011049 filling Methods 0.000 claims description 20
- 238000002360 preparation method Methods 0.000 claims description 18
- 230000005611 electricity Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000001914 filtration Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000003792 electrolyte Substances 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000000945 filler Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 80
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
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Abstract
The invention provides a 3D global pixel unit and a manufacturing method thereof. The 3D global pixel unit comprises a photosensitive diode manufactured on a first silicon substrate layer and a signal storage and reading-out circuit manufactured on a second silicon substrate layer, wherein the photosensitive diode and the signal storage and reading-out circuit are vertically arranged and are mutually connected through a through hole. According to the 3D global pixel unit, the back light technology and the 3D structure are employed, stereo unit structures are manufactured at different layers, the photosensitive diode and the signal storage and reading-out circuit are vertically arranged, so not only can light paths between the external part and the photosensitive diode are improved, light isolation of a signal storage capacitor is improved, and a chip area occupied by pixel units can be reduced.
Description
Technical field
The present invention relates to semiconductor image detection technology field, be specifically related to a kind of 3D 10T overall situation pixel cell
And preparation method thereof.
Background technology
Traditional global shutter pixel technique is mainly used in ccd image sensor.Owing to cmos image passes
Constantly popularizing of sensor, and owing to machine vision, film making, industry, automobile and scanning application requirement must
Must catch the object of quickly movement with high image quality, Ge great imageing sensor manufacturer has been directed to overcome
The relevant tradition obstacle of global shutter pixel technique is used on cmos image sensor.Under this effort,
The global shutter pixel technique provided has less Pixel Dimensions, bigger activity coefficient, lower dark
Electric current and lower noise so that what cmos image sensor became ccd sensor in more application can
Row replacement scheme.
In the overall pixel cell of conventional cmos image sensor, light sensitive diode and signal storage and reading
Go out circuit unit device all to do in the same plane.Memory element needs to take bigger area to make storage
The electric capacity of signal, therefore the area of overall situation pixel is difficult to reduce all the time, and activity coefficient is the least.Further,
Light sensitive diode, storage electric capacity and reading circuit three between easily interfere with each other.
Summary of the invention
In order to overcome problem above, it is desirable to provide the overall pixel cell of a kind of 3D structure and preparation thereof
Method, uses back-illuminated technique and 3D structure, makes stereo-unit structure in different aspects, it is possible to achieve signal
Reading circuit and the perpendicular interconnection of light sensitive diode.
In order to achieve the above object, the invention provides 3D overall situation pixel cell, at least include photosensitive region and
Signal storage and reading circuit region, the storage of described signal and reading circuit region have signal storage and read
Circuit (14)；Described photosensitive region and the storage of described signal and the arrangement of reading circuit region in the vertical direction；
Described photosensitive region is arranged in the first layer-of-substrate silicon (02), comprising:
Light sensitive diode (01) that described first layer-of-substrate silicon (02) back side sets gradually from top to bottom, anti-reflective coating
Layer (04), color filtration layer (05) and lenticule (06), be provided with in described light sensitive diode (01) both sides and be filled with
Dielectric isolated groove (03)；
The storage of described signal is arranged in the second layer-of-substrate silicon (10) with reading circuit region, comprising:
Described second layer-of-substrate silicon (10) back side sets gradually from the top down: the second dielectric layer (09),
Light shielding layer (08) and the first dielectric layer (07)；
The front of described second layer-of-substrate silicon (10) is followed successively by from bottom to top: signal storage with reading circuit (14),
It is positioned at described signal be stored in the 3rd dielectric layer (15) of reading circuit (14) top and be positioned at the 3rd electricity Jie
The metal level (M) of matter layer (15) top；Wherein,
By through hole (12) phase between described light sensitive diode (01) with the storage of described signal and reading circuit (14)
Even, one end of described through hole (12) connects described light sensitive diode (01), and described through hole (12) passes described first
Dielectric layer (07), described light shielding layer (08), described second dielectric layer (09) and described second silicon
Substrate layer (10) so that the other end of described through hole (12) connects the storage of described signal and reading circuit (14),
Further, the sidewall of described through hole (12) has the 4th dielectric layer (13)；
Described 3rd dielectric layer (15) is for the storage of described signal and reading circuit (14) and described metal
Isolation between layer (M)；Described 3rd dielectric layer (15) has contact hole (CT)；Described signal
Storage realizes interconnection by contact hole (CT) with described metal level (M) with reading circuit (14).
Preferably, the storage of described signal including with reading circuit (14): reset switch, the first sampling capacitance,
Second sampling capacitance, transfer tube, the first source follower, preliminary filling fulgurite, the first switching tube, second switch pipe,
3rd switching tube, the 4th switching tube, the second source follower, row selector；The drain electrode of described reset switch connects
Resetting voltage, the grid of described reset switch connects pixel input, and the source electrode of described reset switch connects transfer tube
Source electrode, the drain electrode of described transfer tube is connected with the negative electrode of pinned photodiode, the grid of described transfer tube
It is connected with pixel cell input；The drain electrode of the first source follower connects VDD, the source of described first source follower
Pole is connected with the drain electrode of charger, the source ground of described charger, and it is defeated that the grid of described charger connects pixel
Enter end；The source electrode of described first source follower and draining and described first switching tube of described preliminary filling fulgurite
Drain electrode, the drain electrode of described second switch pipe are connected, the source electrode of described first switching tube and described first sampling electricity
Drain electrode, the drain electrode of described 3rd switching tube held are connected, and the source electrode of described second switch pipe is adopted with described first
Sample electric capacity is connected with described 4th switching tube, the source electrode of described 4th switching tube and the source of described 3rd switching tube
The grid of pole and described second source follower is connected, and the source electrode of described second source follower selects with described row
The drain electrode of device is connected；The grid of described preliminary filling fulgurite is pixel cell input, described first switching tube, institute
The grid stating second switch pipe, described 3rd switching tube and described 4th switching tube inputs with pixel cell respectively
End is connected, the other end of described first sampling capacitance and the other end ground connection of described second sampling capacitance；Institute
The drain electrode stating the second source follower is connected with VDD, and the grid of described row selector is pixel cell input,
The source electrode of described row selector is as the outfan of whole pixel cell.
Preferably, the material of described first dielectric layer and described second dielectric layer is insulant.
Preferably, the material of described first dielectric layer and described second dielectric layer is silicon oxide.
Preferably, the material of described silicon substrate is monocrystal silicon.
In order to achieve the above object, present invention also offers the preparation side of a kind of above-mentioned 3D overall situation pixel cell
Method, comprising:
Step 01: be sequentially depositing described first dielectric layer in described first layer-of-substrate silicon front, described light hides
Barrier, described second dielectric layer and described second layer-of-substrate silicon；
Step 02: in described second layer-of-substrate silicon, described second dielectric layer, described light shielding layer, described
Forming described through hole in first dielectric layer and the first layer-of-substrate silicon, the bottom of described through hole inserts described first
In layer-of-substrate silicon；
Step 03: form described 4th dielectric layer at described through-hole side wall, and fill in described through hole
Metal；
Step 04: prepare the storage of described signal and reading circuit in described second layer-of-substrate silicon front；
Step 05: form described 3rd electrolyte in the described second layer-of-substrate silicon front completing described step 04
Layer；
Step 06: prepare described contact hole in described 3rd dielectric layer, and at described contact hole table
Face and described 3rd dielectric layer surface form described metal level；
Step 07: the thinning described first layer-of-substrate silicon back side；
Step 08: form described light sensitive diode in the described first layer-of-substrate silicon back side, make described photosensitive two
Pole pipe is connected with described through hole, and formation is positioned at the isolated groove around described light sensitive diode, and
Filling dielectric in described isolated groove；
Step 09: sequentially form on described isolated groove surface and described light sensitive diode surface anti-reflecting layer,
Described color filtration layer and described lenticule.
Preferably, in described step 04, prepared described signal storage includes with reading circuit: resets and opens
Close, the first sampling capacitance, the second sampling capacitance, transfer tube, the first source follower, preliminary filling fulgurite, first
Switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the second source follower, row selector；
The drain electrode of described reset switch connects resetting voltage, and the grid of described reset switch connects pixel input, described multiple
The source electrode of bit switch connects the source electrode of transfer tube, the negative electrode phase of the drain electrode of described transfer tube and pinned photodiode
Even, the grid of described transfer tube is connected with pixel cell input；The drain electrode of the first source follower meets VDD,
The described source electrode of the first source follower is connected with the drain electrode of charger, and the source ground of described charger is described
The grid of charger connects pixel input；The source electrode of described first source follower and the leakage of described preliminary filling fulgurite
Pole is connected with the drain electrode of the drain electrode of described first switching tube, described second switch pipe, described first switching tube
Source electrode is connected with the drain electrode of the drain electrode of described first sampling capacitance, described 3rd switching tube, described second switch
The source electrode of pipe is connected with described first sampling capacitance and described 4th switching tube, the source electrode of described 4th switching tube
Being connected with the source electrode of described 3rd switching tube and the grid of described second source follower, described second source is followed
The source electrode of device is connected with the drain electrode of described row selector；The grid of described preliminary filling fulgurite is pixel cell input,
Described first switching tube, described second switch pipe, described 3rd switching tube and the grid of described 4th switching tube
It is connected with pixel cell input respectively, the other end of described first sampling capacitance and described second sampling electricity
The other end ground connection held；The drain electrode of described second source follower is connected with VDD, the grid of described row selector
For pixel cell input, the source electrode of described row selector is as the outfan of whole pixel cell.
Preferably, in described step 01, preparing of described first dielectric layer and described second dielectric layer is equal
Use thermal oxidation technology.
Preferably, in described step 01, the preparation of described light shielding layer uses Damascus technics.
Preferably, described step 03 specifically includes:
Step 031: at described via bottoms and sidewall and described second layer-of-substrate silicon surface deposition described the
Four dielectric layers；
Step 032: use photoetching and etching technics, etching to remove described via bottoms and described second silicon substrate
Described 4th dielectric layer on layer surface, retains described 4th dielectric layer of described through-hole side wall；
Step 033: plating seed layer and filler metal successively in described through hole.
Overall pixel cell of 3D structure of the present invention and preparation method thereof, by using back-illuminated technique and 3D
Structure, makes stereo-unit structure in different aspects, it is possible to achieve signal read circuit and light sensitive diode
Perpendicular interconnection；Thus not only increase the extraneous light-path with light sensitive diode, improve signal storage electric capacity
Optically isolated degree, and reduce the chip area shared by pixel cell.
Accompanying drawing explanation
Fig. 1 is the cross section structure schematic diagram of the 3D overall situation pixel cell of a preferred embodiment of the present invention
Fig. 2 is the electrical block diagram of the 3D overall situation pixel cell of a preferred embodiment of the present invention
Fig. 3 is the flow process signal of the preparation method of the 3D overall situation pixel cell of a preferred embodiment of the present invention
Figure
Fig. 4-12 is each of the preparation method of the 3D overall situation pixel cell of a preferred embodiment of the present invention
Step schematic diagram
Detailed description of the invention
For making present disclosure more clear understandable, below in conjunction with Figure of description, to present disclosure
It is described further.Certainly the invention is not limited in this specific embodiment, those skilled in the art institute
Known to general replacement be also covered by within the scope of the present invention.
The 3D overall situation pixel cell of the present invention at least by the first layer-of-substrate silicon make photosensitive region and
The signal storage made in second layer-of-substrate silicon is constituted with reading circuit areas combine；Photosensitive region is positioned at signal
Storage and reading circuit overlying regions；Photosensitive region has the light sensitive diode being positioned at the first layer-of-substrate silicon, letter
Number storage with reading circuit unit area have be positioned at the second layer-of-substrate silicon signal storage and reading circuit, sense
Optical diode is positioned at above signal storage and reading circuit；Realize light sensitive diode by through hole to store with signal
Interconnection with reading circuit.
It should be noted that present invention could apply in 10T or 8T overall situation pixel cell.
Below in conjunction with accompanying drawing 1-12 and specific embodiment, the present invention is described in further detail.It should be noted that,
Accompanying drawing all uses the form simplified very much, uses non-ratio accurately, and only in order to facilitate, clearly to reach
Aid in illustrating the purpose of the present embodiment.
In the present embodiment, refer to Fig. 1,3D 10T overall situation pixel cell, at least include: be positioned at the first silicon
The photosensitive region (deficiency of the upper portion of the body wire frame in Fig. 1) of substrate layer and be positioned at the 10T signal storage of the second layer-of-substrate silicon and read
Circuit region (dificiency in lower-JIAO wire frame in Fig. 1)；Photosensitive region and 10T signal store with reading circuit region in vertically side
Upwards arrange；
Photosensitive region is arranged in the first layer-of-substrate silicon 02, comprising: first silicon substrate 02 back side is from upper past
Under the light sensitive diode 01, ARC 04, color filtration layer 05 and the lenticule 06 that set gradually,
It is provided with in light sensitive diode 01 both sides and is filled with dielectric isolated groove 03；
The storage of 10T signal is arranged in the second layer-of-substrate silicon 10 with reading circuit region, comprising: the second silicon
Substrate layer 10 back side is followed successively by from the top down: the second dielectric layer 09, light shielding layer 08 and the first electricity
Dielectric layer 07；The front of the second layer-of-substrate silicon 10 is followed successively by from bottom to top: the storage of 10T signal and reading circuit
14, it is positioned at signal be stored in the 3rd dielectric layer 15 above reading circuit 14 and be positioned at the 3rd electrolyte
Metal level M above layer 15；Here metal level M is can be with post-channel interconnection metal level；
Light sensitive diode 01 is connected by through hole 12 with between reading circuit 14 with the storage of 10T signal, through hole
One end of 12 connects light sensitive diode 01, through hole 12 through the first dielectric layer 07, light shielding layer 08, the
Two dielectric layer 09 and the second silicon substrates 10 so that the other end of through hole 12 connects the storage of 10T signal and reads
Go out circuit unit 14, and, the sidewall of through hole 12 has the 4th dielectric layer 13；
3rd dielectric layer 15 is for the isolation between the storage of 10T signal and reading circuit 14 and metal level M；
3rd dielectric layer 15 has contact hole CT；The storage of 10T signal and reading circuit 14 are by contact hole CT
Interconnection is realized with described metal level M；Here, also include: be positioned at the active of second layer-of-substrate silicon 10 back side with
Passive region 11.It is also preferred that the left the material of the first dielectric layer 07 and the second dielectric layer 09 is insulant,
Such as oxide, active and in passive region 11 active area is that p-type is doped with source region.Through hole 12 can be adopted
With the making of through-silicon-via (Through Silicon Via) technique.
In the present embodiment, refer to the storage of Fig. 2,10T signal and include with reading circuit 14: reset switch M1,
First sampling capacitance C1, the second sampling capacitance C2, transfer tube M2, the first source follower SF1 (M3), in advance
Charging valve M4, the first switching tube M5, second switch pipe M6, the 3rd switching tube M7, the 4th switching tube
M8, the second source follower SF2 (M9), row selector M10；The drain electrode of reset switch M1 connects resetting voltage
Vreset, the grid of reset switch M1 meets pixel input RX, and the source electrode of reset switch M1 connects transfer tube
The source electrode (FD node) of M2, the drain electrode of transfer tube M2 is connected with the negative electrode of light sensitive diode, transfer tube M2
Grid be connected with pixel cell input TG；The drain electrode of the first source follower SF1 (M3) meets VDD, the
The source electrode of one source follower SF1 (M3) is connected with the drain electrode of preliminary filling fulgurite M4, and the source electrode of preliminary filling fulgurite M4 connects
Ground, the grid of preliminary filling fulgurite M4 meets pixel input PC；The source electrode of the first source follower SF1 (M3) and
The drain electrode of preliminary filling fulgurite M4 is connected with drain electrode, the drain electrode of second switch pipe M6 of the first switching tube M5, the
The drain electrode of the source electrode of one switching tube M5 and the drain electrode of the first sampling capacitance C1, the 3rd switching tube M7 is connected,
The source electrode of second switch pipe M6 and the first sampling capacitance C1 and the 4th switching tube M8 are connected, the 4th switching tube
The grid of the source electrode of M8 and the source electrode of the 3rd switching tube M7 and the second source follower SF2 (M9) is connected, the
The source electrode of two source follower SF2 (M9) is connected with the drain electrode of row selector M10；The grid of preliminary filling fulgurite M4
For pixel cell input PC, the first switching tube M5, second switch pipe M6, the 3rd switching tube M7 and
The grid of four switching tube M8 is connected with pixel cell input S1, S2, S3, S4 respectively, the first sampling electricity
Hold other end ground connection and the other end ground connection of the second sampling capacitance C2 of C1；Second source follower SF2 (M9)
Drain electrode be connected with VDD, the grid of row selector M10 is pixel cell input RS, row selector
The source electrode of M10 is as the outfan of whole pixel cell.By first, second, third and fourth switching tube
According to certain sequential, reset switch and transfer tube are stored respectively on first, second sampling capacitance,
In realizing eventually the signal voltage obtained in time of exposure is stored in pixel cell, a period of time reads again, thus
Realize the global shutter exposure of whole pixel unit array.
Refer to Fig. 3, in the present embodiment, the preparation method of above-mentioned 3D overall situation pixel cell, including:
Step 01: refer to Fig. 4, be sequentially depositing in the first layer-of-substrate silicon 02 front the first dielectric layer 07,
Light shielding layer the 08, second dielectric layer 09 and the second layer-of-substrate silicon 10；
Concrete, thermal oxidation technology can be used to prepare the first dielectric layer 07 and the second dielectric layer 09；
Damascus technics can be used to prepare light shielding layer 08；The preparation of the second layer-of-substrate silicon 10 can use silicon
Epitaxy technique.
Step 02: refer to Fig. 5, second layer-of-substrate silicon the 10, second dielectric layer 09, light shielding layer 08,
Forming through hole 12 in first dielectric layer 07 and the first layer-of-substrate silicon 02, the first silicon is inserted in the bottom of through hole 12
In substrate layer 02；
Concrete, use through-silicon-via (Through Silicon Via) technique to etch through hole 12.
Step 03: refer to Fig. 6, forms the 4th dielectric layer 13 at through hole 12 sidewall, and at through hole
Filler metal in 12；
Concrete, including:
Step 031: be situated between with sidewall and the second layer-of-substrate silicon 10 surface deposition the 4th electricity bottom through hole 12
Matter layer 13；
Step 032: use photoetching and etching technics, etching to remove bottom through hole 12 and the second layer-of-substrate silicon 10
4th dielectric layer 13 on surface, retains the 4th dielectric layer 13 of through hole 12 sidewall；
Step 033: plating seed layer and filler metal successively in through hole 12.
Step 04: refer to Fig. 7, prepare in the second layer-of-substrate silicon 10 front the storage of above-mentioned 10T signal with
Reading circuit 14；
Concrete, total is inverted, forms active and passive region 11 in the second layer-of-substrate silicon 10 front,
As used ion implanting to form p-type doped with source region；
Step 05: refer to Fig. 8, forms the 3rd electricity in the second layer-of-substrate silicon 10 front completing step 04
Dielectric layer 15；
Concrete, can be, but not limited to use thermal oxidation technology or chemical vapor deposition method to prepare the 3rd electricity
Dielectric layer 15；
Step 06: refer to Fig. 9, prepares contact hole CT in the 3rd dielectric layer 15, and is connecing
Contact hole CT surface and the 3rd dielectric layer 15 forming metal layer on surface M；
Concrete, prepare contact hole CT through photoetching and etching technics, complete the storage of 10T signal and read electricity
The line on road 14 and metal level M and the making of contact block (pad).
Step 07: refer to Figure 10, thinning first layer-of-substrate silicon 02 back side；
Step 08: refer to Figure 11, forms light sensitive diode 01 in first layer-of-substrate silicon 02 back side, makes
Obtain light sensitive diode 01 to be connected with through hole 12, and formation is positioned at the isolating trenches around light sensitive diode 01
Groove 03, and filling dielectric in isolated groove 03；
Concrete, light sensitive diode 01 can use light sensitive diode here；The first layer-of-substrate silicon 02 is made to carry on the back
Facing up, carry out N-type ion implanting in the first layer-of-substrate silicon 02, ion implanting certain depth is to the first silicon
Substrate layer 02 front, and prepare light sensitive diode 01, carry out photoetching and quarter around light sensitive diode 01
Erosion forms isolated groove 03, then can be, but not limited to use chemical vapor deposition method at isolated groove 03
Interior filling dielectric；
Step 09: refer to Figure 12, forms anti-reflective on isolated groove 03 surface and light sensitive diode 01 surface
Penetrate layer 04, color filtration layer 05 and lenticule 06；
Concrete, can be, but not limited to complete the first layer-of-substrate silicon 02 back side and isolated groove of step 08
03 surface-coated or deposit anti-reflecting layer 04, then sequentially form color filtration layer on anti-reflecting layer 04 surface
05 and the preparation of lenticule 06, this step can use common process, repeat no more here.
Although the present invention discloses as above with preferred embodiment, right described embodiment is lifted only for the purposes of explanation
Example, is not limited to the present invention, and those skilled in the art is without departing from spirit and scope of the invention
On the premise of can make some changes and retouching, the protection domain that the present invention is advocated should be with claims institute
State and be as the criterion.
Claims (10)
1. a 3D overall situation pixel cell, at least includes photosensitive region and signal storage and reading circuit region,
The storage of described signal and reading circuit region have signal storage and reading circuit (14)；It is characterized in that, described
Photosensitive region and the storage of described signal and the arrangement of reading circuit region in the vertical direction；
Described photosensitive region is arranged in the first layer-of-substrate silicon (02), comprising:
Light sensitive diode (01) that described first layer-of-substrate silicon (02) back side sets gradually from top to bottom, anti-reflective
Penetrate coating (04), color filtration layer (05) and lenticule (06), be provided with in described light sensitive diode (01) both sides and fill out
It is filled with dielectric isolated groove (03)；
The storage of described signal is arranged in the second layer-of-substrate silicon (10) with reading circuit region, comprising:
Described second layer-of-substrate silicon (10) back side sets gradually from the top down: the second dielectric layer (09),
Light shielding layer (08) and the first dielectric layer (07)；
The front of described second layer-of-substrate silicon (10) is followed successively by from bottom to top: signal storage and reading electricity
Road (14), be positioned at described signal storage with reading circuit (14) top the 3rd dielectric layer (15) and position
Metal level (M) in the 3rd dielectric layer (15) top；Wherein,
By through hole (12) phase between described light sensitive diode (01) with the storage of described signal and reading circuit (14)
Even, one end of described through hole (12) connects described light sensitive diode (01), and described through hole (12) passes described first
Dielectric layer (07), described light shielding layer (08), described second dielectric layer (09) and described second silicon
Substrate layer (10) so that the other end of described through hole (12) connects the storage of described signal and reading circuit (14),
Further, the sidewall of described through hole (12) has the 4th dielectric layer (13)；
Described 3rd dielectric layer (15) is for the storage of described signal and reading circuit (14) and described metal
Isolation between layer (M)；Described 3rd dielectric layer (15) has contact hole (CT)；Described signal
Storage realizes interconnection by contact hole (CT) with described metal level (M) with reading circuit (14).
3D overall situation pixel cell the most according to claim 1, it is characterised in that described signal storage with
Reading circuit (14) including: reset switch, the first sampling capacitance, the second sampling capacitance, transfer tube, the
One source follower, preliminary filling fulgurite, the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube,
Second source follower, row selector；The drain electrode of described reset switch connects resetting voltage, described reset switch
Grid connects pixel input, and the source electrode of described reset switch connects the source electrode of transfer tube, the drain electrode of described transfer tube
Being connected with the negative electrode of pinned photodiode, the grid of described transfer tube is connected with pixel cell input；The
The drain electrode of one source follower meets VDD, and the described source electrode of the first source follower is connected with the drain electrode of charger, institute
Stating the source ground of charger, the grid of described charger connects pixel input；Described first source follower
Drain electrode and the drain electrode of described first switching tube, the leakage of described second switch pipe of source electrode and described preliminary filling fulgurite
The most connected, the source electrode of described first switching tube and the drain electrode of described first sampling capacitance, described 3rd switching tube
Drain electrode be connected, the source electrode of described second switch pipe and described first sampling capacitance and described 4th switching tube phase
Even, the source electrode of described 4th switching tube and the source electrode of described 3rd switching tube and described second source follower
Grid is connected, and the source electrode of described second source follower is connected with the drain electrode of described row selector；Described precharge
The grid of pipe is pixel cell input, described first switching tube, described second switch pipe, the described 3rd opens
Described in Guan Guanhe, the grid of the 4th switching tube is connected with pixel cell input respectively, described first sampling capacitance
The other end and the other end ground connection of described second sampling capacitance；The drain electrode of described second source follower with
VDD is connected, and the grid of described row selector is pixel cell input, the source electrode conduct of described row selector
The outfan of whole pixel cell.
3D overall situation pixel cell the most according to claim 1, it is characterised in that described first electrolyte
The material of layer and described second dielectric layer is insulant.
3D overall situation pixel cell the most according to claim 3, it is characterised in that described first electrolyte
The material of layer and described second dielectric layer is silicon oxide.
3D overall situation pixel cell the most according to claim 1, it is characterised in that the material of described silicon substrate
Material is monocrystal silicon.
6. the preparation method of the 3D overall situation pixel cell described in a claim 1, it is characterised in that including:
Step 01: be sequentially depositing described first dielectric layer in described first layer-of-substrate silicon front, described light hides
Barrier, described second dielectric layer and described second layer-of-substrate silicon；
Step 02: in described second layer-of-substrate silicon, described second dielectric layer, described light shielding layer, described
Forming described through hole in first dielectric layer and the first layer-of-substrate silicon, the bottom of described through hole inserts described first
In layer-of-substrate silicon；
Step 03: form described 4th dielectric layer at described through-hole side wall, and fill in described through hole
Metal；
Step 04: prepare the storage of described signal and reading circuit in described second layer-of-substrate silicon front；
Step 05: form described 3rd electrolyte in the described second layer-of-substrate silicon front completing described step 04
Layer；
Step 06: prepare described contact hole in described 3rd dielectric layer, and at described contact hole table
Face and described 3rd dielectric layer surface form described metal level；
Step 07: the thinning described first layer-of-substrate silicon back side；
Step 08: form described light sensitive diode in the described first layer-of-substrate silicon back side, make described photosensitive two
Pole pipe is connected with described through hole, and formation is positioned at the isolated groove around described light sensitive diode, and
Filling dielectric in described isolated groove；
Step 09: sequentially form on described isolated groove surface and described light sensitive diode surface anti-reflecting layer,
Described color filtration layer and described lenticule.
Preparation method the most according to claim 6, it is characterised in that in described step 04, prepared
Described signal storage include with reading circuit: reset switch, the first sampling capacitance, the second sampling capacitance,
Transfer tube, the first source follower, preliminary filling fulgurite, the first switching tube, second switch pipe, the 3rd switching tube,
4th switching tube, the second source follower, row selector；The drain electrode of described reset switch connects resetting voltage, institute
The grid stating reset switch connects pixel input, and the source electrode of described reset switch connects the source electrode of transfer tube, described
The drain electrode of transfer tube is connected with the negative electrode of pinned photodiode, and the grid of described transfer tube is defeated with pixel cell
Enter end to be connected；The drain electrode of the first source follower connects VDD, the source electrode of described first source follower and charger
Drain electrode is connected, and the source ground of described charger, the grid of described charger connects pixel input；Described
The drain electrode of the source electrode of one source follower and described preliminary filling fulgurite and the drain electrode of described first switching tube, described the
The drain electrode of two switching tubes is connected, the source electrode of described first switching tube and the drain electrode of described first sampling capacitance, institute
The drain electrode stating the 3rd switching tube is connected, the source electrode of described second switch pipe and described first sampling capacitance and described
4th switching tube is connected, the source electrode of the source electrode of described 4th switching tube and described 3rd switching tube and described the
The grid of two source followers is connected, and the source electrode of described second source follower is connected with the drain electrode of described row selector；
The grid of described preliminary filling fulgurite is pixel cell input, described first switching tube, described second switch pipe,
Described 3rd switching tube is connected with pixel cell input respectively with the grid of described 4th switching tube, and described
The other end of one sampling capacitance and the other end ground connection of described second sampling capacitance；Described second source follower
Drain electrode be connected with VDD, the grid of described row selector is pixel cell input, described row selector
Source electrode is as the outfan of whole pixel cell.
Preparation method the most according to claim 6, it is characterised in that in described step 01, described
The preparation of one dielectric layer and described second dielectric layer all uses thermal oxidation technology.
Preparation method the most according to claim 6, it is characterised in that in described step 01, described light
The preparation of barrier bed uses Damascus technics.
Preparation method the most according to claim 6, it is characterised in that described step 03 is specifically wrapped
Include:
Step 031: at described via bottoms and sidewall and described second layer-of-substrate silicon surface deposition described the
Four dielectric layers；
Step 032: use photoetching and etching technics, etching to remove described via bottoms and described second silicon substrate
Described 4th dielectric layer on layer surface, retains described 4th dielectric layer of described through-hole side wall；
Step 033: plating seed layer and filler metal successively in described through hole.
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| CN108281446A (en) * | 2018-01-30 | 2018-07-13 | 德淮半导体有限公司 | Imaging sensor and the method for forming imaging sensor |
| CN110324548A (en) * | 2019-06-27 | 2019-10-11 | Oppo广东移动通信有限公司 | A kind of pixel unit circuit, signal processing method and storage medium |
| CN112729566A (en) * | 2020-12-15 | 2021-04-30 | 上海集成电路研发中心有限公司 | Detector imaging device |
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| US20040041219A1 (en) * | 2002-08-27 | 2004-03-04 | Calvin Chao | Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure |
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| US20040041219A1 (en) * | 2002-08-27 | 2004-03-04 | Calvin Chao | Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure |
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| CN108281446A (en) * | 2018-01-30 | 2018-07-13 | 德淮半导体有限公司 | Imaging sensor and the method for forming imaging sensor |
| CN110324548A (en) * | 2019-06-27 | 2019-10-11 | Oppo广东移动通信有限公司 | A kind of pixel unit circuit, signal processing method and storage medium |
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