CN105552094B - Pixel unit, imaging system and the method that optical isoaltion structure is made in pixel unit - Google Patents
Pixel unit, imaging system and the method that optical isoaltion structure is made in pixel unit Download PDFInfo
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- CN105552094B CN105552094B CN201510700902.0A CN201510700902A CN105552094B CN 105552094 B CN105552094 B CN 105552094B CN 201510700902 A CN201510700902 A CN 201510700902A CN 105552094 B CN105552094 B CN 105552094B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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- H04N25/70—SSIS architectures; Circuits associated therewith
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Abstract
Present application is related to a kind of pixel unit, imaging system and the method that optical isoaltion structure is made in pixel unit.Pixel unit includes photodiode, and the photodiode is placed in semiconductor material with the accumulation of image in response to the guided incident light to the photodiode.Global shutter gate gated transistors are placed in the semiconductor material and are coupled to the photodiode selectively to exhaust the described image charge from the photodiode.Memory transistor is placed in the semiconductor material to store described image charge.Optical isoaltion structure is placed in the semiconductor material stray light and spuious charge on the outside of the memory transistor in the side wall and the semiconductor material close to the memory transistor the memory transistor is isolated.The optical isoaltion structure is filled with tungsten.
Description
Technical field
The present invention relates generally to semiconductor processes.More specifically, example of the invention with global shutter
The semiconductor processes of image sensor pixel cells are related.
Background technique
For high speed imaging sensor, global shutter can be used to capture the object fast moved.Global shutter usually makes
The all pixels unit obtained in imaging sensor can capture image simultaneously.For the object moved more slowly, use is more common
Rolling shutter.Rolling shutter usually captures image with a sequence.For example, two-dimentional (" 2D ") pixel unit battle array can sequentially be enabled
Every a line in column so that each pixel unit in single row captures image simultaneously, but enables every a line with rolling sequence.Such as
This, each pixel unit row captures image during different images obtain window.For the object slowly moved, between every a line
Time difference can produce image fault.For the object fast moved, rolling shutter can lead to be felt along the shifting axle of object
Know elongation distortion.
To implement global shutter, storage or memory transistor can be used for temporarily storing by each pixel in array
Its waiting is read the image charge that unit obtains from pixel unit array simultaneously.When using global shutter, usually using transfer
Image charge is transferred to memory transistor from photodiodes by transistor, and will then be stored using output transistor
Image charge is transferred to the reading node of pixel unit from memory transistor.Influence the image sensor pixel with global shutter
The factor of the performance of unit includes global shutter efficiency, dark current, white pixel and picture lag.In general, global shutter
Pixel performance is improved with global shutter efficiency improvement.Global shutter efficiency be to signal charge can not by parasitic and/
Or the measurement of the good degree in memory node is stored in the case where electrical crosstalk pollution.
Summary of the invention
In an aspect, present application provides a kind of pixel unit comprising：Photodiode is placed in and partly leads
With the accumulation of image in response to the guided incident light to the photodiode in body material；Global shutter gate polar crystal
Pipe, is placed in the semiconductor material and is coupled to the photodiode selectively to exhaust from the photoelectricity two
The described image charge of pole pipe；Memory transistor is placed in the semiconductor material to store described image charge；And light
Isolation structure is learned, is placed in the semiconductor material close to the memory transistor so that the memory transistor is isolated
The stray light and spuious charge on the outside of the memory transistor in side wall and the semiconductor material, wherein the optics every
There is tungsten from structure filling.
In another aspect, present application provides a kind of imaging system comprising：The pixel array of pixel unit, wherein
Each of described pixel unit includes：Photodiode, be placed in semiconductor material in response to guided to institute
State the incident light of photodiode and accumulation of image；Global shutter gate gated transistors are placed in the semiconductor material
In and be coupled to the photodiode selectively to exhaust the described image charge from the photodiode；Storage is brilliant
Body pipe is placed in the semiconductor material to store described image charge；And optical isoaltion structure, it is placed in described half
Close to the memory transistor to be isolated in the side wall and the semiconductor material of the memory transistor in conductor material
Stray light and spuious charge on the outside of the memory transistor, wherein the optical isoaltion structure is filled with tungsten；Control circuit,
It is coupled to the pixel array to control the operation of the pixel array；And reading circuit, it is coupled to the pixel array
To read image data from the multiple pixel.
In another aspect, present application provides a kind of make in the pixel unit with global shutter and is optically isolated knot
The method of structure, the method includes：It is brilliant next to the storage of the pixel unit in the semiconductor material of the pixel unit
Body pipe forms deep trench isolation opening；Passivation is formed above the internal side wall of deep trench isolation opening；In the depth
Thin-oxide is formed above the passivation of trench isolations opening；Described in deep trench isolation opening is coated with titanium nitride
Internal side wall；The deep trench isolation opening is filled with tungsten；And it is formed above the tungsten in deep trench isolation opening
Protective layer, wherein the protective layer includes one of oxide or nitride, wherein described in optical isoaltion structure isolation
The stray light and spuious charge on the outside of the memory transistor in memory transistor and the semiconductor material.
Detailed description of the invention
It refers to the following figures and describes non-limiting and non-exclusive example of the invention, wherein run through various views, it is similar
Component symbol refers to similar component, unless otherwise prescribed.
Fig. 1 is the pixel unit for illustrating the global pixel storage organization comprising isolation of teaching according to the present invention
The schematic diagram of one example.
Fig. 2 is the pixel unit for illustrating the global pixel storage organization comprising isolation of teaching according to the present invention
The cross-sectional view of a part of one example.
Fig. 3 is to illustrate the production isolation structure of teaching according to the present invention so that the reality of global pixel storage organization is isolated
The flow chart of example property process.
Fig. 4 is the figure for illustrating an example of the imaging system comprising pixel array for teaching according to the present invention
Formula, the pixel array include the pixel unit of the global pixel storage organization with isolation.
In all several views of schema, counter element symbol indicates corresponding component.Those skilled in the art will
Understand, the element in figure is to illustrate for the sake of simple and is clear, and be not necessarily drawn to scale.For example, in figure
The size of some elements in element may be exaggerated relative to other elements to help to improve to various implementations of the invention
The understanding of example.In addition, not describing useful or required common and well-known member in commercially viable embodiment usually
Part is to promote the more unobstructed observation to these various embodiments of the invention.
Specific embodiment
As will be shown, the method and apparatus for being directed to the global shutter pixel storage organization of isolation is disclosed.It is described below
In, state numerous specific details in order to provide thorough understanding of the present invention.In the following description, statement numerous specific details with
A thorough understanding of embodiments are just provided.However, those skilled in the technology concerned are it will be recognized that skill described herein
Art can be practiced in the case where not having one or more of specific detail or by other methods, component, material etc..At it
In its example, well-known structure, material or operation are not shown in detail or described to avoid keeping some aspects fuzzy.
" one embodiment ", " embodiment ", " example " or referring to for " example " are meant through this specification
In conjunction with the embodiments or a particular feature, structure, or characteristic described in example is contained at least one embodiment of the present invention or example
In.Therefore, occur in each place of this specification for example " in one embodiment " or " in an example "
Phrase is not all referring to identical embodiment or example.In addition, in one or more embodiments or example, it can be with any suitable side
Formula combines a particular feature, structure, or characteristic.It is hereafter by reference to attached drawing to used in the description of example of the invention
Term and element detailed description.
As will be shown, the circular storage crystal of one or more deep trench optical isoaltion structures comprising being filled with tungsten is disclosed
The global shutter pixel unit of pipe.It discusses in detail as discussed further below, the deep trench optical isoaltion structure isolation of tungsten filling
The side wall of the memory transistor of global shutter pixel unit and parasitic stray light and/or spuious charge are in order to avoid into storage crystal
Pipe.Therefore, global shutter efficiency is improved, because image charge of the isolated storage in memory transistor draws with by parasitic stray light
The pollutant risen, this reduces the electron hole pair generated in memory transistor due to parasitic stray light.In addition, according to this hair
Bright teaching prevents spuious charge from entering memory transistor, this reduces deep silicon electrical crosstalk.
To illustrate, Fig. 1 is the fast with global shutter and the overall situation of isolation of diagram illustrating teaching according to the present invention
The schematic diagram of one example of the pixel unit 100 of door pixel storage organization.In instances, pixel unit 100 can be pixel battle array
One of multiple pixel units in column.It is shown in example as depicted, pixel unit 100 includes global shutter gate
Transistor 102, transfering transistor 106, memory transistor 108, output transistor 110, reads node at photodiode 104
114, reset transistor 112, amplifier transistor 116 and the row selecting transistor 118 for being coupled to bit line 178.In an example
In, reading node 114 is the floating diffusion portion being placed in the semiconductor material of pixel unit 100.In an example, coupling is used
The transistor for closing source follower implements amplifier transistor 116.As Figure 1 shows the example, global shutter gate polar crystal
Pipe 102 is coupled in VGSBetween voltage and photodiode 104.
In operation, global shutter gate gated transistors are coupled to photoelectricity two and in response to global shutter signal GS
Pole pipe 104 is selectively coupled to voltage VGSSelectively to exhaust the image charge accumulated in photodiode 104.Light
Electric diode 104 is placed in semiconductor material pixel unit 100 in response to the guided incident light to photodiode 104
122 and accumulation of image.In an example, incident light 122 may be directed the semiconductor material across pixel unit 100
Front side.In another example, it should be understood that incident light 122 may be directed the back side of the semiconductor material across pixel unit 100.
The image charge accumulated in photodiode 104 is coupled to be transferred to memory transistor 108 by transfering transistor 106
Input.
In the illustrated case, memory transistor 108 is illustrated as in the semiconductor material of pixel unit 100
It is isolated by the first optical isoaltion structure 120A and the second optical isoaltion structure 120B.It discusses in detail as discussed further below,
In one example, teaching according to the present invention, the first optical isoaltion structure 120A and the second optical isoaltion structure 120B are to stop
It is global fast to improve that parasitic stray light and/or spuious charge from the peripheral region of memory transistor 108 enter memory transistor 108
The optically opaque optical isoaltion structure of door efficiency.
Example in Fig. 1 also illustrates output transistor 110 and is coupled to the output of memory transistor 108 so that image is electric
Lotus is selectively transferred to the reading node for floating diffusion portion FD in the illustrated example from memory transistor 108
114.Reset transistor 112 is coupled in resetting voltage VRESETWill be read in response to reset signal RST between reading node 114
Charge in egress 114 selectively resets.In instances, amplifier transistor 116 includes and is coupled to read node 114
Amplifier grid is to amplify the signal on reading node 114 to export image data from pixel unit 100.Row selecting transistor
118 are coupled between bit line 178 and amplifier transistor 116 so that image data is output to bit line 178.
Fig. 2 is the pixel unit for illustrating the global pixel storage organization comprising isolation of teaching according to the present invention
The cross-sectional view of a part of 200 example.In instances, pixel unit 200 can be multiple pixels in pixel array
One of unit.Note that in an example, the pixel unit 200 of Fig. 2 is the cross of a part of the pixel unit 100 of Fig. 1
Sectional view, and the element of similar name and number mentioned below is similar to as described above and couples and play a role.
It will be appreciated that the cross section of Fig. 2 illustrates not with each and each element crosses demonstrated in Figure 1, and therefore schemed in Fig. 1
The some elements (although presented in pixel unit 200) for solving explanation can not be seen in the cross section of Fig. 2 illustrates.
Illustrated example shows that pixel unit 200 includes the storage crystalline substance being placed in semiconductor material 228 in Fig. 2
Body pipe 208.In instances, memory transistor 208 includes memory block 278 to store the light by being placed in semiconductor material 228
The image charge that electric diode (for example, photodiode 104) is accumulated in response to the guided incident light to photodiode.
In an example, semiconductor material 228 may include silicon, and memory block 278 can be memory transistor 208 in storage grid
242 lower sections are formed with the storage diode of the doped silicon in semiconductor material 228, and wherein gate oxide 240, which is placed in, deposits
It stores up between grid 242 and memory block 278.
Example demonstrated in Figure 2 shows pixel unit 200 also comprising being placed in partly leading in 208 outside of memory transistor
Other surrounding components in body material 228.For example, global shutter gate gated transistors 202, which are illustrated as, is placed in half
In conductor material 228.In instances, it can be used global shutter gate gated transistors 202 by by voltage VGS224 are coupled to photoelectricity
Diode and selectively exhaust the image charge from the photodiode being also arranged in semiconductor material 228.
Pixel unit 200 is also comprising being placed in one or more light in semiconductor material 228 next to memory transistor 208
Learn isolation structure, such as (for example) optical isoaltion structure 220A and 220B.It is shown in example as depicted, according to this
The teaching of invention, optical isoaltion structure 220A and 220B be placed in semiconductor material 228 close to memory transistor 208 with every
Side wall from memory transistor 208 in the semiconductor material 228 in 208 outside of memory transistor parasitic stray light and/or
Spuious charge.
In an example, with filled with tungsten 234 deep trench optical isoaltion structure together in semiconductor material 228 shape
At each optical isoaltion structure 220A and 220B.In an example, it is that deep trench isolation is formed in semiconductor material 208 to be opened
After mouthful, and before filling deep trench isolation opening with tungsten 234, passivation is formed in the internal side wall of deep trench isolation opening
Layer 230.In an example, passivation layer 230 is P+ passivation layer 230.In instances, after forming passivation layer 230, in zanjon
Thin-oxide 231 is formed above passivation layer 230 in the internal side wall of slot isolation opening, as demonstrated.Then deep trench every
It leaves and forms titanium nitride coating 232 in the internal side wall of mouth above thin-oxide 231.In an example, according to the present invention
Teaching, then with tungsten 234 fill deep trench isolation opening to form optical isoaltion structure 220A and 220B.
In an example, after filling optical isoaltion structure 220A and 220B with tungsten 234, chemical machinery can be performed and throw
Light (CMP) and then the formation protective layer 236 above optical isoaltion structure 220A and 220B.In an example, protective layer 236
Include one of oxide or nitride (for example, for example silicon nitride).Example demonstrated in Figure 2, which also shows that, to be connect
Be bordering in the interlayer dielectric 284 of the front side 286 of pixel unit 200 formed comprising conducting body 246,250 and 254 conducting body with
And the metallic conductor comprising metallic conductor 244,248 and 252.It will be appreciated that teaching according to the present invention, is optically isolated knot each
Protective layer 236 above structure 220A and 220B protects gate oxide 240 from by each optical isoaltion structure 220A and 220B
Tungsten 234 pollute.
In operation, each optical isoaltion structure 220A and 220B is that parasitic stray light and/or spuious charge is stopped to enter
The optically opaque isolation structure in the area of the memory transistor 208 in semiconductor material 228.For example, pixel list wherein
Member 200 is in the example of front side-illuminated formula pixel unit, Fig. 2 illustrates the semiconductor entered in 208 outside of memory transistor
The stray light 222A of the front side 286 of material 228 is optically isolated structure 220A blocking.Stray light 222B can enter in storage crystal
Semiconductor material 228 in the region in 208 outside of pipe, and therefore photoelectricity generates electron hole pair, comprising as show in Figure 2
Charge 226.However, optical isoaltion structure 220A also block charge 226 enters memory transistor 208, as demonstrated.
It includes to be placed in close to semiconductor material 228 that example depicted in figure 2, which also illustrates pixel unit 200,
Metallic conductor and conducting body in the interlayer dielectric 284 of front side 286.For example, institute's exhibition in example as illustrated
Show, metallic conductor 244,248 and 252 provides the memory transistor that pixel unit 200 is arrived by conducting body 246,250 and 254
208、VGSThe electrical connection of the counter structure of 224 male parts and global shutter gate gated transistors 202.It will be appreciated that stray light can also be by
These structural scatterings are deflected away from these structures.For example, example depicted in figure 2 show stray light 220C deflection from
Metallic conductor 248 is opened towards memory transistor 208, and stray light 222D is deflected away from conducting body 250 towards memory transistor
208.However, as demonstrated, teaching according to the present invention, optical isoaltion structure 220B also stops stray light 222C and 222D to enter
Memory transistor 208.
Therefore, teaching according to the present invention, optical isoaltion structure 220A and 220B stop stray light and/or spuious charge from
Peripheral region in semiconductor material 228 enters memory transistor 208.In fact, the electron hole not generated comprising photoelectricity
Pair spuious charge can be generated in memory transistor 208.Therefore, teaching according to the present invention improves global shutter efficiency.
In another example, it should be understood that pixel unit 200 can be backside illuminated pixel unit.It answers in this example
Therefore solution, stray light can enter semiconductor material 228 by the back side 288 of semiconductor material 228.In this example, it should be understood that
Teaching according to the present invention, shielded layer 238 may be optionally formed on the back side 288 of semiconductor material 228 in memory transistor
208 tops.Shown in example as depicted, teaching according to the present invention, stray light 222E shielded by shielded layer 238 in order to avoid
Into semiconductor material 228 back side 288 into memory transistor 208.In an example, shielded layer 238 may include metal,
Such as (for example) tungsten.
Fig. 3 be illustrate teaching according to the present invention production be contained in the optical isoaltion structure in pixel unit with every
The flow chart of example process 356 from global pixel storage node structure.For example, in an example, it should be understood that real
Example property process 356 can describe the process of the pixel unit 100 that can be used for making Fig. 1 and/or the pixel unit 200 of Fig. 2, and hereafter
The mentioned element similarly named or numbered is similar to as described above and couples and play a role.
It is shown in example as illustrated in figure 3, the displaying of process frame 358 forms deep trench in a semiconductor material
Isolation opening.In an example, and then global shutter memory transistor or global fast that will be formed in a semiconductor material
The place of door memory transistor forms deep trench isolation opening in a semiconductor material.Process frame 360 is shown then in deep trench
It is isolated above the internal side wall of opening and forms passivation.In an example, passivation is P+ passivation.The displaying of process frame 36 connects
Form thin-oxide above passivation, and process frame 362 is shown then with nitride (for example, titanium nitride) in thin-oxide
Top coats the inner surface of deep trench isolation opening.Process frame 364 is shown then with tungsten filling deep trench isolation opening.
In an example, process frame 366 is shown can then execute chemical machine to the tungsten in deep trench optical isoaltion structure
Tool polishes (CMP).After polish tungsten, process frame 368 is shown then above the deep trench optical isoaltion structure of tungsten filling
Form protective layer.In an example, protective layer includes one of oxide or nitride (for example, silicon nitride).
Fig. 4 be illustrate teaching according to the present invention the imaging system 474 comprising exemplary pixel array 476 one
The schema of a example, exemplary pixel array 476 include the multiple images sensor of the global pixel storage organization with isolation
Pixel unit.It is shown in example as in the depicted, imaging system 474 includes to be coupled to control circuit 484 and reading circuit 480
The pixel array 476 of (it is coupled to function logic 482).
In an example, pixel array 476 be image sensor pixel cells (for example, pixel P1, P2, P3 ..., Pn)
Two dimension (2D) array.Note that pixel unit P1, P2 in pixel array 476 ... Pn can for Fig. 1 pixel unit 100 and/
Or Fig. 2 pixel unit 200 and/or the pixel unit made in Fig. 3 example, and similar name and volume mentioned below
Number element be similar to as described above and couple and play a role.As illustrated, each pixel unit arrangement is embarked on journey
(for example, row R1 to Ry) and (for example, column C1 to Cx) is arranged to obtain the image data of people, place, object etc., institute then can be used
Image data is stated to reproduce the 2D image of the people, place, object etc..
In an example, each pixel unit P1, P2, P3 ..., Pn obtained its image data or image charge it
Afterwards, described image data are read by bit line 478 by reading circuit 480 and are then transferred to function logic 482.In various examples
In, reading circuit 480 may include amplifying circuit, analog/digital (ADC) conversion circuit or other.Function logic 482 can simply store
Described image data even pass through the rear image effect of application (for example, cutting out, rotating, removing blood-shot eye illness, adjustment brightness, adjustment pair
Than degree or other) manipulate described image data.In an example, reading circuit 480 can once be read along alignment is read
A variety of other technologies (not illustrating) can be used to read described image data for a line image data (illustrated), such as
Series read-out reads the full parellel that all pixels carry out simultaneously.
In an example, control circuit 484 is coupled to pixel array 476 to control the operating characteristic of pixel array 476.
In an example, control circuit 484 is coupled to generate the image as described above for controlling each pixel unit and obtains
The global shutter signal and control signal taken.In instances, global shutter signal and control signal are same during individually obtaining window
All pixels unit P1, P2, P3 in Shi Qiyong pixel array 476 ... Pn with by image charge from each corresponding two pole of photoelectricity
Pipe transfer.
The above description of illustrated example of the invention comprising content described in abstract of invention is not intended to
It is exhaustive or be limited to revealed precise forms.Although describing the particular embodiment of the present invention for illustrative purpose herein
And example, but without departing substantially from relatively broader spirit of the invention and range, various equivalent modifications are possible.It is true
On, it should be understood that specific example voltage, electric current, frequency, power range values, time etc. be provide for explanatory purposes, and
Other values can also be used in the other embodiments and example of teaching according to the present invention.
According to above-detailed these modifications can be made to example of the invention.It is used in the attached claims
Term should not be construed to limit the invention to specific embodiment disclosed in specification and claims.But it is of the invention
Range will determine that described the appended claims will be explained according to the claim that is created by the appended claims completely
Principle is to understand.Therefore this specification and each figure should be considered as illustrative and non-limiting.
Claims (26)
1. a kind of pixel unit comprising：
Photodiode is placed in semiconductor material to accumulate in response to the guided incident light to the photodiode
Tired image charge；
Global shutter gate gated transistors, wherein a part of the global shutter gate transistor is placed in the semiconductor material
In and be coupled to the photodiode selectively to exhaust the described image charge from the photodiode；
Memory transistor, wherein a part of the memory transistor is placed in the semiconductor material to store described image
Charge；And
Optical isoaltion structure is placed in the semiconductor material brilliant the storage is isolated close to the memory transistor
The stray light and spuious charge on the outside of the memory transistor in the side wall of body pipe and the semiconductor material,
Wherein the optical isoaltion structure includes the deep trench isolation structure being formed in the semiconductor material, wherein the depth
Groove isolation construction is filled with tungsten, wherein the optical isoaltion structure further comprises being formed in the deep trench isolation structure
P+ passivation above internal side wall between the tungsten and the semiconductor material.
2. pixel unit according to claim 1, wherein the optical isoaltion structure is to be placed in the semiconductor material
In close to the memory transistor with the side wall of isolated storage transistor and being deposited described in the semiconductor material
Store up one of the stray light and the multiple optical isoaltion structures of the spuious charge on the outside of transistor.
3. pixel unit according to claim 1, further comprises：
Gate oxide level is placed in the memory transistor above the semiconductor material in the semiconductor material
Storage grid and the memory transistor memory block between；And
Protective layer is placed in above the optical isoaltion structure and close to the memory transistor to protect the grid oxygen
Compound layer is from by the tungsten contamination of the optical isoaltion structure, wherein being placed in described above the optical isoaltion structure
Protective layer includes one of oxide or nitride.
4. pixel unit according to claim 1, wherein the optical isoaltion structure further comprises being formed in the P+
Thin-oxide above passivation between the semiconductor material and the tungsten.
5. pixel unit according to claim 4, wherein the optical isoaltion structure further comprise be formed in it is described thin
Titanium nitride coating above oxide between the tungsten and the semiconductor material.
6. pixel unit according to claim 1, wherein the incident light is by the front side of the semiconductor material through drawing
Lead the photodiode.
7. pixel unit according to claim 1, wherein the incident light is by the back side of the semiconductor material through drawing
The photodiode is led, wherein the pixel unit further comprises being placed on the back side of the semiconductor material
Side is above the memory transistor to shield the memory transistor against the shielded layer of the stray light.
8. pixel unit according to claim 1 further comprises being placed in the semiconductor material and being coupled in
To select described image charge from the photodiode between the photodiode and the input of the memory transistor
Property it is transferred to the transfering transistor of the memory transistor.
9. pixel unit according to claim 1 further comprises being placed in the semiconductor material and being coupled to
Described image charge to be selectively transferred to read node from the memory transistor by the output of the memory transistor
Output transistor.
10. pixel unit according to claim 9, wherein the reading node includes being placed in the semiconductor material
Floating diffusion portion.
11. pixel unit according to claim 9, further comprises：
Reset transistor is placed in the semiconductor material and is coupled to the reading node；
Amplifier transistor is placed in the semiconductor material, is had and is coupled to the amplifier grid for reading node；
And
Row selecting transistor is placed in the semiconductor material, is coupled between bit line and the amplifier transistor.
12. a kind of imaging system comprising：
The pixel array of pixel unit, wherein each of described pixel unit includes：
Photodiode is placed in semiconductor material to accumulate in response to the guided incident light to the photodiode
Tired image charge；
Global shutter gate gated transistors, wherein a part of the global shutter gate transistor is placed in the semiconductor material
In and be coupled to the photodiode selectively to exhaust the described image charge from the photodiode；
Memory transistor, wherein a part of the memory transistor is placed in the semiconductor material to store described image
Charge；And
Optical isoaltion structure is placed in the semiconductor material brilliant the storage is isolated close to the memory transistor
The stray light and spuious charge on the outside of the memory transistor in the side wall of body pipe and the semiconductor material, wherein described
Optical isoaltion structure includes the deep trench isolation structure being formed in the semiconductor material, wherein the deep trench isolation structure
Filled with tungsten, wherein the optical isoaltion structure further comprises above the internal side wall for being formed in the deep trench isolation structure
P+ passivation between the tungsten and the semiconductor material；
Control circuit is coupled to the pixel array to control the operation of the pixel array；And
Reading circuit is coupled to the pixel array to read image data from the multiple pixel.
13. imaging system according to claim 12 further comprises being coupled to the reading circuit to come to store
The function logic of the described image data of each of the multiple pixel unit.
14. imaging system according to claim 12, wherein the control circuit is coupled to during individually obtaining window
Simultaneously enable all pixel units in pixel array with simultaneously transfer the figure from each corresponding photodiode
Mirror charge.
15. imaging system according to claim 12, wherein the optical isoaltion structure is to be placed in the semiconductor material
In material close to the memory transistor with the side wall of isolated storage transistor in the semiconductor material described
One of described stray light and multiple optical isoaltion structures of the spuious charge on the outside of memory transistor.
16. imaging system according to claim 12, wherein each of described pixel unit further comprises：
Gate oxide level is placed in the memory transistor above the semiconductor material in the semiconductor material
Storage grid and the memory transistor memory block between；And
Protective layer is placed in above the optical isoaltion structure and close to the memory transistor to protect the grid oxygen
Compound layer is from by the tungsten contamination of the optical isoaltion structure, wherein being placed in described above the optical isoaltion structure
Protective layer includes one of oxide or nitride.
17. imaging system according to claim 12, wherein the optical isoaltion structure further comprises being formed in the P
Thin-oxide above+passivation between the semiconductor material and the tungsten.
18. imaging system according to claim 17, wherein the optical isoaltion structure further comprise be formed in it is described
Titanium nitride coating above thin-oxide between the tungsten and the semiconductor material.
19. imaging system according to claim 12, wherein each of described pixel unit further comprises placement
In the semiconductor material and it is coupled between the photodiode and the input of the memory transistor with by the figure
Mirror charge is selectively transferred to the transfering transistor of the memory transistor from the photodiode.
20. imaging system according to claim 12, wherein each of described pixel unit further comprises placement
In the semiconductor material and be coupled to the output of the memory transistor with by described image charge from the storage crystal
Pipe is selectively transferred to read the output transistor of node.
21. imaging system according to claim 20, wherein the reading node includes being placed in the semiconductor material
In floating diffusion portion.
22. imaging system according to claim 20, wherein each of described pixel unit further comprises：
Reset transistor is placed in the semiconductor material and is coupled to the reading node；
Amplifier transistor is placed in the semiconductor material, is had and is coupled to the amplifier grid for reading node；
And
Row selecting transistor is placed in the semiconductor material, is coupled between bit line and the amplifier transistor.
23. a kind of method for making optical isoaltion structure in the pixel unit with global shutter comprising：
Deep trench isolation is formed next to the memory transistor of the pixel unit in the semiconductor material of the pixel unit
Opening；
Passivation is formed above the internal side wall of deep trench isolation opening, wherein deep trench isolation opening is described
The passivation above internal side wall is that P+ adulterates passivation；
Thin-oxide is formed above the passivation of deep trench isolation opening；
The internal side wall of the deep trench isolation opening is coated with titanium nitride；
The deep trench isolation opening is filled with tungsten；And
Protective layer is formed above the tungsten in deep trench isolation opening, wherein the protective layer includes oxide or nitrogen
One of compound, wherein the optical isoaltion structure be isolated the memory transistor in the semiconductor material described
Stray light and spuious charge on the outside of memory transistor.
24. according to the method for claim 23, further comprising the tungsten being in the deep trench isolation opening
Top executes the chemically mechanical polishing of the tungsten in the deep trench isolation opening before forming the protective layer.
25. according to the method for claim 23, wherein the protective layer includes one of oxide or nitride.
26. further comprising according to the method for claim 23, being deposited on the back side of the semiconductor material described
Store up transistor above formed shielded layer to shield the memory transistor in case stray light enter the semiconductor material described in
Back side.
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| US14/524,791 | 2014-10-27 | ||
| US14/524,791 US9484370B2 (en) | 2014-10-27 | 2014-10-27 | Isolated global shutter pixel storage structure |
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| US9484370B2 (en) | 2014-10-27 | 2016-11-01 | Omnivision Technologies, Inc. | Isolated global shutter pixel storage structure |
| FR3043495A1 (en) | 2015-11-09 | 2017-05-12 | St Microelectronics Crolles 2 Sas | IMAGE SENSOR WITH GLOBAL SHUTTER |
| FR3057395A1 (en) * | 2016-10-07 | 2018-04-13 | Stmicroelectronics (Crolles 2) Sas | IMAGE SENSOR WITH BACKLIGHT LIGHT |
| TW201817223A (en) * | 2016-10-20 | 2018-05-01 | 原相科技股份有限公司 | Global shutter high dynamic range pixel and global shutter high dynamic range image sensor |
| WO2018085250A1 (en) * | 2016-11-03 | 2018-05-11 | Bae Systems Information And Electronic Systems Integration Inc. | Backside illuminated global shutter cmos image sensor |
| JP6743181B2 (en) * | 2016-12-15 | 2020-08-19 | タワー パートナーズ セミコンダクター株式会社 | Solid-state image sensor |
| US10070079B2 (en) | 2017-01-30 | 2018-09-04 | Semiconductor Components Industries, Llc | High dynamic range global shutter image sensors having high shutter efficiency |
| US10566359B1 (en) * | 2018-08-22 | 2020-02-18 | Omnivision Technologies, Inc. | Variably biased isolation structure for global shutter pixel storage node |
| FR3085246B1 (en) | 2018-08-23 | 2020-09-18 | St Microelectronics Crolles 2 Sas | BUILT-IN IMAGE SENSOR WITH GLOBAL SHUTTER SUITABLE FOR THE ACHIEVEMENT OF LARGE DYNAMIC RANGE IMAGES |
| CN109326621B (en) * | 2018-10-17 | 2021-02-09 | 德淮半导体有限公司 | Method of forming image sensor and image sensor |
| KR102652444B1 (en) | 2019-01-11 | 2024-03-28 | 삼성전자주식회사 | Image sensor |
| JPWO2020195824A1 (en) * | 2019-03-28 | 2020-10-01 | ||
| JP2021044439A (en) * | 2019-09-12 | 2021-03-18 | 浜松ホトニクス株式会社 | Backside incident type image sensor |
| US11233080B2 (en) | 2019-12-30 | 2022-01-25 | Omnivision Technologies, Inc. | Image sensor with partially encapsulating attenuation layer |
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| US11695030B2 (en) * | 2020-12-30 | 2023-07-04 | Omnivision Technologies, Inc. | Reduced cross-talk pixel-array substrate and fabrication method |
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| US20170018583A1 (en) | 2017-01-19 |
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