CN109326621B - Method of forming image sensor and image sensor - Google Patents
Method of forming image sensor and image sensor Download PDFInfo
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- CN109326621B CN109326621B CN201811205424.6A CN201811205424A CN109326621B CN 109326621 B CN109326621 B CN 109326621B CN 201811205424 A CN201811205424 A CN 201811205424A CN 109326621 B CN109326621 B CN 109326621B
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
Abstract
The present disclosure relates to a method of forming an image sensor, comprising: forming a doped layer in a trench covering a wall of the trench, the doped layer having a P-type dopant and a concentration of the P-type dopant in the doped layer being higher than a concentration of the P-type dopant in a portion of the semiconductor substrate around the trench; forming a thermally conductive layer over the semiconductor substrate, the thermally conductive layer including a first portion located in the trench and covering the doped layer; and heat treating the semiconductor substrate from above the semiconductor substrate, wherein the thermally conductive layer conducts heat to the doped layer through the first portion, thereby causing the P-type dopant in the doped layer to diffuse into the semiconductor substrate, thereby forming a P-type diffusion region at the wall of the trench in the semiconductor substrate. The present disclosure also relates to an image sensor. The present disclosure can improve a dark current of an image sensor.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a method of forming an image sensor and an image sensor.
Background
Trench isolation structures (including Deep Trench Isolation (DTI) structures and Shallow Trench Isolation (STI) structures, etc.) are typically formed in CMOS image sensors.
Therefore, there is a need for new technologies.
Disclosure of Invention
An object of the present disclosure is to provide a novel method of forming an image sensor and an image sensor.
According to a first aspect of the present disclosure, there is provided a method of forming an image sensor, comprising: forming a doped layer in a trench in a semiconductor substrate covering a wall of the trench, the doped layer having a P-type dopant and a concentration of the P-type dopant in the doped layer being higher than a concentration of the P-type dopant in a portion of the semiconductor substrate surrounding the trench; forming a thermally conductive layer over the semiconductor substrate, the thermally conductive layer including a first portion located in the trench and covering the doped layer; and heat treating the semiconductor substrate from above the semiconductor substrate, wherein the thermally conductive layer conducts heat to the doped layer through the first portion, thereby causing the P-type dopant in the doped layer to diffuse into the semiconductor substrate, thereby forming a P-type diffusion region at the wall of the trench in the semiconductor substrate.
According to a second aspect of the present disclosure, there is provided an image sensor comprising: a trench isolation structure formed in a semiconductor substrate; and a diffusion region located around the trench isolation structure in the semiconductor substrate and covering the diffusion region, wherein the diffusion region has a P-type dopant and a concentration of the P-type dopant in the diffusion region is higher than a concentration of the P-type dopant in a portion of the semiconductor substrate located around the diffusion region, wherein the trench isolation structure includes: a high dielectric constant layer located at an outer layer portion of the trench isolation structure and covering the semiconductor substrate; and the low light transmission layer is positioned in the inner layer part of the groove isolation structure and covers the high dielectric constant layer.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1A to 1D are schematic views respectively schematically showing cross sections of an image sensor at some steps of an example of a method of forming an image sensor according to one or more exemplary embodiments of the present disclosure.
Fig. 2 is a schematic diagram schematically illustrating operations at the step illustrated in fig. 1C according to one or more exemplary embodiments of the present disclosure.
Fig. 3A and 3D are schematic diagrams respectively schematically illustrating cross-sections of an image sensor at some steps of an example of a method of forming an image sensor according to one or more exemplary embodiments of the present disclosure.
Fig. 4A and 4D are schematic diagrams respectively schematically illustrating cross-sections of an image sensor at some steps of an example of a method of forming an image sensor according to one or more exemplary embodiments of the present disclosure.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In some cases, similar reference numbers and letters are used to denote similar items, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.
For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.
Detailed Description
Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the structures and methods herein are shown by way of example to illustrate different embodiments of the structures and methods of the present disclosure. Those skilled in the art will understand, however, that they are merely illustrative of exemplary ways in which the disclosure may be practiced and not exhaustive. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
For convenience, orientations such as top, bottom, upper, lower, lateral, etc., are described herein with reference to the orientation shown in the figures. For example, when referring to the upper surface of a semiconductor substrate, it refers to the upper surface of the semiconductor substrate in the direction shown in the drawings, which may or may not be the surface for receiving light irradiation; similarly, when referring to the lower surface of the semiconductor substrate, it refers to the lower surface of the semiconductor substrate in the direction shown in the drawings, which may or may not be the surface for receiving light irradiation.
In a semiconductor substrate of a CMOS image sensor, a plurality of pixel units each including a photodiode and a transistor associated with the photodiode are generally arranged. Between adjacent devices (e.g., between photodiodes, between transistors, or between a photodiode and a transistor, etc.), there is typically a trench isolation structure to prevent interference between devices. The inventors of the present disclosure found, by studying the prior art, that some defects of these trench isolation structures, such as etching interface defects generated in the etching process for forming the trench, are liable to cause the generation of dark current.
Accordingly, in a first aspect of the present disclosure, a method of forming an image sensor is provided that can mitigate or eliminate dark current caused by etch interface defects of trenches.
A method of forming an image sensor according to one or more exemplary embodiments of the present disclosure is described below with reference to fig. 1A to 1D.
As shown in fig. 1A, processing is performed from the upper surface of the semiconductor substrate 11, and a trench 12 is formed in the semiconductor substrate 11. Wherein the trench 12 is formed between two adjacent devices or around the devices. It will be understood by those skilled in the art that it is meant that the trench 12 is located between or around two adjacent devices in a plan view parallel to the major surface of the image sensor. The trench 12 may be formed by, for example, a photolithography and etching process. The etching process to form the trench 12 may be a dry etching process.
Those skilled in the art will appreciate that the semiconductor substrate 11 may be made of any semiconductor material suitable for semiconductor devices, such as Si, SiC, SiGe, etc. The semiconductor substrate 11 may be a semiconductor portion of various composite substrates such as a silicon-on-insulator (SOI) substrate and a silicon-germanium-on-insulator (sige-on-insulator). It will be appreciated by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application.
Furthermore, although in the examples shown in the figures of the present disclosure, the trench 12 and other structures to be formed later are formed from the upper surface of the semiconductor substrate 11, those skilled in the art will understand that the trench 12 and other structures to be formed later may also be formed from the lower surface of the semiconductor substrate 11.
It will be appreciated by those skilled in the art that in the example shown in fig. 1A, the following processes may have been performed prior to forming the trench 12: the photodiode and the transistor associated with the photodiode are formed in the semiconductor substrate 11, the metal interconnection layer is formed on the lower surface of the semiconductor substrate 11, a device wafer and a carrier wafer including the semiconductor substrate 11 and the metal interconnection layer are subjected to bonding processing, and thinning processing and the like are performed on the top of the semiconductor substrate 11.
As shown in fig. 1B, processing is performed from the upper surface of the semiconductor substrate 11, and a doped layer 13 covering the walls of the trench 12 is formed in the trench 12 in the semiconductor substrate 11, wherein the doped layer 13 does not fill the entire trench 12. Doped layer 13 has a P-type dopant, which may be formed of a dielectric material or a semiconductor material having a P-type dopant, and the concentration of the P-type dopant in doped layer 13 is higher than the concentration of the P-type dopant in the portion of semiconductor substrate 11 around trench 12. The term "overlying" as used herein includes both full and partial overlying, for example, although doped layer 13 is shown in the figures as fully overlying the walls of trench 12, it will be understood by those skilled in the art that partially overlying the walls of trench 12 with doped layer 13 can serve the purpose of the present disclosure. The same applies to the other thermally conductive layers 14, diffusion regions 15, high dielectric constant layer 16, low light transmitting layer 17, and second oxide layer 18.
In some embodiments, the P-type dopant may be one or more of boron, indium, gallium, and the like. In some embodiments, the dielectric material with P-type dopants comprises one or more of borosilicate glass and boron oxide. The boron content of boron oxide is higher than that of borosilicate glass, and the desired concentration of a P-type dopant can be achieved by adjusting the ratio of borosilicate glass to boron oxide. The semiconductor material having P-type dopants comprises polysilicon doped with P-type dopants.
In some embodiments, doped layer 13 may be formed by an Atomic Layer Deposition (ALD) process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. The doping layer 13 formed by the atomic layer deposition process or the plasma enhanced chemical vapor deposition process has good uniformity, so that the diffusion region 15 formed subsequently has good uniformity, which is beneficial to reducing dark current, and the doping layer 13 can be formed to be thin enough to prevent excessive P-type dopant from diffusing to the semiconductor substrate 11 in the subsequent step to affect the performance of the photodiode. In some embodiments, doped layer 13 is formed to a thickness of less than 50 angstroms by an atomic layer deposition process or a plasma enhanced chemical vapor deposition process. The thickness of doped layer 13 herein refers to the dimension of doped layer 13 in the longitudinal direction of the drawing at, for example, a portion covering the bottom wall of trench 12, and the dimension of doped layer 13 in the lateral direction of the drawing at, for example, a portion covering the sidewall of trench 12.
In some embodiments, prior to forming doped layer 13, processing is performed from the upper surface of semiconductor substrate 11, forming a first oxide layer (not shown) in trench 12 in semiconductor substrate 11 that covers the walls of trench 12 and does not fill trench 12. Since the first oxide layer is located between the semiconductor substrate 11 and the doped layer 13, the first oxide layer may serve to block plasma damage to the semiconductor substrate 11 during formation of the doped layer 13 by a plasma enhanced chemical vapor deposition process; an oxygen source is introduced in the process of forming the first oxide layer, so that the etching defects on the wall of the groove 12 can be repaired, and the shape of a diffusion region formed in the subsequent step can be controlled; furthermore, the first oxide layer can also function to control the timing (e.g., prevent P-type dopant in doped layer 13 from entering semiconductor substrate 11 early) and thickness (e.g., adjust the thickness of P-type dopant in doped layer 13 diffused into semiconductor substrate 11 in a subsequent step by adjusting the thickness of the first oxide layer) of diffusion of P-type dopant in doped layer 13 into semiconductor substrate 11. In some embodiments, the first oxide layer may be formed by an Atomic Layer Deposition (ALD) process. The thickness of the formed first oxide layer can be determined according to design requirements and simulation and/or experiment results in practical application. In some embodiments, the first oxide layer has a thickness of 30 angstroms or less. The thickness of the first oxide layer herein means the dimension of the first oxide layer in the longitudinal direction of the drawing at a portion covering, for example, the bottom wall of the trench 12, and the dimension of the first oxide layer in the lateral direction of the drawing at a portion covering, for example, the side wall of the trench 12.
As shown in fig. 1C, a heat conductive layer 14 is formed over semiconductor substrate 11 from the upper surface of semiconductor substrate 11 such that heat conductive layer 14 includes a first portion (e.g., first portion 141 shown in fig. 2) that is located in trench 12 and covers doped layer 13. The heat conductive layer 14 is made of a material having a high thermal conductivity, such as silicon carbide, silver, copper, tungsten, or the like.
On the other hand, if the P-type dopant in doped layer 13 diffuses too much into semiconductor substrate 11, for example, if diffusion region 15 is formed to a greater thickness, the performance of the photodiode/transistor may be affected, for example, the full well capacity of the photodiode may be reduced. Therefore, in order to not occupy too much the area of the photodiode/transistor and not reduce the performance of the photodiode/transistor, the thickness of the diffusion region 15 should be as thin as possible under the premise of isolating the etching defect of the trench 12; at the same time, the diffusion region 15 cannot be too thin in order to ensure that the diffusion region 15 can isolate all etch defects of the trench 12 from the photodiode/transistor. In some embodiments, the diffusion region 15 is formed to a thickness of 1nm to 50 nm. The thickness of the diffusion region 15 herein means that the portion at, for example, the bottom wall of the trench 12 is the dimension of the diffusion region 15 in the longitudinal direction of the drawing, and the portion at, for example, the side wall of the trench 12 is the dimension of the diffusion region 15 in the lateral direction of the drawing.
This method conducts heat to the doping layer 13 covering the wall of the trench 12 by the heat conductive layer 14, so that only the semiconductor substrate 11 needs to be heat-treated from above the semiconductor substrate 11, and the entire semiconductor substrate 11 does not need to be heated, and thermal influence on the structures (e.g., metal interconnection layers, etc.) located at the middle-lower portion of the semiconductor substrate 11 (e.g., the implanted region of a photodiode, a transistor, etc.) and below the semiconductor substrate 11 can be avoided. In addition, by forming the heat conductive layer 14 with a material having good heat conductivity, the heat conductive layer 14 can rapidly conduct heat to the doped layer 13, so that the heating time can be shortened, the thermal influence on other structures can be further avoided, and the thermal budget can be saved. In some embodiments, the thermally conductive layer 14 comprises metallic tungsten. Tungsten has good thermal conductivity and can reduce or avoid metal contamination.
In some embodiments, in addition to the first portion 141, the thermally conductive layer 14 includes a second portion 142 overlying the semiconductor substrate 11 and covering the upper surface of the semiconductor substrate 11, see fig. 2, where the first portion 141 and the second portion 142 are continuous, such as by the third portion 143. It will be understood by those skilled in the art that reference herein to first portion 141 and second portion 142 being "continuous" means that heat transfer can occur between first portion 141 and second portion 142, and is not limited to first portion 141 and third portion 143 being in complete contact and second portion 142 and third portion 143 also being in complete contact as shown in the figures.
In these cases, heat treating the semiconductor substrate 11 from above the semiconductor substrate 11 includes heat treating the second portion 142 of the thermally conductive layer 14 from above the semiconductor substrate 11. Since first portion 141 and second portion 142 are continuous, when second portion 142, which is located on the top surface of semiconductor substrate 11, is heated, heat is conducted to first portion 141 of thermally conductive layer 14, and thus to doped layer 13, to promote diffusion of P-type dopants in doped layer 13 into semiconductor substrate 11.
Although the thermally conductive layer 14 is shown in the drawings as filling the entire trench 12, it will be understood by those skilled in the art that the thermally conductive layer 14 need only have a first portion 141 overlying the doped layer 13 and a second portion 142 overlying the upper surface of the semiconductor substrate 11, with the first portion 141 and the second portion 142 being contiguous. For example, thermally conductive layer 14 may also have a topography similar to doped layer 13 shown in the figures.
In order to heat only the semiconductor substrate 11 or only the second portion 142 on the upper surface of the semiconductor substrate 11, a process of heating only a local region (or a specific region) may be selected. In addition, Rapid Thermal Processing (RTP) may be selected so that the overall heating process time is not too long, and so that the P-type dopant does not diffuse too much, but not too deeply. In some embodiments, the heating treatment comprises one or more of: rapid thermal processing immersion annealing, rapid thermal processing spike annealing, laser annealing, and microwave annealing. With such a heating process, the local region is rapidly heated, so that the temperature of the heated region, such as the second portion 142, is rapidly increased, while other regions of the image sensor are kept at a lower temperature, thereby reducing the thermal budget; and due to the good thermal conductivity of thermally conductive layer 14, the heat received by second portion 142 is quickly and efficiently conducted to first portion 141 overlying doped layer 13 and further to doped layer 13, so that the P-type dopant in doped layer 13 can be diffused into semiconductor substrate 11 and activated in a short time, which can shorten the time for performing the heating process, thereby reducing the thermal budget while also preventing the P-type dopant from being diffused into semiconductor substrate 11 too much, i.e., without forming diffusion region 15 too thick, so as to not affect the performance of the photodiode.
On the other hand, the heating process requires a higher temperature in order to secure the effect of diffusion of the P-type dopant in doped layer 13 into semiconductor substrate 11 and enable the P-type dopant that has entered into semiconductor substrate 11 to be activated (e.g., boron ions that have entered into the silicon substrate bond with silicon). In some embodiments, the heating process causes the temperature of doped layer 13 to be not lower than 700 ℃. For example, when the heat treatment is performed by the rapid thermal processing immersion annealing, the heating time may be more than 1 second, so that the heating temperature and time of the doped layer 13 can be satisfied. Similarly, the heating time for rapid thermal processing spike annealing is greater than 1 millisecond, the heating time for laser annealing is greater than 1 millisecond, and the heating time for microwave annealing is greater than 1 second.
In some embodiments, where thermally conductive layer 14 is formed of a metallic material, an adhesion layer (not shown) is formed in trench 12 overlying doped layer 13 after doped layer 13 is formed and before thermally conductive layer 14 is formed; a thermally conductive layer 14 covering the adhesive layer is then formed in the groove 12. It will be appreciated by those skilled in the art that the adhesion layer may increase the adhesion between the metal and the media it is intended to cover, and may be more advantageous for the formation of the metallic thermally conductive layer 14.
After the diffusion regions 15 have been formed, the upper surface of the image sensor of the part that has been formed may be subjected to a planarization process, for example by an etching process or a Chemical Mechanical Polishing (CMP) process, in order to facilitate the formation of structures in and on the semiconductor substrate 11 in a subsequent step. In some embodiments, as shown in fig. 1D, portions of thermally conductive layer 14 and doped layer 13 above the upper surface of semiconductor substrate 11 may be removed (in some cases, portions of diffusion region 15 above the upper surface of semiconductor substrate 11 may also be removed). It will be understood by those skilled in the art that the planarization process may not remove these structures located above the upper surface of the semiconductor substrate 11, but simply planarize the upper surface of the already formed portion of the image sensor.
In the embodiments described above in connection with fig. 1A to 1D, the trench isolation structure of the image sensor is formed to include the doped layer 13 covering the walls of the trench and the thermally conductive layer 14 covering the doped layer 13. In the case where at least one of the doped layer 13 and the thermally conductive layer 14 is formed of a dielectric material, such a trench isolation structure can prevent out-diffusion of photogenerated carriers in the photodiode. Further, in the case where the material forming the heat conductive layer 14 also has low light transmittance, for example, in the case where the heat conductive layer 14 is formed of metal, such a trench isolation structure can also prevent crosstalk of light between the photodiodes. Meanwhile, the diffusion region 15 surrounding the trench isolation structure in the vicinity of the trench isolation structure in the semiconductor substrate 11 can reduce or eliminate dark current.
A method of forming an image sensor according to one or more exemplary embodiments of the present disclosure is described below with reference to fig. 3A to 3D.
In some embodiments, as shown in fig. 3A, after the diffusion region 15 is formed as shown in fig. 1D, the thermally conductive layer 14 and the doped layer 13 are removed. Removing the thermally conductive layer 14 and the doped layer 13 may be performed by a wet etching process, and the etching of the material of the thermally conductive layer 14 and the doped layer 13 may be selected to be a relatively high etching solution, for example by one or more of: DHF cleaning, SPM cleaning, APM cleaning, and HPM cleaning.
As shown in fig. 3B, after removing thermally conductive layer 14 and doped layer 13, high dielectric constant layer 16 covering the walls of trench 12 (i.e., covering diffusion region 15) is formed in trench 12. As shown in fig. 3C, after the high dielectric constant layer 16 is formed, a low light-transmitting layer 17 covering the high dielectric constant layer 16 may also be formed in the trench 12. As shown in fig. 3D, after the low-light-transmitting layer 17 is formed, the upper surface of the image sensor of the portion that has been formed is subjected to a planarization process, such as an etching process or a Chemical Mechanical Polishing (CMP) process, so that a structure in and over the semiconductor substrate 11 is formed in a subsequent step. In some embodiments, as shown in fig. 3D, portions of low-light-transmissive layer 17 and high-dielectric-constant layer 16 that are located above the upper surface of semiconductor substrate 11 may be removed (in some cases, portions of diffusion regions 15 that are located at the upper surface of semiconductor substrate 11 may also be removed). It will be understood by those skilled in the art that the planarization process may not remove these structures located above the upper surface of the semiconductor substrate 11, but simply planarize the upper surface of the already formed portion of the image sensor.
In the embodiment described above in connection with fig. 3A to 3D, the trench isolation structure of the image sensor is formed to include the high dielectric constant layer 16 covering the wall of the trench and the low light-transmitting layer 17 covering the high dielectric constant layer 16. Since the high-k layer 16 is formed of a high-k material, such a trench isolation structure is more advantageous in preventing out-diffusion of photogenerated carriers in the photodiode. Meanwhile, the high dielectric constant layer 16 covering the walls of the trench forms a hole layer in a portion of the semiconductor substrate 11 close to the high dielectric constant layer 16, which makes the trench isolation structure more resistant to diffusion of photogenerated carriers. In addition, both the hole layer and the diffusion region 15 can function to reduce or eliminate dark current, which enhances the effect of reducing or eliminating dark current. Such a trench isolation structure can also prevent crosstalk of light between photodiodes since the low-light-transmitting layer 17 is formed of a material having low light-transmitting property (for example, a dark material having a certain thickness).
In these embodiments, compared to the embodiments described in connection with fig. 1A to 1D, the finally formed trench isolation structure does not include the doped layer 13 having P-type dopants therein. Such a trench isolation structure can prevent the P-type dopant in doped layer 13 from continuing to diffuse into semiconductor substrate 11 again, i.e., from excessively diffusing, in an operation after diffusion region 15 has been formed.
A method of forming an image sensor according to one or more exemplary embodiments of the present disclosure is described below with reference to fig. 4A to 4D.
In some embodiments, as shown in fig. 4A, after thermally conductive layer 14 and doped layer 13 are removed as shown in fig. 3A, second oxide layer 18 is formed in trench 12 covering the walls of trench 12. Then, as shown in fig. 4B to 4D, after the second oxide layer 18 is formed, the high dielectric constant layer 16 covering the second oxide layer 18 and the low light-transmitting layer 17 covering the high dielectric constant layer 16 are formed in the trench 12, and then the upper surface of the image sensor of the portion which has been formed is subjected to planarization processing.
In these embodiments, a second oxide layer 18 is also formed between the semiconductor substrate 11 and the high dielectric constant layer 16. Since high dielectric constant layer 16 is typically formed of an oxide of a metal, such as hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or a combination thereof, second oxide layer 18 formed between semiconductor substrate 11 and high dielectric constant layer 16 may prevent metal contamination of semiconductor substrate 11 by high dielectric constant layer 16.
The diffusion region 15 may have a reduced effect of reducing or eliminating dark current due to the depletion of P-type dopants (e.g., boron) in the diffusion region 15, for example, as the process of forming oxide introduces a source of oxygen, which oxidizes the walls of the trench 12 and thereby affects the performance of the diffusion region 15 at the walls of the trench 12. In some embodiments, forming the second oxide layer 18 is performed at least by a low temperature atomic layer deposition (soft ALD) process. The low temperature atomic layer deposition process has a lower process temperature, so that the influence on the formed diffusion region 15 is less, the amount of the P-type dopant in the diffusion region 15 can be ensured, and the effect of reducing or eliminating dark current in the diffusion region is ensured. It will be understood by those skilled in the art that the second oxide layer 18 is formed "at least" by a low temperature atomic layer deposition process, meaning that the portion of the second oxide layer 18 proximate to the semiconductor substrate 11 needs to be formed by a low temperature atomic layer deposition process, while the portion of the second oxide layer 18 distal from the semiconductor substrate 11 is not limited, and may be formed by a low temperature atomic layer deposition process, as well as by other processes such as an Atomic Layer Deposition (ALD) process.
In the embodiment described above in connection with fig. 4A to 4D, the trench isolation structure of the image sensor is formed to include the second oxide layer 18 covering the wall of the trench, the high dielectric constant layer 16 covering the second oxide layer 18, and the low light-transmitting layer 17 covering the high dielectric constant layer 16. Among them, such a trench isolation structure can have the same advantageous effects as the trench isolation structure in the embodiment described above with reference to fig. 3A to 3D, due to the high dielectric constant layer 16 and the low light-transmitting layer 17. Also, in order not to affect the formation of the hole layer in the semiconductor substrate 11 by the high dielectric constant layer 16, the thickness of the second oxide layer 18 cannot be too large, for example, the thickness of the second oxide layer is not more than 50 angstroms. The thickness of the second oxide layer 18 herein refers to the dimension of the second oxide layer 18 in the longitudinal direction of the drawing at, for example, a portion covering the bottom wall of the trench 12, and the dimension of the second oxide layer 18 in the lateral direction of the drawing at, for example, a portion covering the side wall of the trench 12.
In the specification and claims, the word "a or B" includes "a and B" and "a or B" rather than exclusively including only "a" or only "B" unless specifically stated otherwise.
The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.
As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in a practical implementation.
In addition, the foregoing description may refer to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly connected. That is, to "couple" is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.
In addition, "first," "second," and like terms may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.
It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the present disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/setting," "installing/assembling," and/or "ordering" the object, and the like.
Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
In addition, embodiments of the present disclosure may also include the following examples:
1. a method of forming an image sensor, comprising:
forming a doped layer in a trench in a semiconductor substrate covering a wall of the trench, the doped layer having a P-type dopant and a concentration of the P-type dopant in the doped layer being higher than a concentration of the P-type dopant in a portion of the semiconductor substrate surrounding the trench;
forming a thermally conductive layer over the semiconductor substrate, the thermally conductive layer including a first portion located in the trench and covering the doped layer; and
heating the semiconductor substrate from above the semiconductor substrate, wherein the thermally conductive layer conducts heat through the first portion to the doped layer, thereby causing the P-type dopant in the doped layer to diffuse into the semiconductor substrate, thereby forming a P-type diffusion region at the walls of the trench in the semiconductor substrate.
2. The method of claim 1, wherein the thermally conductive layer further comprises a second portion overlying the semiconductor substrate and covering the upper surface of the semiconductor substrate, wherein the first portion and the second portion are continuous,
wherein heat treating the semiconductor substrate from above the semiconductor substrate comprises heat treating the second portion of the thermally conductive layer from above the semiconductor substrate.
3. The method of claim 1, wherein the thermally conductive layer comprises metallic tungsten.
4. The method of claim 3, further comprising:
forming an adhesion layer in the trench covering the doped layer after forming the doped layer and before forming the heat conductive layer,
wherein the heat conductive layer covers the adhesive layer.
5. The method according to 1, wherein the heating treatment is performed so that the temperature of the doped layer is not lower than 700 ℃.
6. The method of 1, wherein the heating treatment comprises one or more of: rapid thermal processing immersion annealing, rapid thermal processing spike annealing, laser annealing, and microwave annealing.
7. The method of 1, wherein the dielectric material having P-type dopants comprises one or more of: borosilicate glass, and boron oxide.
8. The method of claim 1, wherein the doped layer is formed by an atomic layer deposition process or a plasma enhanced chemical vapor deposition process.
9. The method of claim 1, wherein the doped layer has a thickness of less than 50 angstroms.
10. The method of claim 1, further comprising:
forming a first oxide layer in the trench covering the walls of the trench prior to forming the doped layer.
11. The method of claim 1, further comprising:
removing the heat conduction layer and the doping layer after the diffusion region is formed; and
a high dielectric constant layer is formed in the trench overlying the walls of the trench.
12. The method of claim 1, wherein removing the thermally conductive layer and the doped layer is performed by a wet etch process.
13. The method of claim 11, further comprising:
forming a second oxide layer in the trench covering walls of the trench after removing the thermally conductive layer and the doped layer and before forming the high dielectric constant layer,
wherein the high dielectric constant layer covers the second oxide layer.
14. The method of claim 13, wherein forming the second oxide layer is performed at least by a low temperature atomic layer deposition process.
15. The method of claim 13, wherein the second oxide layer has a thickness of no greater than 50 angstroms.
16. The method of claim 11, further comprising:
after the high dielectric constant layer is formed, a low light-transmitting layer covering the high dielectric constant layer is formed in the trench.
17. An image sensor, comprising:
a trench isolation structure formed in a semiconductor substrate; and
a diffusion region located around the trench isolation structure in the semiconductor substrate and covering the diffusion region, wherein the diffusion region has a P-type dopant and a concentration of the P-type dopant in the diffusion region is higher than a concentration of the P-type dopant in a portion of the semiconductor substrate located around the diffusion region,
wherein the trench isolation structure includes:
a high dielectric constant layer located at an outer layer portion of the trench isolation structure and covering the semiconductor substrate; and
and the low light transmission layer is positioned in the inner layer part of the trench isolation structure and covers the high dielectric constant layer.
18. The image sensor of claim 17, wherein the diffusion region has a thickness of 1nm to 50 nm.
19. The image sensor of claim 17, wherein the trench isolation structure further comprises:
an oxide layer located between the high dielectric constant layer and the semiconductor substrate.
20. The image sensor of claim 19, wherein the oxide layer has a thickness of no greater than 50 angstroms.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (16)
1. A method of forming an image sensor, comprising:
forming a doped layer in a trench in a semiconductor substrate covering a wall of the trench, the doped layer having a P-type dopant and a concentration of the P-type dopant in the doped layer being higher than a concentration of the P-type dopant in a portion of the semiconductor substrate surrounding the trench;
forming a thermally conductive layer over the semiconductor substrate, the thermally conductive layer including a first portion located in the trench and covering the doped layer; and
heating the semiconductor substrate from above the semiconductor substrate, wherein the thermally conductive layer conducts heat through the first portion to the doped layer, thereby causing the P-type dopant in the doped layer to diffuse into the semiconductor substrate, thereby forming a P-type diffusion region at the walls of the trench in the semiconductor substrate.
2. The method of claim 1, wherein the thermally conductive layer further comprises a second portion overlying the semiconductor substrate and covering the upper surface of the semiconductor substrate, wherein the first portion and the second portion are continuous,
wherein heat treating the semiconductor substrate from above the semiconductor substrate comprises heat treating the second portion of the thermally conductive layer from above the semiconductor substrate.
3. The method of claim 1, wherein the thermally conductive layer comprises metallic tungsten.
4. The method of claim 3, further comprising:
forming an adhesion layer in the trench covering the doped layer after forming the doped layer and before forming the heat conductive layer,
wherein the heat conductive layer covers the adhesive layer.
5. The method according to claim 1, wherein the heating treatment is performed so that the temperature of the doped layer is not lower than 700 ℃.
6. The method of claim 1, wherein the heating process comprises one or more of: rapid thermal processing immersion annealing, rapid thermal processing spike annealing, laser annealing, and microwave annealing.
7. The method of claim 1, wherein the dielectric material having P-type dopants comprises one or more of: borosilicate glass, and boron oxide.
8. The method of claim 1, wherein the doped layer is formed by an atomic layer deposition process or a plasma enhanced chemical vapor deposition process.
9. The method of claim 1, wherein the doped layer has a thickness of less than 50 angstroms.
10. The method of claim 1, further comprising:
forming a first oxide layer in the trench covering the walls of the trench prior to forming the doped layer.
11. The method of claim 1, further comprising:
removing the heat conduction layer and the doping layer after the diffusion region is formed; and
a high dielectric constant layer is formed in the trench overlying the walls of the trench.
12. The method of claim 1, wherein removing the thermally conductive layer and the doped layer is performed by a wet etch process.
13. The method of claim 11, further comprising:
forming a second oxide layer in the trench covering walls of the trench after removing the thermally conductive layer and the doped layer and before forming the high dielectric constant layer,
wherein the high dielectric constant layer covers the second oxide layer.
14. The method of claim 13, wherein forming the second oxide layer is performed by at least a low temperature atomic layer deposition process.
15. The method of claim 13, wherein the second oxide layer has a thickness of no more than 50 angstroms.
16. The method of claim 11, further comprising:
after the high dielectric constant layer is formed, a low light-transmitting layer covering the high dielectric constant layer is formed in the trench.
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| CN105552094A (en) * | 2014-10-27 | 2016-05-04 | 全视科技有限公司 | Pixel cell, imaging system and method for making optical isolation structure in pixel cell |
| CN108257995A (en) * | 2018-01-16 | 2018-07-06 | 德淮半导体有限公司 | Imaging sensor and the method for forming imaging sensor |
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| CN105552094A (en) * | 2014-10-27 | 2016-05-04 | 全视科技有限公司 | Pixel cell, imaging system and method for making optical isolation structure in pixel cell |
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