CN105977204B - 3D overall situation pixel unit and preparation method thereof - Google Patents
3D overall situation pixel unit and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 71
- 239000010703 silicon Substances 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000003860 storage Methods 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005070 sampling Methods 0.000 claims description 31
- 238000011049 filling Methods 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001914 filtration Methods 0.000 claims description 5
- 238000001459 lithography Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 55
- 230000000717 retained effect Effects 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000003287 optical effect Effects 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
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Abstract
The present invention provides a kind of 3D overall situation pixel units and preparation method thereof, and signal storage and reading circuit are made including the light sensitive diode made in the first silicon substrate layer and in the second silicon substrate layer；Light sensitive diode is stored with signal and is arranged on reading circuit vertical direction；The interconnection of light sensitive diode and signal storage and reading circuit is realized by the connection of through-hole；The present invention makes stereo-unit structure by using back-illuminated technique and 3D structure, in different level, and the perpendicular interconnection of signal storage and reading circuit and light sensitive diode may be implemented；To not only increase the extraneous light-path with light sensitive diode, the optical isolation degree of signal storage capacitance is improved, and reduce the occupied chip area of pixel unit.
Description
Technical field
The present invention relates to semiconductor image detection technology fields, and in particular to a kind of 3D 10T overall situation pixel unit and its system
Preparation Method.
Background technique
Traditional global shutter pixel technique is mainly used for ccd image sensor.It is continuous due to cmos image sensor
It is universal, and since machine vision, film making, industry, automobile and scanning application requirement must be captured quickly with high image quality
Mobile object, major imaging sensor manufacturer has been directed to overcome uses global shutter pixel on cmos image sensor
The traditional obstacle of the correlation of technology.Under this effort, provided global shutter pixel technique has smaller Pixel Dimensions, more
Big fill factor, lower dark current and lower noise passes so that cmos image sensor becomes CCD in more applications
The viable alternatives of sensor.
In the global pixel unit of conventional cmos image sensor, light sensitive diode and signal storage and reading circuit list
Component is done in the same plane.Storage unit needs to occupy biggish area to make the capacitor of storage signal, therefore complete
The area of office's pixel is difficult to reduce always, and fill factor is smaller always.Also, light sensitive diode, storage capacitance and reading circuit
It is easy to interfere with each other between three.
Summary of the invention
In order to overcome the above problems, the present invention is intended to provide a kind of global pixel unit of 3D structure and preparation method thereof,
Using back-illuminated technique and 3D structure, stereo-unit structure is made in different level, signal read circuit and photosensitive two may be implemented
The perpendicular interconnection of pole pipe.
In order to achieve the above object, it the present invention provides 3D overall situation pixel unit, is deposited including at least photosensitive region and signal
Storage and reading circuit region, the signal storage have signal storage and reading circuit (14) with reading circuit region；The sense
Light region stores with the signal and arranges in the vertical direction with reading circuit region；
The photosensitive region is set on the first silicon substrate layer (02) comprising:
Light sensitive diode (01) that first silicon substrate layer (02) back side is set gradually from top to bottom, anti-reflection coating
(04), color filtration layer (05) and lenticule (06) are provided in the light sensitive diode (01) two sides filled with dielectric
Isolated groove (03)；
The signal storage is set on the second silicon substrate layer (10) with reading circuit region comprising:
Second silicon substrate layer (10) back side is set gradually from the top down: the second dielectric layer (09), light shielding layer
(08) and the first dielectric layer (07)；
The front of second silicon substrate layer (10) is from bottom to top successively are as follows: signal storage and reading circuit (14) are located at
The signal is stored in the third dielectric layer (15) above reading circuit (14) and is located above third dielectric layer (15)
Metal layer (M)；Wherein,
The light sensitive diode (01) stores with the signal to be connected between reading circuit (14) by through-hole (12), institute
The one end for stating through-hole (12) connects the light sensitive diode (01), the through-hole (12) pass through first dielectric layer (07),
The light shielding layer (08), second dielectric layer (09) and second silicon substrate layer (10), so that the through-hole (12)
The other end connect signal storage and reading circuit (14), also, the side wall of the through-hole (12) has the 4th dielectric
Layer (13)；
The third dielectric layer (15) stores between reading circuit (14) and the metal layer (M) for the signal
Isolation；There is contact hole (CT) in the third dielectric layer (15)；The signal storage is with reading circuit (14) by connecing
Contact hole (CT) and the metal layer (M), which are realized, to be interconnected.
Preferably, the signal storage and reading circuit (14) include: reset switch, the first sampling capacitance, the second sampling
Capacitor, transfer tube, the first source follower, preliminary filling fulgurite, first switch tube, second switch, third switching tube, the 4th switch
Pipe, the second source follower, row selector；The drain electrode of the reset switch connects resetting voltage, and the grid of the reset switch connects picture
Plain input terminal, the source electrode of the reset switch connect the source electrode of transfer tube, the drain electrode of the transfer tube and pinned photodiode
Cathode is connected, and the grid of the transfer tube is connected with pixel unit input terminal；The drain electrode of first source follower meets VDD, and described
The source electrode of one source follower is connected with the drain electrode of charger, and the source electrode ground connection of the charger, the grid of the charger connects picture
Plain input terminal；The drain electrode of the source electrode of first source follower and the preliminary filling fulgurite to drain with the first switch tube,
The drain electrode of the second switch is connected, the drain electrode of the source electrode of the first switch tube and first sampling capacitance, described the
The drain electrode of three switching tubes is connected, the source electrode of the second switch and first sampling capacitance and the 4th switching tube phase
Even, the source electrode of the 4th switching tube is connected with the grid of the source electrode of the third switching tube and second source follower,
The source electrode of second source follower is connected with the drain electrode of the row selector；The grid of the preliminary filling fulgurite is that pixel unit is defeated
Enter end, the first switch tube, the second switch, the third switching tube and the 4th switching tube grid respectively with
Pixel unit input terminal is connected, the other end ground connection of the other end of first sampling capacitance and second sampling capacitance；
The drain electrode of second source follower is connected with VDD, and the grid of the row selector is pixel unit input terminal, the row selection
Output end of the source electrode of device as entire pixel unit.
Preferably, the material of first dielectric layer and second dielectric layer is insulating materials.
Preferably, the material of first dielectric layer and second dielectric layer is silica.
Preferably, the material of the silicon substrate is monocrystalline silicon.
In order to achieve the above object, the present invention also provides a kind of preparation method of above-mentioned 3D overall situation pixel unit,
Include:
Step 01: being sequentially depositing first dielectric layer, the light shielding layer, institute in first silicon substrate layer front
State the second dielectric layer and second silicon substrate layer；
Step 02: being situated between in second silicon substrate layer, second dielectric layer, the light shielding layer, first electricity
The through-hole is formed in matter layer and the first silicon substrate layer, the bottom of the through-hole is inserted into first silicon substrate layer；
Step 03: forming the 4th dielectric layer in the through-hole side wall, and fill metal in the through-hole；
Step 04: preparing the signal storage and reading circuit in second silicon substrate layer front；
Step 05: forming the third dielectric layer in second silicon substrate layer front for completing the step 04；
Step 06: the contact hole is prepared in the third dielectric layer, and in the contact hole surface and institute
It states third dielectric layer surface and forms the metal layer；
Step 07: first silicon substrate layer back side is thinned；
Step 08: form the light sensitive diode in first silicon substrate layer back side, make the light sensitive diode with
The through-hole is connected, and forms the isolated groove being located at around the light sensitive diode, and in the isolated groove
Filling dielectric；
Step 09: sequentially forming anti-reflecting layer, the color on the isolated groove surface and the light sensitive diode surface
Color filter layer and the lenticule.
Preferably, in the step 04, prepared signal storage and reading circuit include: reset switch, and first
Sampling capacitance, the second sampling capacitance, transfer tube, the first source follower, preliminary filling fulgurite, first switch tube, second switch, third
Switching tube, the 4th switching tube, the second source follower, row selector；The drain electrode of the reset switch connects resetting voltage, the reset
The grid of switch connects pixel input terminal, and the source electrode of the reset switch connects the source electrode of transfer tube, the drain electrode of the transfer tube and nail
The cathode of pinned photodiode is connected, and the grid of the transfer tube is connected with pixel unit input terminal；The leakage of first source follower
Pole meets VDD, and the source electrode of first source follower is connected with the drain electrode of charger, the source electrode ground connection of the charger, described to fill
The grid of electric appliance connects pixel input terminal；The drain electrode of the source electrode of first source follower and the preliminary filling fulgurite and described first
The drain electrode of switching tube, the drain electrode of the second switch are connected, the source electrode of the first switch tube and first sampling capacitance
Drain electrode, the third switching tube drain electrode be connected, the source electrode of the second switch and first sampling capacitance and described
4th switching tube is connected, the source electrode of the 4th switching tube and the source electrode of the third switching tube and second source follower
Grid be connected, the source electrode of second source follower is connected with the drain electrode of the row selector；The grid of the preliminary filling fulgurite
For pixel unit input terminal, the first switch tube, the second switch, the third switching tube and the 4th switching tube
Grid be connected respectively with pixel unit input terminal, the other end of first sampling capacitance and second sampling capacitance
Other end ground connection；The drain electrode of second source follower is connected with VDD, and the grid of the row selector is pixel unit input
End, output end of the source electrode of the row selector as entire pixel unit.
Preferably, in the step 01, the preparation of first dielectric layer and second dielectric layer is all made of heat
Oxidation technology.
Preferably, in the step 01, the preparation of the light shielding layer uses Damascus technics.
Preferably, the step 03 specifically includes:
Step 031: being situated between in the via bottoms and side wall and second silicon substrate layer surface deposition the 4th electricity
Matter layer；
Step 032: using lithography and etching technique, etching removes the via bottoms and second silicon substrate layer surface
The 4th dielectric layer, retain the 4th dielectric layer of the through-hole side wall；
Step 033: in the through-hole successively plating seed layer and filling metal.
Global pixel unit of 3D structure of the invention and preparation method thereof, by using back-illuminated technique and 3D structure,
Different level makes stereo-unit structure, and the perpendicular interconnection of signal read circuit and light sensitive diode may be implemented；To not only
The extraneous light-path with light sensitive diode is improved, improves the optical isolation degree of signal storage capacitance, and reduce pixel list
The occupied chip area of member.
Detailed description of the invention
Fig. 1 is the cross section structure schematic diagram of the 3D overall situation pixel unit of a preferred embodiment of the invention
Fig. 2 is the electrical block diagram of the 3D overall situation pixel unit of a preferred embodiment of the invention
Fig. 3 is the flow diagram of the preparation method of the 3D overall situation pixel unit of a preferred embodiment of the invention
Fig. 4-12 is that each step of the preparation method of the 3D overall situation pixel unit of a preferred embodiment of the invention is shown
It is intended to
Specific embodiment
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, general replacement known to those skilled in the art
It is included within the scope of protection of the present invention.
3D overall situation pixel unit of the invention is at least by the photosensitive region that makes in the first silicon substrate layer and in the second silicon
The signal made on substrate layer, which is stored, combines composition with reading circuit region；Photosensitive region is located at signal storage and reading circuit area
Above domain；Photosensitive region has the light sensitive diode positioned at the first silicon substrate layer, and signal storage has with reading circuit unit area
There are the signal storage positioned at the second silicon substrate layer and reading circuit, light sensitive diode is located at signal storage and reading circuit top；
The interconnection of light sensitive diode and signal storage and reading circuit is realized by through-hole.
It should be noted that present invention could apply in 10T or 8T overall situation pixel unit.
Below in conjunction with attached drawing 1-12 and specific embodiment, invention is further described in detail.It should be noted that attached drawing
It is all made of very simplified form, using non-accurate ratio, and only to facilitate, clearly reach aid illustration the present embodiment
Purpose.
In the present embodiment, referring to Fig. 1,3D 10T overall situation pixel unit, includes at least: positioned at the sense of the first silicon substrate layer
Light region (in Fig. 1 upper dotted line frame) and 10T signal storage positioned at the second silicon substrate layer and reading circuit region (lower void in Fig. 1
Wire frame)；Photosensitive region is stored with 10T signal and is arranged in the vertical direction with reading circuit region；
Photosensitive region is set in the first silicon substrate layer 02 comprising: 02 back side of the first silicon substrate is successively set from top to bottom
Light sensitive diode 01, anti-reflection coating 04, color filtration layer 05 and the lenticule 06 set are arranged in 01 two sides of light sensitive diode
Have filled with dielectric isolated groove 03；
The storage of 10T signal is set in the second silicon substrate layer 10 with reading circuit region comprising: the second silicon substrate layer 10
The back side is from the top down successively are as follows: the second dielectric layer 09, light shielding layer 08 and the first dielectric layer 07；Second silicon substrate layer
10 front is from bottom to top successively are as follows: the storage of 10T signal is stored in above reading circuit 14 with reading circuit 14, positioned at signal
Third dielectric layer 15 and the metal layer M above third dielectric layer 15；Here metal layer M is can be with post-channel interconnection
Metal layer；
Light sensitive diode 01 is stored with 10T signal to be connected between reading circuit 14 by through-hole 12, one end of through-hole 12
Light sensitive diode 01 is connected, through-hole 12 passes through the first dielectric layer 07, light shielding layer 08, the second dielectric layer 09 and the second silicon lining
Bottom 10, so that other end connection 10T signal storage and the reading circuit unit 14 of through-hole 12, also, the side wall of through-hole 12 has
4th dielectric layer 13；
Third dielectric layer 15 stores and being isolated between reading circuit 14 and metal layer M for 10T signal；Third electricity is situated between
There is contact hole CT in matter layer 15；The storage of 10T signal is realized with reading circuit 14 by the contact hole CT and metal layer M mutual
Even；Here, further includes: the active and passive region 11 positioned at 10 back side of the second silicon substrate layer.Preferably, 07 He of the first dielectric layer
The material of second dielectric layer 09 is insulating materials, such as oxide, and the active active area with passive region 11 is p-type doping
Active area.Through-hole 12 can be using the production of through-silicon-via (Through Silicon Via) technique.
In the present embodiment, referring to Fig. 2, the storage of 10T signal includes: reset switch M1, the first sampling with reading circuit 14
Capacitor C1, the second sampling capacitance C2, transfer tube M2, the first source follower SF1 (M3), preliminary filling fulgurite M4, first switch tube M5, the
Two switching tube M6, the third switching tube source follower SF2 of M7, the 4th switching tube M8, second (M9), row selector M10；Reset switch
The drain electrode of M1 meets resetting voltage Vreset, and the grid of reset switch M1 meets pixel input terminal RX, and the source electrode of reset switch M1 connects biography
The source electrode (FD node) of defeated pipe M2, the drain electrode of transfer tube M2 is connected with the cathode of light sensitive diode, the grid and picture of transfer tube M2
Plain unit input terminal TG is connected；The drain electrode of first source follower SF1 (M3) meets VDD, the source electrode of the first source follower SF1 (M3) with
The drain electrode of preliminary filling fulgurite M4 is connected, and the source electrode ground connection of preliminary filling fulgurite M4, the grid of preliminary filling fulgurite M4 meets pixel input terminal PC；First
The drain electrode of the source electrode and preliminary filling fulgurite M4 of source follower SF1 (M3) and the drain electrode of first switch tube M5, second switch M6
Drain electrode is connected, and the source electrode of first switch tube M5 is connected with the drain electrode of the first sampling capacitance C1, the drain electrode of third switching tube M7, and second
The source electrode of switching tube M6 is connected with the first sampling capacitance C1 and the 4th switching tube M8, and the source electrode and third of the 4th switching tube M8 switchs
The grid of the source electrode of pipe M7 and the second source follower SF2 (M9) are connected, and the source electrode and row of the second source follower SF2 (M9) selects
The drain electrode of device M10 is connected；The grid of preliminary filling fulgurite M4 be pixel unit input terminal PC, first switch tube M5, second switch M6,
The grid of third switching tube M7 and the 4th switching tube M8 are connected with pixel unit input terminal S1, S2, S3, S4 respectively, the first sampling
The other end of capacitor C1 is grounded and the other end of the second sampling capacitance C2 ground connection；The drain electrode of second source follower SF2 (M9) with
VDD is connected, and the grid of row selector M10 is pixel unit input terminal RS, and the source electrode of row selector M10 is as entire pixel unit
Output end.By the first, second, third and fourth switching tube according to certain timing, reset switch and transfer tube are distinguished
It is stored on the first, second sampling capacitance, the signal voltage obtained in the time for exposure is stored in pixel unit by final realize
A period of time reads again, to realize the global shutter exposure of entire pixel unit array.
Referring to Fig. 3, in the present embodiment, the preparation method of above-mentioned 3D overall situation pixel unit, comprising:
Step 01: referring to Fig. 4, being sequentially depositing the first dielectric layer 07, light shielding layer in 02 front of the first silicon substrate layer
08, the second dielectric layer 09 and the second silicon substrate layer 10；
Specifically, the first dielectric layer 07 and the second dielectric layer 09 can be prepared using thermal oxidation technology；It can adopt
Light shielding layer 08 is prepared with Damascus technics；The preparation of second silicon substrate layer 10 can use silicon epitaxy process.
Step 02: referring to Fig. 5, being situated between in the second silicon substrate layer 10, the second dielectric layer 09, the 08, first electricity of light shielding layer
Through-hole 12 is formed in matter layer 07 and the first silicon substrate layer 02, the bottom of through-hole 12 is inserted into the first silicon substrate layer 02；
Specifically, etching through-hole 12 using through-silicon-via (Through Silicon Via) technique.
Step 03: referring to Fig. 6, forming the 4th dielectric layer 13 in 12 side wall of through-hole, and gold is filled in through-hole 12
Belong to；
Specifically, including:
Step 031: depositing the 4th dielectric layer 13 in 12 bottom and side wall of through-hole and 10 surface of the second silicon substrate layer；
Step 032: use lithography and etching technique, the of etching removal 12 bottom of through-hole and 10 surface of the second silicon substrate layer
Four dielectric layers 13 retain the 4th dielectric layer 13 of 12 side wall of through-hole；
Step 033: in through-hole 12 successively plating seed layer and filling metal.
Step 04: referring to Fig. 7, preparing the above-mentioned storage of 10T signal and reading circuit in 10 front of the second silicon substrate layer
14；
Specifically, total is inverted, formed in 10 front of the second silicon substrate layer it is active with passive region 11, such as using from
Son injection forms p-type doping active area；
Step 05: referring to Fig. 8, forming third dielectric layer 15 in 10 front of the second silicon substrate layer for completing step 04；
Specifically, can be, but not limited to prepare third dielectric layer using thermal oxidation technology or chemical vapor deposition process
15；
Step 06: referring to Fig. 9, preparing contact hole CT in third dielectric layer 15, and on the surface contact hole CT
With 15 forming metal layer on surface M of third dielectric layer；
Specifically, preparing contact hole CT through lithography and etching technique, the storage of 10T signal and reading circuit 14 and gold are completed
Belong to the production of the line and contact block (pad) of layer M.
Step 07: referring to Fig. 10,02 back side of the first silicon substrate layer is thinned；
Step 08: please referring to Figure 11, light sensitive diode 01 is formed in 02 back side of the first silicon substrate layer, so that photosensitive two pole
Pipe 01 is connected with through-hole 12, and forms the isolated groove 03 being located at around light sensitive diode 01, and in isolated groove 03
Interior filling dielectric；
Specifically, light sensitive diode 01 can use light sensitive diode here；Make 02 back side of the first silicon substrate layer upward,
N-type ion injection is carried out in first silicon substrate layer 02, ion implanting certain depth is prepared to 02 front of the first silicon substrate layer
Light sensitive diode 01 carries out lithography and etching around light sensitive diode 01 and forms isolated groove 03, then can with but it is unlimited
In using chemical vapor deposition process filling dielectric in isolated groove 03；
Step 09: please referring to Figure 12, form anti-reflecting layer 04, color on 03 surface of isolated groove and 01 surface of light sensitive diode
Color filter layer 05 and lenticule 06；
Specifically, can be, but not limited to apply at 02 back side of the first silicon substrate layer and 03 surface of isolated groove of completing step 08
It covers or deposits anti-reflecting layer 04, the preparation of color filtration layer 05 and lenticule 06 is then sequentially formed on 04 surface of anti-reflecting layer,
This step can use common process, and which is not described herein again.
Although the present invention is disclosed as above with preferred embodiment, the right embodiment illustrate only for the purposes of explanation and
, it is not intended to limit the invention, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection scope that the present invention is advocated should be subject to described in claims.
Claims (9)
1. a kind of 3D overall situation pixel unit, includes at least photosensitive region and signal storage and reading circuit region, the signal are deposited
Storage has signal storage and reading circuit (14) with reading circuit region；It is characterized in that, the photosensitive region and the signal
Storage is arranged in the vertical direction with reading circuit region；
The photosensitive region is set on the first silicon substrate layer (02) comprising:
Light sensitive diode (01) that first silicon substrate layer (02) back side is set gradually from top to bottom, anti-reflection coating (04),
Color filtration layer (05) and lenticule (06) are provided in the light sensitive diode (01) two sides filled with dielectric isolating trenches
Slot (03)；
The signal storage is set on the second silicon substrate layer (10) with reading circuit region comprising:
Second silicon substrate layer (10) back side is set gradually from the top down: the second dielectric layer (09), light shielding layer (08),
And first dielectric layer (07)；
The front of second silicon substrate layer (10) is from bottom to top successively are as follows: signal storage and reading circuit (14), be located at it is described
Signal storage and the third dielectric layer (15) above reading circuit (14) and the gold being located above third dielectric layer (15)
Belong to layer (M)；Wherein,
The light sensitive diode (01) stores with the signal to be connected between reading circuit (14) by through-hole (12), described logical
The one end in hole (12) connects the light sensitive diode (01), and the through-hole (12) passes through first dielectric layer (07), described
Light shielding layer (08), second dielectric layer (09) and second silicon substrate layer (10), so that the through-hole (12) is another
One end connects the signal storage and reading circuit (14), also, the side wall of the through-hole (12) has the 4th dielectric layer
(13)；
The third dielectric layer (15) for the signal store and reading circuit (14) and the metal layer (M) between every
From；There is contact hole (CT) in the third dielectric layer (15)；The signal storage passes through contact hole with reading circuit (14)
(CT) it realizes and interconnects with the metal layer (M)；
Wherein, the signal storage and reading circuit (14) include: reset switch, the first sampling capacitance, the second sampling capacitance, biography
Defeated pipe, the first source follower, preliminary filling fulgurite, first switch tube, second switch, third switching tube, the 4th switching tube, the second source
Follower, row selector；The drain electrode of the reset switch connects resetting voltage, and the grid of the reset switch connects pixel input terminal,
The source electrode of the reset switch connects the source electrode of transfer tube, and the drain electrode of the transfer tube is connected with the cathode of pinned photodiode,
The grid of the transfer tube is connected with pixel unit input terminal；The drain electrode of first source follower connects VDD, first source follower
Source electrode be connected with the drain electrode of charger, the source electrode of charger ground connection, the grid of the charger connects pixel input terminal；Institute
State the drain electrode of the source electrode and the preliminary filling fulgurite of the first source follower and drain electrode, the second switch of the first switch tube
The drain electrode of pipe is connected, the source electrode of the first switch tube and the drain electrode of first sampling capacitance, the leakage of the third switching tube
Extremely it is connected, the source electrode of the second switch is connected with first sampling capacitance and the 4th switching tube, and the described 4th opens
The source electrode for closing pipe is connected with the grid of the source electrode of the third switching tube and second source follower, and second source follows
The source electrode of device is connected with the drain electrode of the row selector；The grid of the preliminary filling fulgurite be pixel unit input terminal, described first
Switching tube, the second switch, the third switching tube and the 4th switching tube grid inputted respectively with pixel unit
End is connected, the other end ground connection of the other end of first sampling capacitance and second sampling capacitance；Second source with
It is connected with the drain electrode of device with VDD, the grid of the row selector is pixel unit input terminal, the source electrode conduct of the row selector
The output end of entire pixel unit.
2. 3D overall situation pixel unit according to claim 1, which is characterized in that first dielectric layer and described second
The material of dielectric layer is insulating materials.
3. 3D overall situation pixel unit according to claim 2, which is characterized in that first dielectric layer and described second
The material of dielectric layer is silica.
4. 3D overall situation pixel unit according to claim 1, which is characterized in that the material of the silicon substrate is monocrystalline silicon.
5. a kind of preparation method of 3D overall situation pixel unit described in claim 1 characterized by comprising
Step 01: being sequentially depositing first dielectric layer, the light shielding layer, described in first silicon substrate layer front
Two dielectric layers and second silicon substrate layer；
Step 02: in second silicon substrate layer, second dielectric layer, the light shielding layer, first dielectric layer
With form the through-hole in the first silicon substrate layer, the bottom of the through-hole is inserted into first silicon substrate layer；
Step 03: forming the 4th dielectric layer in the through-hole side wall, and fill metal in the through-hole；
Step 04: preparing the signal storage and reading circuit in second silicon substrate layer front；
Step 05: forming the third dielectric layer in second silicon substrate layer front for completing the step 04；
Step 06: the contact hole is prepared in the third dielectric layer, and in the contact hole surface and described
Three dielectric layer surfaces form the metal layer；
Step 07: first silicon substrate layer back side is thinned；
Step 08: form the light sensitive diode in first silicon substrate layer back side, make the light sensitive diode with it is described
Through-hole is connected, and forms the isolated groove being located at around the light sensitive diode, and fill in the isolated groove
Dielectric；
Step 09: sequentially forming anti-reflecting layer, the color mistake on the isolated groove surface and the light sensitive diode surface
Filtering layer and the lenticule.
6. preparation method according to claim 5, which is characterized in that in the step 04, the prepared signal is deposited
Storage and reading circuit include: reset switch, the first sampling capacitance, the second sampling capacitance, transfer tube, the first source follower, preliminary filling
Fulgurite, first switch tube, second switch, third switching tube, the 4th switching tube, the second source follower, row selector；It is described multiple
The drain electrode of bit switch connects resetting voltage, and the grid of the reset switch connects pixel input terminal, and the source electrode of the reset switch connects biography
The source electrode of defeated pipe, the drain electrode of the transfer tube are connected with the cathode of pinned photodiode, the grid and pixel of the transfer tube
Unit input terminal is connected；The drain electrode of first source follower connects VDD, the drain electrode phase of the source electrode and charger of first source follower
Even, the source electrode ground connection of the charger, the grid of the charger connect pixel input terminal；The source electrode of first source follower with
And the drain electrode of the preliminary filling fulgurite is connected with the drain electrode of the first switch tube, the drain electrode of the second switch, described first
The source electrode of switching tube is connected with the drain electrode of first sampling capacitance, the drain electrode of the third switching tube, the second switch
Source electrode be connected with first sampling capacitance and the 4th switching tube, the source electrode of the 4th switching tube is opened with the third
The grid of the source electrode and second source follower that close pipe is connected, the source electrode and the row selector of second source follower
Drain electrode be connected；The grid of the preliminary filling fulgurite be pixel unit input terminal, the first switch tube, the second switch,
The grid of the third switching tube and the 4th switching tube is connected with pixel unit input terminal respectively, first sampling capacitance
The other end and second sampling capacitance the other end ground connection；The drain electrode of second source follower is connected with VDD, described
The grid of row selector is pixel unit input terminal, output end of the source electrode of the row selector as entire pixel unit.
7. preparation method according to claim 5, which is characterized in that in the step 01, first dielectric layer and
The preparation of second dielectric layer is all made of thermal oxidation technology.
8. preparation method according to claim 5, which is characterized in that in the step 01, the preparation of the light shielding layer
Using Damascus technics.
9. preparation method according to claim 5, which is characterized in that the step 03 specifically includes:
Step 031: depositing the 4th dielectric in the via bottoms and side wall and second silicon substrate layer surface
Layer；
Step 032: using lithography and etching technique, the institute of etching the removal via bottoms and second silicon substrate layer surface
The 4th dielectric layer is stated, the 4th dielectric layer of the through-hole side wall is retained；
Step 033: in the through-hole successively plating seed layer and filling metal.
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