CN105959011B - A kind of segment delay ring moulds number converter - Google Patents
A kind of segment delay ring moulds number converter Download PDFInfo
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- CN105959011B CN105959011B CN201610422490.3A CN201610422490A CN105959011B CN 105959011 B CN105959011 B CN 105959011B CN 201610422490 A CN201610422490 A CN 201610422490A CN 105959011 B CN105959011 B CN 105959011B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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Abstract
The invention discloses a kind of segment delay ring moulds number converter, a high position for the analog-digital converter is designed using piece-wise linearization, and low level is using delay ring structure, and digit precision is 6 in total；The analog-digital converter includes that the range of input voltage is divided into four voltage piecewise intervals by sample code module, ring retard conversion modulus module, reference voltage adjustment module and segmentation comparison module, the reference voltage being segmented in comparison module；Segmentation comparison module carries out analog-to-digital conversion to input voltage according to four voltage piecewise intervals and obtains high two binary code B1 B2, ring retard analog-to-digital conversion module is respectively adjusted the delay line length of four voltage piecewise intervals according to B1 B2, reference voltage adjustment module is respectively adjusted the reference voltage of four voltage piecewise intervals according to B1 B2, and ring retard analog-to-digital conversion module combination delay line length and reference voltage carry out analog-to-digital conversion to input voltage and obtain low tetrad code B3 B4 B5 B6.The present invention has taken into account the advantages of piece-wise linearization design and delay ring structure.
Description
Technical field
The present invention relates to a kind of segment delay ring moulds number converter, belong to the analog-digital converter skill in IC design
Art.
Background technique
Delaying type ADC is compared with the Window-type ADC obtained is improved on the basis of simulating ADC structure, this novel
ADC is made of digital building blocks, and in digital switch power supply with greater advantage: power consumption is lower, and area is smaller, stronger
Antinoise anti-interference ability can be realized, Ke Yiyong independent of accurate analog device with the digital logic unit of standard
Hardware description language is designed.One distinct disadvantage of this structure is exactly that output accuracy is influenced by technique, temperature etc.,
So some additional support circuits is needed to proofread export structure.In addition, the supply voltage of delaying type ADC is exactly to count
The output voltage of the output voltage of word switch power supply, i.e. digital switch power supply is exactly the input voltage of ADC, this voltage is general
It is different with the supply voltage that is required in digital technology, so in level transmission process, it is also contemplated that level difference is brought
Adverse effect.Above-mentioned two aspect is the most significant disadvantage of delaying type ADC, limits to apply in digital switch power supply and prolong
The convenience of slow type ADC.Delay line type ADC is to convert digital quantity for analog output voltage by the structure of delay line, according to
The delay time of delay cell and the inversely proportional relationship of supply voltage are right by propagation of the input pulse signal on delay chain
Different nodes collect corresponding transmission voltage swing, generally high level and low level on delay chain, to obtain number
Amount.This structure is a little digital design, greatly reduce circuit overall power and loop compensation brought by it is multiple
Miscellaneous degree.
Summary of the invention
Goal of the invention: in order to overcome the deficiencies in the prior art, the present invention provides a kind of segment delay ring modulus turn
Parallel operation, can be improved the precision and transfer efficiency of delay type analog-to-digital converter, while can take into account the property of section and ring retard
It can advantage.
Technical solution: to achieve the above object, the technical solution adopted by the present invention are as follows:
A high position for a kind of segment delay ring moulds number converter, the analog-digital converter is designed using piece-wise linearization, and low level is adopted
With delay ring structure, digit precision is 6 in total；The analog-digital converter includes sample code module, ring retard modulus of conversion digital-to-analogue
Block, reference voltage adjustment module and segmentation comparison module, are segmented reference voltage V1, V2 and V3 in comparison module for input voltage
The range of Vsence is divided into four voltage piecewise intervals [V0, V1], [V1, V2], [V2, V3] and [V3, V4], wherein V0 and V4
The respectively lower and upper limit of input voltage Vsence, V0 < V1 < V2 < V3 < V4；Comparison module is segmented according to four voltages
Piecewise interval carries out analog-to-digital conversion to input voltage Vsence and obtains high two binary codes B1 and B2, ring retard analog-to-digital conversion
Module is respectively adjusted the delay line length of four voltage piecewise intervals according to high two binary codes B1 and B2, with reference to electricity
Pressure adjustment module is respectively adjusted the reference voltage of four voltage piecewise intervals according to high two binary codes B1 and B2, prolongs
Slow ring modulus conversion module combines the delay line length of each voltage piecewise interval and reference voltage to be segmented respectively in four voltages
Analog-to-digital conversion is carried out to input voltage Vsence in section and obtains low tetrad code B3, B4, B5 and B6.
In above scheme, after high two binary codes B1 and B2 has been determined, Gao Liangwei binary code B1 and B2 will make
Be maintained at for final binary system highest order segmentation comparison module in, until input voltage Vsence change and departing from
Current voltage piecewise interval.The reference voltage of four voltage piecewise intervals is determining according to high two binary codes B1 and B2, if
High two binary codes B1 and B2 are remained unchanged, then the reference voltage of four voltage piecewise intervals also remains unchanged.
When input voltage Vsence changes in smaller range, the voltage characteristic of delay cell can approximation regard line as
Property；But when input voltage Vsence changes in a big way, the voltage characteristic linearity of delay cell is not just very
Gao Liao.In the above scheme, the range of input voltage Vsence is divided into several lesser voltage piecewise intervals by us, every
Input voltage Vsence is converted into binary digit amount in a voltage piecewise interval, has been considerably improved entire analog-digital converter
The linearity.By the thinner of the range division of input voltage Vsence, the linearity of entire analog-digital converter is higher；If but dividing
Must be too thin, corresponding circuit is realized will be excessively complicated；So comprehensively considering the complexity and entire analog-to-digital conversion of circuit realization
The factors such as the conversion accuracy of device, the range of input voltage Vsence is divided into four voltage piecewise intervals by us, corresponding
Binary coding is B1 and B2.
Specifically, the control signal of the ring retard conversion modulus module is generated by the inside of the analog-digital converter, delay
Ring convert modulus module control signal and enable signal enable respectively as nor gate two input signals, NOT gate it is defeated
The introducing of input voltage Vsence is controlled out.Since the control signal of ring retard conversion modulus module is by the analog-digital converter
What inside generated, therefore additional control signal generating circuit is not needed, and the internal control signal generated is by same
The influence of the factors such as temperature, technique, load, therefore can suitably offset the delay distortion of ring retard conversion modulus module.
Specifically, the ring retard conversion modulus module includes delay chain, with reference to delay chain and AD conversion unit three
Part, delay of the delay chain for step signal are transmitted to obtain the corresponding delaying state of different voltages, are used for reference to delay chain
The delayed-action of sampled signal, AD conversion unit are used to convert digital code for delaying state；Delay chain and refer to delay chain
Corresponding four voltage piecewise intervals are respectively divided between four sections, adjacent two sections to be connected by two distributors, and each two
Distributor by high two binary codes B1 and B2 determine the preceding paragraph output signal be output to next section or directly it is defeated
AD conversion unit group is arrived out.
The utility model has the advantages that segment delay ring moulds number converter provided by the invention, by the way of two-stage conversion, at the same it is simultaneous
The advantages of having cared for segment design and time delay ring: 1, since the control signal of ring retard conversion modulus module is by the analog-to-digital conversion
What the inside of device generated, therefore additional control signal generating circuit is not needed, and the internal control signal generated is by same
The influence of the factors such as temperature, technique, the load of sample, thus can suitably offset ring retard conversion modulus module delay distortion 2,
When input voltage Vsence changes in smaller range, the voltage characteristic of delay cell approximate can be seen linear；I
The range of input voltage Vsence is divided into several lesser voltage piecewise intervals, will be defeated in each voltage piecewise interval
Enter voltage Vsence and be converted into binary digit amount, so that it may substantially increase the linearity of entire analog-digital converter；3, two-stage
In switch power supply system transient response or starting establishment process, the variation range of output voltage can exceed the amount of window for conversion
Change range, the output of entire analog-digital converter at this time is full 0 or complete 1, can system quickly be established, keep output voltage fast
Speed can reflect close to window quantization range, the situation of change of this output voltage being segmented relatively high two output valves；
And when output voltage reaches stable, system can reach a stable state, and entire analog-digital converter only needs the window in a very little
Mouth carries out detection conversion to output voltage, and high two general constant, to improve the transformation efficiency of entire analog-digital converter.
Detailed description of the invention
Fig. 1 is segment delay ring modulus transformer work flow figure of the invention；
Fig. 2 is existing basic delaying type analog-digital converter structure figure；
Fig. 3 is segment delay ring modulus converter circuit schematic diagram of the invention；
Fig. 4 is that comparison module schematic diagram is segmented in the present invention；
Fig. 5 is that reference voltage adjusts module principle figure in the present invention；
Fig. 6 is the simulation result of segment delay ring moulds number converter of the invention.
Specific embodiment
The present invention will be further explained with reference to the accompanying drawing.
The range of input voltage Vsence is divided into four voltages by reference voltage V1, V2 and V3 in segmentation comparison module
Piecewise interval [V0, V1], [V1, V2], [V2, V3] and [V3, V4], wherein V0 and V4 is respectively under input voltage Vsence
Limit and the upper limit, V0 < V1 < V2 < V3 < V4.As shown in figure 3, segmentation comparison module is according to four voltage piecewise intervals to input
Voltage Vsence progress analog-to-digital conversion, which obtains high two binary codes B1B2, B1B2, to protect as final binary system highest order
It holds in segmentation comparison module, until input voltage Vsence changes and departing from current voltage piecewise interval.Delay
Ring modulus conversion module is respectively adjusted the delay line length of four voltage piecewise intervals according to B1B2, reference voltage adjustment
Module is respectively adjusted the reference voltage of four voltage piecewise intervals according to B1B2, and ring retard analog-to-digital conversion module combines each
The delay line length and reference voltage of a voltage piecewise interval are respectively in four voltage piecewise intervals to input voltage Vsence
It carries out analog-to-digital conversion and obtains low tetrad code B3B4B5B6.
Ring retard conversion modulus module still utilize delay cell delay time and delay cell supply voltage at anti-
The principle of the relationship of ratio designs, and as seen from Figure 3, ring retard conversion modulus module includes delay chain, with reference to delay chain and modulus turn
Change three parts of unit group.For following reference delay chain as sampled signal generation circuit, output is adopting for rising edge sampling
The supply voltage of sample signal, corresponding delay cell is reference level.Delay chain above forms cyclic annular knot by a nor gate
Structure, ring retard convert modulus module control signal and enable signal enable respectively as nor gate two input signals,
The introducing of the output control input voltage Vsence of NOT gate.The supply voltage of corresponding delay cell is input voltage Vsence, when
When enable signal enable is 1, then the output of nor gate is 0, then it is 0 that all delay cells (B-sample, B-A) are all clear；When
When enable signal enable jump is 0, since the signal at A is also 0, the output of nor gate is 1, the step that this 0 jump is 1
Signal will transmit backward in upper and lower two delay chains, when there is 0 to 1 jump step signal in sample signal, Jiu Huitong
Over-sampling circuit samples master delay chain, and decoding obtains output binary code B3B4B5B6.After sampling the 1 of delay chain after
Continuous back kick also becomes 1 until A point, as soon as the input terminal of i.e. nor gate is 1, output B jump is 0.After B point becomes 0, up and down
Two delay chains all from front to back successively clear 0, until A point is 0, then the jump of B point is 1, starts next sampling period.
Segmentation comparison module as shown in Figure 4, when the range of input voltage Vsence is very big, when the delay of delay cell
Between and the linearity of supply voltage be not just very high, but when input voltage Vsence changes in lesser range, prolong
The voltage characteristic of slow unit approximate can be seen linear.So if by the range of input voltage Vsence be divided into it is several compared with
When small section, in each interval in input voltage Vsence is converted into binary digit amount, will greatly improve entire
The transfer linearity degree of analog-digital converter.The range of input voltage Vsence is divided it is thinner, entire analog-digital converter it is linear
It spends higher；But if split hairs are drawn, corresponding circuit is realized will be excessively complicated；So comprehensively considering the difficulty or ease journey of circuit realization
The factors such as the conversion accuracy of degree and entire analog-digital converter, the range of input voltage Vsence is divided into four voltages point by us
Section section, corresponding binary coding are B1B2.
Reference voltage is needed to control sampled signal with reference to delay chain, due to voltage segmentation and ring retard
The structure limitation of modulus module is converted, so the reference voltage of each voltage piecewise interval generally takes affiliated voltage piecewise interval
Interior minimum voltage.As shown in figure 5, the transformation of reference voltage is a dynamic adjustment process, in each change-over period
Adaptable adjustment can be made according to high two bit binary numbers amount B1B2.
In different voltage piecewise intervals, ring retard converts the delay chain of modulus module and with reference to required for delay chain
Delay cell number be it is identical, delay cell on two delay chains can with the variation of two bit binary number amount B1B2 and
Corresponding adjustment is done, of delay cell is determined according to the input voltage of the relationship of corresponding delay and current voltage piecewise interval
Number.Ring retard analog-to-digital conversion module is according to high two binary codes B1 and B2 respectively to the delay wire length of four voltage piecewise intervals
Degree is adjusted.As shown in figure 3, delay chain and the corresponding four voltage piecewise intervals of reference delay chain are respectively divided into four sections, phase
By a two distributors connection between two sections adjacent, each two distributor passes through high two binary codes B1 and B2 and determines
The output signal of the preceding paragraph is output to next section and is still directly output to AD conversion unit group.
As seen from Figure 6 invention can complete analog-digital conversion function, input emulation signal is a ramp signal, output letter
Number be square wave.
The above is only a preferred embodiment of the present invention, it should be pointed out that: for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of segment delay ring moulds number converter, it is characterised in that: a high position for the analog-digital converter is set using piece-wise linearization
Meter, low level is using delay ring structure, and digit precision is 6 in total；The analog-digital converter includes sample code module, delay ring moulds
Number conversion module, reference voltage adjustment module and segmentation comparison module, reference voltage V1, V2 and the V3 being segmented in comparison module will
The range of input voltage Vsence is divided into four voltage piecewise intervals [V0, V1], [V1, V2], [V2, V3] and [V3, V4],
Middle V0 and V4 is respectively the lower and upper limit of input voltage Vsence, V0 < V1 < V2 < V3 < V4；Be segmented comparison module according to
Four voltage piecewise intervals carry out analog-to-digital conversion to input voltage Vsence and obtain high two binary codes B1 and B2, postpone ring moulds
Number conversion module is respectively adjusted the delay chain length of four voltage piecewise intervals according to high two binary codes B1 and B2,
Reference voltage adjusts module and is carried out respectively to the reference voltage of four voltage piecewise intervals according to high two binary codes B1 and B2
Adjustment, the delay chain length and reference voltage that ring retard analog-to-digital conversion module combines each voltage piecewise interval are respectively in four electricity
Analog-to-digital conversion is carried out to input voltage Vsence in pressure piecewise interval and obtains low tetrad code B3, B4, B5 and B6.
2. segment delay ring moulds number converter according to claim 1, it is characterised in that: the ring retard analog-to-digital conversion mould
The control signal of block is generated by the inside of the analog-digital converter, the control signal and enable signal of ring retard analog-to-digital conversion module
Two input signals of the enable respectively as nor gate, the introducing of the output control input voltage Vsence of nor gate.
3. segment delay ring moulds number converter according to claim 1, it is characterised in that: the ring retard analog-to-digital conversion mould
Block includes delay chain, with reference to three parts of delay chain and AD conversion unit, delay chain for step signal delay transmitting with
The corresponding delaying state of different voltages is obtained, the delay of sampled signal is used for reference to delay chain, AD conversion unit to be for that will prolong
Slow condition conversion is digital code；Delay chain and reference delay chain correspond to four voltage piecewise intervals, pass through between adjacent two sections
One two distributors connection, each two distributor determine that the output of the preceding paragraph is believed by high two binary codes B1 and B2
Number being output to next section is still directly output to AD conversion unit.
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| CN201610422490.3A CN105959011B (en) | 2016-06-13 | 2016-06-13 | A kind of segment delay ring moulds number converter |
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| CN201610422490.3A CN105959011B (en) | 2016-06-13 | 2016-06-13 | A kind of segment delay ring moulds number converter |
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| CN105959011B true CN105959011B (en) | 2019-03-19 |
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| CN107769785B (en) * | 2017-11-27 | 2020-04-07 | 北京华大九天软件有限公司 | Time sequence control circuit suitable for high-speed analog-to-digital converter |
Citations (3)
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|---|---|---|---|---|
| CN1885722A (en) * | 2006-07-06 | 2006-12-27 | 复旦大学 | A/D converter adapted for mainboard voltage regulation module digital control chip |
| CN101305519A (en) * | 2005-11-11 | 2008-11-12 | Nxp股份有限公司 | Integrating analog to digital converter |
| CN104852739A (en) * | 2015-05-12 | 2015-08-19 | 西安交通大学 | Accuracy reconfigurable delay line ADC circuit for digital power supply |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6977605B2 (en) * | 2003-11-26 | 2005-12-20 | Texas Instruments Incorporated | Dummy delay line based DLL and method for clocking in pipeline ADC |
| US8310290B2 (en) * | 2009-11-17 | 2012-11-13 | Texas Instruments Incorporated | ADC having improved sample clock jitter performance |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101305519A (en) * | 2005-11-11 | 2008-11-12 | Nxp股份有限公司 | Integrating analog to digital converter |
| CN1885722A (en) * | 2006-07-06 | 2006-12-27 | 复旦大学 | A/D converter adapted for mainboard voltage regulation module digital control chip |
| CN104852739A (en) * | 2015-05-12 | 2015-08-19 | 西安交通大学 | Accuracy reconfigurable delay line ADC circuit for digital power supply |
Non-Patent Citations (1)
| Title |
|---|
| 一种用于数字电源的改进型延迟环ADC设计;常昌远 徐兵 杨洋;《电力电子技术》;20101220;第44卷(第12期);第44-46页 |
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