CN200997595Y - Modulus converter structure - Google Patents

Abstract

A structure of new analog-to-digital converter is characterized in that: the structure of analog-to-digital converter is composed of a flowline type ADC and a flash type ADC, which are in series connections. The external analog signal, imputed into the flowline type ADC of the front end, shall produce a N1 digit numerical value after being treated, and then, the analog value, put out by the final grade of the flowline type ADC, is input into the flash type ADC, by which the analog value can be converted to a N2 digit numerical value, and the `` N1+N2`` digit numerical value is put out by an output stage unit circuit at last.

Description

Novel analog-digital converter structure

Technical field

The utility model belongs to field of analog integrated circuit, relates in particular to the novel analog-digital converter structure that a kind of pipeline system ADC combines with lightening ADC.

Background technology

In recent years, along with the quick growth of communication and multimedia recreation consumption market, Digital Signal Processing has obtained fast development, and is widely used in every field.Adopt Digital Signal Processing can realize various advanced persons' adaptive algorithm easily, the function that analog circuit can't be realized before finishing.Therefore, increasing analog is replaced by digital technology.

Along with filtering, frequency conversion, modulation/some Processing tasks such as conciliation enter digital field, the task of analogue unit becomes more and more single, but to more and more higher as the requirement of the analog to digital converter (ADC) that between analogue system and digital system, serves as a connection.

At first, in the application of the video and the communications field, the conversion speed between analog-and digital-continues to increase, and the design of ADC has been proposed new challenge; Secondly, when analog to digital converter is applied on the monolithic system of high integration, can be subjected to interference of noise; In mixed signal processing system, the antijamming capability of ADC becomes more and more important; At last, the development of SOC (system on a chip) is more and more higher for the power consumption requirement of the submodule in the big system, and as the ADC of submodule, its power consumption also is a very crucial parameter in current many application.

The development trend of ADC

Comprehensive technical data of some integrated circuit (IC) design companies both at home and abroad and the information that product manual provides, as can be seen, the main development trend of data converting circuit is to develop towards high-resolution, high conversion rate, low-power consumption, single supply, low-voltage, singualtion, CMOS type direction.

(1) develops to high-resolution, high conversion speed direction

By adopting ∑-Δ modulation technique, under same process conditions, can make the resolution of monolithic ADC reach 18～24; And pipeline system ADC (Pipeline ADC) had both had higher resolution (8～12), and very high conversion speed (5MHz～200MHz) is arranged again.

(2) develop to single supply, low pressure, low-power consumption direction

Adopt CMOS, BiCMOS technology, low-work voltage (1.2V/1.8V) and power supply dormancy working method measure and technology such as (Sleep Mode), both can make converter circuit obtain high-resolution, high accuracy and high conversion rate, can reach the requirement of low-power consumption again, adapt to the needs of portable instrument.

(3) develop to the singualtion direction

Along with improving constantly of semiconductor process technology, the maturation of LSI, VLSI technology, the high-performance change-over circuit that will adopt module, hybrid circuit production in the past coverlet flake products gradually replaces, thereby has reduced the cost and the power consumption of chip, reduce volume, improved reliability.

(4) transform to single CMOS technology

In recent years, visible trend is to attempt as far as possible transducer and some mixed signal functions adopting a kind of technology to make analog-and digital-circuit from CMOS type technology expensive, that complicated professional technology changes main flow over to.

Up to now, the monolithic ADC that is most widely used mainly comprises following several types: integral form, successive approximation, ∑-Δ type, pipeline system and lightening ADC.Wherein first three kind all can't reach very high speed, generally in 1MHz.To simply introduce the operation principle of lightening ADC and pipeline system adc circuit structure below respectively:

Lightening ADC is fastest, and structure is the simplest ADC also, and typical structure adopts (2 as shown in Figure 1 ^N-1) individual comparator is realized N position precision.Reference voltage is by (2 ^N+ 1) individual series resistance dividing potential drop, and respectively as the threshold voltage of each comparator, comparator is output as thermometer-code, is converted to " 8421 " binary code by decoding circuit, exports by output stage at last.

The characteristics of Flash ADC are:

(1) speed is fast

Because whole analog-digital conversion process only needs by once relatively just finishing, so Flash ADC is that operating rate is the fastest among all ADC, and its speed is only limited by comparator, and the conversion speed of present Flash ADC can be up to 8GHz;

(2) area is big, and power consumption is big

Because the number of comparator and the number of resistance become 2 power exponent relation with the ADC precision, so the hardware consumption of Flash ADC is very big, brings the deficiency that area is big, cost is high and power consumption is big thus; (3) precision is limited

In Flash ADC, because reference voltage is subjected to the resistors match characteristic limitations, factors such as the imbalance of comparator have all limited the precision of ADC.The accuracy limitations of general lightening ADC is below 8bit.

The circuit structure of pipelined analog-digital converter as shown in Figure 2, the core of circuit is the N level production line of 1.5bit/stage, peripheral circuit comprises that reference voltage source, clock circuit, delay aim at register array, digital correction circuit and output stage.Every grade of circuit of streamline comprises a MDAC (Multiply Digital to Analog Converter) and 1.5bit dynamic comparer (afterbody is 2bit).The structure of MDAC is the switching capacity sample/hold amplifier, and it has digital-to-analogue conversion, subtraction, 2 times of amplifications and sampling and keeps four functions.Reference power circuit mainly comprises a bandgap voltage reference, produce the burning voltage about a 1.25V, obtain some stable reference voltages and reference current by buffer and resistance chain dividing potential drop then, reference current is as the bias current of the tail current source of operational amplifier, comparator, and reference voltage is the reference voltage of device and MDAC as a comparison; Clock circuit produces the not overlapping clock control signal of many groups, controls 8 level production lines, utilizes different sequential to make circuit alternations such as sample/hold amplifier, comparator and digital error correction; It is synchronous with the dateout adjustment of each level production line to postpone to aim at register array; The digital rectification circuit utilizes redundant digit that transformation result is carried out certain error correction, and error correction procedure realizes with full adder; Output stage adopts the latch output stage, can play to make dateout stable, prevents the effect of external interference.

Find out that thus lightening ADC biggest advantage is exactly that switching rate is high in the prior art, can reach more than the 1Gsps, but the problem that self also exists some to overcome.The exponential increase along with the raising of conversion accuracy of lightening adc circuit scale and power consumption so the monolithic ADC resolution of this structure is less, generally all in 8, can not be satisfied most of demands of applications; Pipeline system ADC structure grows up on lightening structure, it has simplified circuit design, the device count that it is used becomes linear dependence with the conversion figure place, power consumption has obtained restriction, realized higher precision by digital correction circuit, analog signal will be passed through multistage conversion, is between the analog signal parallel processing can reach higher conversion speed.But the major defect of pipelined ad C is an input signal must pass several grades of circuit, causes pipelining delay.

Summary of the invention

The purpose of this utility model is to provide a kind of novel analog-digital converter structure, it combines the advantage of lightening adc circuit structure and pipeline system adc circuit structure, both had high speed, high accuracy, has short advantage of response delay time again, the i.e. new A DC structure of " circuit, two kinds of structures ".

Novel analog-digital converter structure described in the utility model, it is characterized in that: described this analog-digital converter structure is connected in series by pipeline system ADC and lightening ADC, external analog signal is input to the pipeline system ADC of front end, produce the N1 bit digital value after treatment, then the analogue value of pipeline ADC afterbody output is input among the lightening ADC, lightening ADC converts this analogue value to low N2 bit digital value again, at last by output stage element circuit output " N1+N2 " bit digital value.

What described pipeline system ADC adopted is the N1 level, 1.5bit/stage the pipeline system structure, every grade is utilized the input analogue value to produce the 1.5bit digital value, to export analog quantity simultaneously and deliver to next stage, next stage utilizes the output analog quantity of upper level to produce 1.5bit digital value and an analogue value, is input to lower-level again, successively continuous productive process, the delayed circuit of the digital value of generations at different levels outputs to digital correction circuit simultaneously, produces the N1 bit digital value;

Described lightening ADC is made up of electric resistance partial pressure array, comparator and decoder, the electric resistance partial pressure array is divided into a series of reference voltages with reference voltage, the analogue value and these reference voltages of input compare, output M position thermometer-code converts M position thermometer-code the binary code output of to N2 position by decoding circuit again;

Comprise a MDAC (Multiply Digital to AnalogConverter) and 1.5bit comparator in every grade of the described pipeline ADC;

Generally comprise 4 grades～8 level production line cellular constructions in the described pipeline ADC structure, its best value is 4 grades～6 level production line cellular constructions;

The structure of described MDAC is the switching capacity sample/hold amplifier, has digital-to-analogue conversion, subtraction, 2 times of amplifications and sampling and keeps four functions;

Digital rectification circuit in the described pipeline ADC utilizes the redundant digit of every grade of 0.5bit that transformation result is carried out certain error correction, and error correction procedure adopts full adder dislocation addition to realize.

Remarkable beneficial effect of the present utility model is:

Analog-digital converter structure described in the utility model is compared with simple pipelined analog-digital converter structure, and a tangible advantage is exactly to have diminished time of delay, and a N bit stream line type analog to digital converter needs

Time just can produce digital signal; And for analog-digital converter structure described in the utility model, identical precision N=N1+N2 position only needs

Just can produce digital signal, save

Time of delay, wherein T is the sampling clock cycle of analog to digital converter.

Novel analog-digital converter structure described in the utility model is compared with simple lightening analog-digital converter structure, and advantage is that hardware consumption and power consumption are all less.Need 2 for a lightening analog to digital converter in N position ^N-1 comparator and 2 ^N+ 1 resistance; And identical precision only needs 2N1+2 for analog to digital converter described in the utility model ^N2-1 comparator and 2 ^N2+ 1 resistance, hardware consumption is much smaller, and power consumption is also corresponding little a lot.

Description of drawings:

Fig. 1 is the circuit structure of lightening analog to digital converter;

Fig. 2 is the circuit structure of pipelined analog-digital converter;

Fig. 3 is an ADC structure of the present utility model;

Fig. 4 is pipeline system ADC internal structures at different levels;

Fig. 5 is the circuit structure of pipelined analog-digital converter MDAC at different levels;

Fig. 6 is in the simplified electrical circuit diagram of amplification stage for the MDAC circuit;

Fig. 7 is the output transfer function graph of a relation of MDAC;

Fig. 8 is 1.5 bit comparator circuit structure diagrams;

Fig. 9 is the output of 1.5bit comparator and the numerical relation table of differential input signal Vip-Vin;

Figure 10 is that the circuit of lightening analog to digital converter is realized.

Embodiment

The new A DC structure that the utility model proposes is based on pipeline system ADC and lightening ADC structure, as shown in Figure 3:

Its circuit comprises a pipeline system ADC and a lightening ADC, and input analog amount at first passes through the pipeline system ADC of front end, produces the N1 bit digital value; Afterbody at pipeline ADC has a simulation surplus, and this simulation surplus inputs to the lightening ADC of back again, produces the N2 bit digital value, and all N1+N2 bit digital value gather output simultaneously by an output stage element circuit again.Adc circuit described in the utility model generally comprises 4 grades～8 level production line cellular constructions, and its best value is 4 grades～6 level production line cellular constructions;

Below with the implementation procedure of labor pipeline system adc circuit and lightening adc circuit, so that operation principle of the present utility model to be described.

The identical circuit unit of N1 level is arranged among the pipeline system ADC, comprise a MDAC (Multiply Digital to Analog Converter) and 1.5bit dynamic comparer in every stage circuit units, the concrete operation principle of pipeline ADC is as follows:

As shown in Figure 4, at first analog signal is sent into the streamline first order, because the first order does not need to do subtraction, keep function so only need a sample/hold amplifier SHA (Sample Hold Amplifier) to finish sampling, SHA sends sampled signal into the 1.5bit comparator at the corresponding levels and the MDAC of next stage, comparator obtains the 1.5bit digital output code to sampled signal do analog to digital conversion, delivers to Digital Logical Circuits at the corresponding levels and partial MDAC simultaneously; Comprise the 1.5bit digital to analog converter among the MDAC of the second level, subtracter and multiplication factor are 2 SHA (as accompanying drawing 4), digital to analog converter is done the DA conversion with the 1.5bit digital code of the first order and is obtained analog signal, the sampling of sending into the subtracter and the first order again keeps output signal to subtract each other, the gained surplus is amplified 2 times of input signals as next stage MDAC by SHA, and same sampled signal at the corresponding levels is delivered to 1.5bit comparator and the MDAC of subordinate at the corresponding levels; 3rd level structure and the 2nd grade are identical, the structure of afterbody unique different be 2bit comparators of this grade needs because the afterbody streamline does not have the redundant position of correcting; The output of comparators at different levels, synchronous by the adjustment of time-delay aligning register array, be converted to binary code output by digital error correction circuit then.

The realization of MDAC:

The circuit structure diagram of MDAC is as shown in Figure 5:

The structure of MDAC is the switching capacity sample/hold amplifier, and it has digital-to-analogue conversion, subtraction, 2 times of amplifications and sampling and keeps four functions.It is sample phase and amplification stage that MDAC is divided into two stages: when switch φ 1 closure, when φ 2 disconnects, MDAC enters sample phase, and the last charge stored of C1～C4 is respectively:

C1 stored charge: Q1=C1* (Vip-Vcm) (1)

C2 stored charge: Q2=C2* (Vin-Vcm) (2)

C3 stored charge: Q3=C3* (Vip-Vcm) (3)

C4 stored charge: Q4=C4* (Vin-Vcm) (4)

When switch φ 1 disconnection, φ 2 closures, MDAC enters amplification stage, the electric charge redistribution on capacitor C 1～C4, and at this moment MDAC has three kinds of operating states:

A) when $-\mathrm{Vref}<\mathrm{Vip}-\mathrm{Vin}<-\frac{1}{4}\mathrm{Vref}$ The time, K switch 1 closure, K switch 2, K3 disconnect.The bottom crown of C1 is received on the Vref1, and the bottom crown of C2 is received on the Vref2, and after amplification stage finished, difference was output as Von-Vop=2 (Vip-Vin)+Vref;

B) when $-\frac{1}{4}\mathrm{Vref}<\mathrm{Vip}-\mathrm{Vin}<\frac{1}{4}\mathrm{Vref}$ The time, K switch 2 closures, K switch 1, K3 disconnect.The bottom crown of C1 and the bottom crown of C2 are connected on the Vcm, and after amplification stage finished, difference was output as Von-Vop=2 (Vip-Vin);

C) when $\frac{1}{4}\mathrm{Vref}<\mathrm{Vip}-\mathrm{Vin}<\mathrm{Vref}$ The time, K switch 3 closures, K switch 1, K2 disconnect.The bottom crown of C1 is received on the Vref2, and the bottom crown of C2 is received on the Vref1, and after amplification stage finished, difference was output as Von-Vop=2 (Vip-Vin)-Vref.

Prove first kind of a situation below, other situation is in like manner analogized.When the bottom crown of C1 is connected on the Vref1, the following step of C3 is connected on the Vref2, and circuit diagram can be and is simplified to as shown in Figure 6.

C1, C2, C3, C4 charge stored become:

Q1′＝C1*(Vref1-Vc) (5)

Q2′＝C2*(Vref2-Vc) (6)

Q3′＝C3*(Von-Vc) (7)

Q4′＝C4*(Vop-Vc) (8)

According to charge conservation: Q1+Q3=Q1 '+Q3 ' (9)

Q2+Q4＝Q2′+Q4′ (10)

Formula (1) to formula (8) is brought in formula (9) and the formula (10), and formula (9) is deducted formula (10), make C1=C2=C3=C4, put in order:

Von-Vop＝2(Vip-Vin)+(Vref2-Vref1)＝2(Vip-Vin)+Vref

In like manner can get artificial situation a and situation c, comprehensive condition a, b, c can obtain the transmission characteristic of MDAC:

$\left\{\begin{array}{cc}\mathrm{Vout}=2*\mathrm{Vin}+\mathrm{Vref}& -\mathrm{Vref}<\mathrm{Vin}<-\frac{1}{4}\mathrm{Vref}\\ \mathrm{Vout}=2*\mathrm{Vin}& -\frac{1}{4}\mathrm{Vref}<\mathrm{Vin}<\frac{1}{4}\mathrm{Vref}\\ \mathrm{Vout}=2*\mathrm{Vin}-\mathrm{<figure-callout\; id="1"\; label="Vref"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">Vref</figure-callout>}& \frac{1}{4}\mathrm{Vref}<\mathrm{Vin}<\mathrm{Vref}\end{array}\right.---\left(11\right)$

By formula (11) can draw MDAC the output transfer function as shown in Figure 7:

1.5bit the realization of dynamic comparer:

In order to reduce the influence of comparator imbalance, streamline adopts the precision of every grade of 1.5bit, and circuit is with two comparators realization 1.5bit precision, and the output of two comparators is 00,01, one of 11 3 kind of state, so the Bit number of this level is exactly log ₂3=1.5bit.

1.5bit comparator is to be made of the comparator of two 1bit and a plurality of resistance, the circuit diagram of 1.5bit comparator as shown in Figure 8

As shown in Figure 8: according to " superposition theorem ", the magnitude of voltage that we can draw comparator C MP1 positive input terminal is ${\mathrm{<figure-callout\; id="1"\; label="V\; CMP"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{CMP}}=\frac{4}{5}\mathrm{Vip}+\frac{1}{5}\mathrm{<figure-callout\; id="1"\; label="Vref"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">Vref</figure-callout>}1,$ The magnitude of voltage of negative input end is ${\mathrm{<figure-callout\; id="1"\; label="V\; CMP"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{CMP}}=\frac{4}{5}\mathrm{Vin}+\frac{1}{5}\text{Vref2.}$ For comparator C MP1, output D1 is that the condition of high level " 1 " is V _{CMP1_POS}＞V _{CMP1_NEG}, promptly

$\frac{4}{5}\mathrm{Vip}+\frac{1}{5}\mathrm{<figure-callout\; id="1"\; label="Vref"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">Vref</figure-callout>}1>\frac{4}{5}\mathrm{Vin}+\frac{1}{5}\mathrm{<figure-callout\; id="2"\; label="Vref"\; filenames="Y20062001634000141.png,Y20062001634000161.png"\; state="\{\{state\}\}">Vref</figure-callout>}2$

$\&DoubleRightArrow;4(\mathrm{Vip}-\mathrm{Vin})>\mathrm{Vref}2-\mathrm{<figure-callout\; id="1"\; label="Vref"\; filenames="Y20062001634000141.png,Y20062001634000171.png"\; state="\{\{state\}\}">Vref</figure-callout>}1$

$\&DoubleRightArrow;\mathrm{Vip}-\mathrm{Vin}>\frac{1}{4}(\mathrm{Vref}2-\mathrm{Vref}1)=\frac{1}{4}\mathrm{\&Delta;Vref}$

Following formula shows, differential signal $(\mathrm{Vip}-\mathrm{vin})>\frac{1}{4}\mathrm{\&Delta;Vref}$ The time, D1 exports high level; And work as $(\mathrm{Vip}-\mathrm{Vin})<\frac{1}{4}\mathrm{\&Delta;Vref}$ The time, the D1 output low level.

For comparator C MP2, we can do same analysis, just directly provide conclusion here: work as differential signal $\mathrm{Vip}-\mathrm{Vin}>-\frac{1}{4}\mathrm{\&Delta;Vref}$ The time, D0 exports high level, and $\mathrm{Vip}-\mathrm{Vin}<-\frac{1}{4}\mathrm{\&Delta;Vref}$ The time, the D0 output low level.

In sum, this 1.5bit comparator has three kinds of output states: work as differential signal $-\mathrm{\&Delta;Vref}<\mathrm{Vip}-\mathrm{Vin}<-\frac{1}{4}\mathrm{\&Delta;Vref}$ The time .5bit comparator output D1 D0=" 00 "; And work as $-\frac{1}{4}\mathrm{\&Delta;Vref}<\mathrm{Vip}-\mathrm{Vin}<\frac{1}{4}\mathrm{\&Delta;Vref}$ The time, 1.5bit comparator output D1 D0=" 01 "; At last, when $\frac{1}{4}\mathrm{\&Delta;Vref}<\mathrm{Vip}-\mathrm{Vin}<\mathrm{\&Delta;Vref}$ The time, 1.5bit comparator output D1 D0=" 11 ".

Accompanying drawing 9 has been represented the output of 1.5bit comparator and the realization that concerns the Flash adc circuit of differential input signal Vip-Vin:

Flash ADC is mainly by the electric resistance partial pressure array, comparator, and decoder is formed.The electric resistance partial pressure array can be realized by accompanying drawing 10:

As shown in Figure 10: Vref is the output valve of bandgap voltage reference, is approximately 1.2V.Amp is an operational amplifier with very big gain.According to amplifier " empty short principle ", V _X=V _Ref=1.2V, then branch current $I=\frac{{\mathrm{<figure-callout\; id="2"\; label="V\; X\; R"\; filenames="Y20062001634000141.png,Y20062001634000161.png"\; state="\{\{state\}\}">V</figure-callout>}}_X}{R},$ Electric current flows through each resistance and has just produced a series of reference voltage Vref 1 to VrefN.Input signal and these reference voltages have relatively produced thermometer-code Da[1]～Da[N], this N bit digital obtains the binary code output of N2 position by decoder for decoding again.

Claims (7)

1, novel analog-digital converter structure, it is characterized in that: described this analog-digital converter structure is connected in series by pipeline system ADC and lightening ADC, external analog signal is input to the pipeline system ADC of front end, produce the N1 bit digital value after treatment, then the analogue value of pipeline ADC afterbody output is input among the lightening ADC, lightening ADC converts this analogue value to low N2 bit digital value again, at last by output stage element circuit output " N1+N2 " bit digital value.

2, novel analog-digital converter structure according to claim 1, it is characterized in that: what described pipeline system ADC adopted is the N1 level, 1.5bit/stage the pipeline system structure, every grade is utilized the input analogue value to produce the 1.5bit digital value, to export analog quantity simultaneously and deliver to next stage, next stage utilizes the output analog quantity of upper level to produce 1.5bit digital value and an analogue value, be input to lower-level again, continuous productive process successively, the delayed circuit of the digital value of generations at different levels outputs to digital correction circuit simultaneously, produces the N1 bit digital value.

3, novel analog-digital converter structure according to claim 1, it is characterized in that: described lightening ADC is made up of electric resistance partial pressure array, comparator and decoder, the electric resistance partial pressure array is divided into a series of reference voltages with reference voltage, the analogue value and these reference voltages of input compare, output M position thermometer-code converts M position thermometer-code the binary code output of to N2 position by decoding circuit again.

4, novel analog-digital converter structure according to claim 1 is characterized in that: comprise a MDAC (Multiply Digital to Analog Converter) and 1.5bit comparator in every grade of the described pipeline ADC.

5, novel analog-digital converter structure according to claim 1 is characterized in that: generally comprise 4 grades～8 level production line cellular constructions in the described pipeline ADC structure, its best is 4 grades～6 level production line cellular constructions.

6, comprise a MDAC in every grade of the pipeline ADC according to claim 4, it is characterized in that: the structure of described MDAC is the switching capacity sample/hold amplifier, has digital-to-analogue conversion, subtraction, 2 times of amplifications and sampling and keeps four functions.

7, pipeline system ADC according to claim 2 is characterized in that: the digital rectification circuit in the described pipeline ADC utilizes the redundant digit of every grade of 0.5bit that transformation result is carried out certain error correction, and error correction procedure adopts full adder dislocation addition to realize.

Images