CN105930609B - A kind of FPGA timing optimization method for coherent demodulation - Google Patents

A kind of FPGA timing optimization method for coherent demodulation Download PDF

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CN105930609B
CN105930609B CN201610289224.8A CN201610289224A CN105930609B CN 105930609 B CN105930609 B CN 105930609B CN 201610289224 A CN201610289224 A CN 201610289224A CN 105930609 B CN105930609 B CN 105930609B
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CN105930609A (en
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柯昌剑
夏文娟
阳坚
崔晟
李佳敏
刘德明
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Huazhong University of Science and Technology
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

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Abstract

The invention discloses a kind of FPGA timing optimization methods for coherent demodulation.The FPGA timing optimization method includes carrying out the pipeline design to FPGA；Judge whether there is the path that total delay is more than delay threshold δ；Judge whether logical time delay and the ratio k of wiring delay are more than or equal to delay proportion threshold value ε in destination path；The destination path is corresponded into the algorithm in algoritic module and is set as the method for exhaustion, and all possible calculated result of the algoritic module is stored in read-only memory；The maximum for resetting FPGA is fanned out to until the maximum value that all paths are always delayed is less than or equal to delay threshold δ.The method that the present invention passes through logic optimization, to solve the problems, such as feedback or interative computation and cannot have been optimized using the pipeline design, all possible calculated result is stored in read-only memory by this method, to reduce the logic series in path using the method for exhaustion, the real-time processing frequency of FPGA is improved.

Description

A kind of FPGA timing optimization method for coherent demodulation
Technical field
The invention belongs to field programmable gate arrays (FPGA) and signal Real-time demodulation field, more particularly, to one kind FPGA timing optimization method for coherent demodulation.
Background technique
Optical fiber telecommunications system transmission capacity is promoted using advanced modulation formats and coherent reception mode, it has also become mainstream technology One of scheme.Signal is inevitably damaged during coherent reception, including dispersion, polarization mode dispersion, frequency are inclined Shifting and phase noise etc..The coherent receiver Digital Signal Processing block diagram of the prior art is as shown in Figure 1, the system includes that light is mixed Frequency device, balanced detector, ADC and FPGA, wherein the input terminal of the output end connection balanced detector of optical mixer unit, balance are visited The input terminal of the output end connection ADC of device is surveyed, the output end of ADC connects FPGA.FPGA unit for Digital Signal Processing is again Including functional modules such as serioparallel exchange, dispersion compensation, polarization demultiplexing, frequency deviation compensation and phase noise compensations, wherein going here and there simultaneously Conversion output connects dispersion compensation input terminal, and dispersion compensation output end connects polarization demultiplexing input terminal, and polarization demultiplexing is defeated Outlet connects frequency deviation and compensates input terminal, and frequency deviation compensates output end and connects phase noise compensation input terminal.The optical signal of input passes through Optical mixer unit, simulation I is obtained after balanced detector, then Q signal samples to obtain digital signal, passes through serioparallel exchange by ADC High-speed serial signals are converted into speed parallel signals, demodulation (dispersion compensation, polarization demultiplexing, the frequency deviation compensation, phase of the signal Position noise compensation) it is placed in FPGA and carries out.Since field programmable gate array (FPGA) has stronger handling capacity and cleverer Property living generallys use the platform that FPGA is designed as coherent demodulation system.
When FPGA carries out Real-time demodulation to signal, hardware handles rate " bottleneck " can be faced, so as to cause real time algorithm Realization process be obstructed.And the parallel processing of FPGA and to FPGA carry out timing optimization, be able to solve this problem.It is based on The development process of the digital information processing system of FPGA is as shown in Fig. 2, include: parts selection, design input, functional simulation, comprehensive It closes, optimization, realize and several parts such as placement-and-routing, code stream generation and code stream downloading.Parts selection refers to answering according to system The real-time processing frequency of miscellaneous degree and required FPGA, resource, cost etc. are assessed, and suitable FPGA model is selected；Design Input refers to is designed exploitation for required algorithm in the form of software development；Functional simulation refers to the circuit to user's design Functional verification is carried out, the result of emulation is exported with file and waveform；It is low that synthesis refers to that the description by advanced level is converted into The description of grade level；Optimization, which refers to, carries out the pipeline design, logic optimization or Wiring optimization to FPGA to meet processing frequency in real time The demand of rate；It then carries out realizing the design for then completing FPGA with placement-and-routing, code stream generation and code stream downloading.
Wherein, the quality of optimization will affect the real-time processing frequency of FPGA.However, in the FPGA algoritic module of the prior art Using a large amount of live calculating method, (according to the process design circuit of certain algorithm, the circuit is for transporting input signal Calculate, the result after exporting operation), this method realizes that the logic series in rear path is more, and logical time delay is longer, causes FPGA real Operational efficiency when existing real time algorithm is not high.Such as article " the Clock and that Amado, S.B. etc. are published on SPIE for 2014 Carrier recovery in high-speed coherent optical communication systems " (" high speed Clock and carrier auxiliary are realized in coherent optical communication system "), since this method does not take effective way excellent to FPGA progress logic Change and Wiring optimization, are only able to achieve the coherent demodulation of 1.25Gb/s QPSK signal.
Summary of the invention
For the disadvantages described above and Improvement requirement of the prior art, the present invention provides when a kind of FPGA for coherent demodulation Sequence optimization method, its object is to improve the real-time processing frequency of FPGA by the pipeline design, logic optimization and Wiring optimization Rate, to realize the demodulation of higher rate signal.
According to one aspect of the present invention, a kind of FPGA timing optimization method for coherent demodulation is provided, including with Lower step:
S1. the pipeline design is carried out to FPGA；
S2. the path that total delay is more than delay threshold δ is judged whether there is, if so, choosing the path as target road Diameter, and S3 is entered step, if it is not, then timing optimization terminates, wherein total delay is made of logical time delay and wiring delay；
S3. judge whether logical time delay and the ratio k of wiring delay are more than or equal to delay proportion threshold value ε in destination path, If so, S4 is entered step, if it is not, then entering S5；
S4. the destination path is corresponded into the algorithm in algoritic module and is set as the method for exhaustion, and the algoritic module is owned Possible calculated result is stored in read-only memory, again comprehensive wiring, return step S2；
S5. the maximum for resetting FPGA is fanned out to the maximum value being always delayed up to all paths and is less than or equal to delay threshold δ, Again comprehensive wiring, return step S2.
Preferably, the delay proportion threshold value ε is 1:4~2:3.
Preferably, the step S5 specifically:
S51. i=1, k are enablediIt is fanned out to for current maximum, AiIt is that maximum is fanned out to as kiWhen, what corresponding all paths were always delayed Maximum value；
S52. k is enabledi+1=[ki/ 2], comprehensive wiring again, wherein ki+1Newly-installed maximum of attaching most importance to is fanned out to, and [] indicates It is rounded downwards；
If S53. Ai+1≤ δ, then return step S2, otherwise i=i+1, return step S52.
Preferably, the S1 specifically: judge with the presence or absence of feedback loop or interative computation in overall circuit, be to protect Hold constant, the otherwise combinational logic circuit in selection overall circuit, and adjacent logic circuit in the combinational logic circuit Between register is set, the calculated result of the logic circuit for storing previous stage.
Preferably, the delay threshold δ≤1/f, f are the real-time processing frequency of FPGA.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, by the pipeline design, The optimization of logical time delay and wiring delay, improves the real-time processing frequency of FPGA, can achieve the following beneficial effects:
1, all possible calculated result of the algoritic module is stored in read-only memory, road is reduced using the method for exhaustion Logic series in diameter, so that solving cannot be optimized because having feedback or interative computation by the pipeline design Problem improves the real-time processing frequency of FPGA；
2, it is fanned out to by limiting the maximum of FPGA, so that solving leads to cloth because being fanned out to excessive influence FPGA wiring stability Line is delayed larger problem, so that device load is reduced, improves the real-time processing frequency of FPGA；
Which 3, need preferentially to carry out using step by the current FPGA of ratio in judgement of logical time delay and wiring delay excellent Change, to choose technological means more efficiently, improves the effect of optimization；
4, using the method for the pipeline design, deposit is set between logic circuit adjacent in combinational logic circuit Complex logic feature operation is divided into multiple periods completions, the handling capacity of data is improved, to improve the real-time of FPGA by device Processing frequency.
Detailed description of the invention
Fig. 1 is coherent receiver Digital Signal Processing block diagram；
Fig. 2 is the development process figure of FPGA；
Fig. 3 is FPGA timing optimization method flow chart of the present invention；
Fig. 4 is that assembly line schematic diagram is not used；
Fig. 5 is using assembly line schematic diagram；
Fig. 6 is that assembly line schematic diagram is not used in multistage complex multiplication in the frequency deviation backoff algorithm of the offer of the embodiment of the present invention 1；
Fig. 7 is that multistage complex multiplication uses assembly line schematic diagram in the frequency deviation backoff algorithm of the offer of the embodiment of the present invention 1；
Fig. 8 is the live calculating method view that the embodiment of the present invention 1 provides；
Fig. 9 is the method for exhaustion Design view that the embodiment of the present invention 1 provides；
Figure 10 be the embodiment of the present invention 1 provide be fanned out to hardware circuit implementation when being 26；
Figure 11 be the embodiment of the present invention 1 provide be fanned out to hardware circuit implementation when being 13.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below Not constituting a conflict with each other can be combined with each other.
In FPGA after the completion of designing and developing with comprehensive wiring, the total delay shadow of the real-time processing frequency of FPGA by path It rings, total delay in each path is made of logical time delay and wiring delay.The present invention provides a kind of for coherent demodulation FPGA timing optimization method, to reduce logical time delay and the wiring delay in path, as shown in Figure 3, comprising the following steps:
S1. the pipeline design
Judge with the presence or absence of feedback loop or interative computation in overall circuit, be to remain unchanged, otherwise chooses overall Combinational logic circuit in circuit, and register is set between logic circuit adjacent in the combinational logic circuit, it is used for Store the calculated result of the logic circuit of previous stage；
This method shortens the time of signal in one cycle by overall circuit, so that the real-time processing of FPGA be made to believe Number frequency is improved.If Fig. 4 is an overall circuit schematic diagram for not using the pipeline design, it can be seen that data pass through two (logic circuit 1, logic circuit 2, and the delay of each logic circuit are a) to need 2a to a logic circuit, then in a clock It (CLK) is 2a by the delay of the overall circuit in the period.Fig. 5 is an overall circuit schematic diagram using assembly line, every It is inserted into register among a classification (logic circuit 1, logic circuit 2), then passes through logic circuit 1 in first clock cycle, under One clock cycle passes through logic circuit 2, then being delayed within a clock cycle by the overall circuit is a.Using assembly line Design reduces the processing delay of overall circuit, to improve the real-time processing frequency of FPGA.
S2. the path that total delay is more than delay threshold δ is judged whether there is, is to choose the path as destination path, S3 is entered step, otherwise timing optimization terminates；
S3. be entire data processing it is singly to flow to using the condition of assembly line, i.e., does not have feedback loop in overall circuit Or interative computation, otherwise it cannot be optimized using the scheme of the pipeline design.When total delay of destination path is more than delay Threshold value δ (the real-time processing frequency that δ≤1/f, f are FPGA), and logical time delay and the ratio k of wiring delay are greater than in the path Be delayed proportion threshold value ε, and ε is 1:4~2:3, and integrating out circuit logic series may need to be more than tens of grades to target road Diameter carries out logic optimization；
S4. logic optimization
Destination path is corresponded into the algorithm in algoritic module and is set as the method for exhaustion, i.e., by all possible meter of the algoritic module It calculates result to be stored in read-only memory, when the method for exhaustion calculates, it is only necessary to the phase from the value of input signal mapping read-only memory The address for answering calculated result further takes out its corresponding calculated result, to reduce logic series.Again after comprehensive wiring, respectively The delay in path can change, and return to S2 at this time, re-start inspection；
For example, if the formula of the algorithm of script algoritic module is y=x4, wherein x be input signal, x=1,2,3,4 or 5, y be output signal, to obtain y firstly the need of calculating x × x=x2, then by x2×x2=y obtains y.If by the algorithm mould Algorithm in block is set as the method for exhaustion, it is only necessary to and the result 1,16,81,256,625 that will likely be obtained is stored in read-only memory, It, can the corresponding result of step taking-up directly according to input signal x when carrying out signal processing.
S5. Wiring optimization
Wiring delay be fanned out in close relations, be fanned out to (Fanout) and refer to that module is directly connected to a of the Subordinate module of driving Number is fanned out to more and is commonly referred to as the multiple lower logical devices of individual node driving.If be fanned out to more than numerical value reaches tens of, at this time Will affect FPGA wiring stability, directly translate into wiring delay it is larger, be unfavorable for timing closure；
In above scheme, maximum being limited using synthesis tool and is fanned out to, synthesis tool will be certainly after being fanned out to value more than maximum Dynamicly register is replicated, to realize Wiring optimization.
The maximum for resetting FPGA is fanned out to until the maximum value that all paths are always delayed is less than or equal to delay threshold δ, weight After new comprehensive wiring, the delay in each path can be changed, and return to S2 at this time, re-start inspection.This method specifically:
S51. i=1, k are enablediIt is fanned out to for current maximum, AiIt is that maximum is fanned out to as kiWhen, what corresponding all paths were always delayed Maximum value；
S52. k is enabledi+1=[ki/ 2], comprehensive wiring again；
If S53. Ai+1≤ δ then enters in next step, otherwise i=i+1, return step S52.
Embodiment 1
In the present embodiment using FPGA to 10GBaud QPSK signal carry out coherent demodulation (including frequency deviation compensation and phase make an uproar Sound compensation), 32 tunnel parallel processings are used in the development process of FPGA, then the real time signal processing frequency of FPGA should reach 10G/ 32=312.5MHz (at this time threshold value δ be 3.2ns) or more, then the timing optimization method of the present embodiment the following steps are included:
S1. the pipeline design:
Judge in overall circuit with the presence or absence of feedback loop or interative computation.If Fig. 6 is QPSK provided in this embodiment The overall circuit of signal frequency deviation compensation and the multistage complex multiplication in phase noise compensation algorithm, the overall circuit include 3 and patrol It collects circuit (i.e. 3 complex multiplier DSP48 units), which is not present feedback loop or interative computation, can It is optimized using the method for the pipeline design.Can be seen that, optimize before each level logic circuit complex multiplication delay be a, one Being delayed in a clock cycle by the overall circuit is 3a.
It is inserted into register between neighbor logic circuit, above-mentioned overall circuit is divided into 3 grades.Fig. 7 is the present embodiment Overall circuit optimized using the above method after schematic diagram, it can be seen that between every two neighbor logic circuit increase by one post Storage is used to store the processing result of the logic circuit of previous stage, and being delayed in a clock cycle by the overall circuit is a.
The larger delay that three complex multiplier composition combinational logic circuits generate can be reduced using the pipeline design, made multiple Miscellaneous logical operation substep is completed, to improve the real-time processing frequency of FPGA.
S2. the path that total delay is more than delay threshold δ is judged whether there is, due to the present embodiment FPGA real time signal processing Frequency f should reach 312.5MHz or more, and delay threshold δ is necessarily less than equal to 1/f (i.e. 3.2ns).Before optimization it is total delay be 5.038ns then first finds out the details of the corresponding destination path that is always delayed, and the destination path corresponds to Unwrap mould at this time Block, as shown in table 1:
The delay path details of table 1Unwrap module
S3. the ratio k ≈ 0.75 that logical time delay and wiring are delayed in the destination path, since the k of the destination path is more than 2:3, then need to carry out logic optimization.
S4. Fig. 8 is that live calculating method provided in this embodiment designs the building-block of logic before the optimization of Unwrap module, it is known that It uses live calculating method electrical combination logic series for 14 grades, causes fpga logic delay bigger than normal.By the destination path Algorithm in (Unwrap module) corresponding algoritic module is set as the method for exhaustion, i.e., ties all possible calculating of the algoritic module Fruit is stored in read-only memory.Fig. 8 is the Unwrap module diagram after being optimized according to the above method, when the module carries out in fact When signal processing when, input signal value mapping read-only memory in corresponding address, then from the address take out calculated result, thoroughly Act method can reduce the corresponding logic series of algoritic module.It may be seen that logic after optimization inside combinational logic in Fig. 9 Series greatly reduces, and reduces from 14 grades to 3 grades, since logical time delay is directly proportional to logic series, it may thus be appreciated that logical time delay is bright It is aobvious to reduce.
After logic optimization, comprehensive wiring again is needed herein, and judges whether that there are still total delay be more than delay threshold δ Path.At this point, still there is the path that total delay is 3.547ns, as shown in table 2, due to 3.547ns >=δ, and the path is corresponding Ratio k=0.08 of logical time delay and wiring delay, it is therefore desirable to carry out in next step, i.e. Wiring optimization.
The delay specifying information table of table 2
S4. from table 2 it can be seen that it is 500 that FPGA current maximum, which is fanned out to, and high be fanned out to causes wiring delay excessive Main cause can be fanned out to realization Wiring optimization by reducing.If Figure 10 is hardware circuit implementation when being fanned out to be limited to 26, it can be seen that Register 1 needs to drive load 1, load 2 ... 26 (i.e. elementary logic circuit units) of load, and the load of driving is more and leads to cloth Wire delay.(it will be fanned out to after limiting maximum and being fanned out to and be limited to 13, then certain signal driver part is no more than 13), Figure 11 is to be fanned out to Hardware circuit implementation when being 13, it can be seen that it, which increases a register 2, makes load be divided into two parts, and the driving load of register 1 is Load 1, load 2 ... load 13, register 2, which drives to load, loads 26 for load 14, load 15 ..., and each register drives negative The reduction of number is carried so that wiring delay reduces, to improve the real-time processing frequency of FPGA.
Table 3 be in QPSK signal frequency deviation provided in this embodiment compensation and the design of phase noise compensation algorithm maximum be fanned out to and The relationship of wiring delay, when being fanned out to reduction, which drives number of loads to reduce, and wiring delay is also corresponding to be reduced, The real-time processing frequency of FPGA is improved.From the data in the table with the reduction being fanned out to, wiring delay also reduces therewith.
3 maximum of table is fanned out to be delayed with wiring
It in concrete operations, can be halved by the way that maximum is fanned out to value every time, and observe the maximum being always delayed in all paths The variation of value, such as:
S51. i=1, k are enablediIt is fanned out to for current maximum, AiIt is that maximum is fanned out to as kiWhen, what corresponding all paths were always delayed Maximum value；
S52. k is enabledi+1=[ki/ 2], comprehensive wiring again；
If S53. Ai+1≤ δ then enters in next step, otherwise i=i+1, return step S52.
Table 4 be the present embodiment carry out the pipeline design, logic optimization and limitation maximum be fanned out to after, current maximum be fanned out to Temporal constraint and running frequency relationship, it is known that timing optimization is carried out to FPGA by the method for the invention and significantly improves FPGA Real-time processing frequency, at this time all paths of the FPGA it is total delay be respectively less than delay threshold, then timing optimization terminates.
Table 4 is currently fanned out to size and temporal constraint and running frequency relationship
It is fanned out to limitation 300 150 75 37 18 9
Temporal constraint (ns) 3.5 3.4 3.3 3.3 3.1 3
Running frequency (MHZ) 285.71 294.12 303.03 303.03 322.58 333.33
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include Within protection scope of the present invention.

Claims (4)

1. a kind of FPGA timing optimization method for coherent demodulation, which comprises the following steps:
S1. the pipeline design is carried out to FPGA；
S2. it judges whether there is total delay and is more than the path of delay threshold δ, if so, the path is chosen as destination path, and S3 is entered step, if it is not, then timing optimization terminates, wherein total delay is made of logical time delay and wiring delay；
S3. judge whether logical time delay and the ratio k of wiring delay are more than or equal to delay proportion threshold value ε in destination path, if so, S4 is then entered step, if it is not, then entering S5；
S4. the destination path is corresponded into the algorithm in algoritic module and is set as the method for exhaustion, and by all possibility of the algoritic module Calculated result be stored in read-only memory, return step S2；
S5. the maximum for resetting FPGA is fanned out to until the maximum value that all paths are always delayed is less than or equal to delay threshold δ, return Step S2；
The S1 specifically: judge with the presence or absence of feedback loop or interative computation in overall circuit, be to remain unchanged, otherwise The combinational logic circuit in overall circuit is chosen, and deposit is set between logic circuit adjacent in the combinational logic circuit Device.
2. FPGA timing optimization method as described in claim 1, which is characterized in that the delay proportion threshold value ε is 1:4~2: 3。
3. FPGA timing optimization method as described in claim 1, which is characterized in that the step S5 specifically:
S51. i=1, k are enablediIt is fanned out to for current maximum, AiIt is that maximum is fanned out to as kiWhen correspond to the maximum that all paths are always delayed Value；
S52. k is enabledi+1=[ki/ 2], comprehensive wiring again, wherein ki+1Newly-installed maximum of attaching most importance to is fanned out to, and [] expression takes downwards It is whole；
If S53. Ai+1≤ δ, then return step S2, otherwise i=i+1, return step S52.
4. FPGA timing optimization method as described in claim 1, which is characterized in that the delay threshold δ≤1/f, f FPGA Real-time processing frequency.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101315547A (en) * 2008-07-15 2008-12-03 北京中星微电子有限公司 Control system based on multiple FPGA
CN102768506A (en) * 2012-07-18 2012-11-07 复旦大学 FPGA (Field Programmable Gate Array) timing driven layout method with timing constraints
CN103885819A (en) * 2012-12-21 2014-06-25 中国科学院微电子研究所 Priority resource sharing method for FPGA area optimization
CN104901686A (en) * 2015-06-09 2015-09-09 中山大学 Phase-locked loop with low phase noise
CN105203137A (en) * 2015-09-07 2015-12-30 华中科技大学 Optical fiber multi-domain sensing system and demodulation method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101315547A (en) * 2008-07-15 2008-12-03 北京中星微电子有限公司 Control system based on multiple FPGA
CN102768506A (en) * 2012-07-18 2012-11-07 复旦大学 FPGA (Field Programmable Gate Array) timing driven layout method with timing constraints
CN103885819A (en) * 2012-12-21 2014-06-25 中国科学院微电子研究所 Priority resource sharing method for FPGA area optimization
CN104901686A (en) * 2015-06-09 2015-09-09 中山大学 Phase-locked loop with low phase noise
CN105203137A (en) * 2015-09-07 2015-12-30 华中科技大学 Optical fiber multi-domain sensing system and demodulation method

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