CN103885819A - Priority resource sharing method for FPGA area optimization - Google Patents
Priority resource sharing method for FPGA area optimization Download PDFInfo
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- CN103885819A CN103885819A CN201210564207.2A CN201210564207A CN103885819A CN 103885819 A CN103885819 A CN 103885819A CN 201210564207 A CN201210564207 A CN 201210564207A CN 103885819 A CN103885819 A CN 103885819A
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Abstract
The invention discloses a priority resource sharing method aiming at FPGA area optimization, which comprises the following steps: reading the RTL integrated intermediate data structure netlist, and searching and collecting all sequential mutually exclusive branches in the netlist; analyzing specific operations in the mutually exclusive branches, and detecting and collecting the same arithmetic operations in the mutually exclusive branches; and sharing arithmetic operations with the same output preferentially, sharing arithmetic operations with only a common input port, and sharing arithmetic operations without a common port. By using the invention, the Arithmetic Logic units (ALU-Arithmetric Logic units) can be reduced by detecting the same Arithmetic operations with mutually exclusive time sequence in the HDL design file and sharing the Arithmetic operations in sequence according to the specified sequence, thereby achieving the effect of area optimization.
Description
Technical field
The present invention relates to field programmable gate array (FPGA) and EDA Technique field, particularly a kind of for the area-optimized priority resource share method of FPGA.
Background technology
Resource sharing refers to the process that two or more arithmetical operations of sequential mutual exclusion are realized with an ALU, is one of key method of FPGA complex optimum.
FPGA eda tool comprises: comprehensive (synthesis), mapping (mapping), layout (placing), wiring (routing), code stream generate several parts such as (bit gen) and code stream download (download), have become the very crucial part in one, FPGA field.The quality of eda tool directly affects realization and the effect of design.
Comprehensively (synthesis) is one of key component in FPGA eda tool, is that the design document that HDL is described is translated and optimizes, and is converted to the net table of gate leve, and is optimized.Its Optimization Dept. divides the optimization comprising for area, sequential and power consumption, and the result of optimization directly determines the quality of design result.
Resource sharing is FPGA one of area-optimized important method in comprehensive, and the number that it can reduce complicated ALU, realizes area-optimized.
In comprehensive (the Register Transfer Level Synthesis) technology of existing RTL, resource sharing algorithm imperfection, causes the optimization that may occur not thorough, and the problem of data stream collision error.
Summary of the invention
(1) technical matters that will solve
In view of this, it is a kind of for the area-optimized priority resource share method of FPGA that fundamental purpose of the present invention is to provide, to solve the problem of the thorough and data stream collision error of resource sharing may occur in RTL is comprehensive optimization.
(2) technical scheme
For achieving the above object, the invention provides a kind ofly for the area-optimized priority resource share method of FPGA, comprising: read the comprehensive intermediate data structure net of RTL table, search and collecting net table in the branch of all sequential mutual exclusions; Concrete operations in the branch of analysis sequential mutual exclusion, detect and collect arithmetical operation identical in the branch of sequential mutual exclusion; And preferentially the arithmetical operation that has identical output is shared, secondly the arithmetical operation of only having public input port is shared, finally the arithmetical operation that there is no public port is shared.
In such scheme, the described comprehensive intermediate data structure net of the RTL table that reads, search and collecting net table in the step of branch of all sequential mutual exclusions, at any time, in every group, sequential mutual exclusion branch only has at most a branch to carry out, these branches comprise the different branches of if, else branch and case, and comprise the difference input branch of mux in structural level description.
In such scheme, the concrete operations in the branch of described analysis sequential mutual exclusion, detect and collect in the step of arithmetical operation identical in the branch of sequential mutual exclusion, only share for complicated arithmetical operation, do not consider logical operation.
In such scheme, described preferential to there being the arithmetical operation of identical output to carry out in shared step, be preferentially the arithmetical operation that is connected to same mux to be shared, shared concrete operations comprise: two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation A; Secondly between the identical arithmetical operation of detection Mei Zu mutual exclusion branch, have and there is no public input port, public port is connected to an input of this arithmetical operation A; The mux of output terminal is moved to input end, select the driving signal of non-public input port.
In such scheme, described the arithmetical operation of only having public input port is carried out to shared step, comprise: two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation, public port is connected to an input of this arithmetical operation, mux of another one input end interpolation selects the driving signal of non-public input port, and output terminal drives multiple modules.
In such scheme, described the arithmetical operation that there is no public port is carried out to shared step, comprise: two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation, two input ends add respectively a mux and select to drive signal, and output terminal drives multiple modules.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, provided by the invention is the improvement project on the basis of resource sharing for the area-optimized priority resource share method of FPGA, and sharable resource priority orders is according to the rules shared successively.Not only can avoid like this data stream collision error, but also can make the mux quantity that result increases reduce.
2, provided by the invention for the area-optimized priority resource share method of FPGA, first to collect the branch of all sequential mutual exclusions, as if, else branch and case branch, between the different branches of each group, be sequential mutual exclusion, all moment only have at most a branch to carry out.Guarantee there will not be signal conflict after sharing like this.Secondly, detect each branch, the identical arithmetical operation of the different branches of mark, shares these arithmetical operations priority orders according to the rules.
3, provided by the invention for the area-optimized priority resource share method of FPGA, sharing operation has reduced the number of complicated ALU, has realized area-optimized.The method is only shared arithmetical operation, logical operation is not shared.Because the Area comparison that ALU takies is large, although may introduce mux, total cognition reduces area.And logical block is carried out to shared process, and reduce logical block, increase mux, result area not necessarily reduces.
4, provided by the inventionly improve on the basis of resource sharing for the area-optimized priority resource share method of FPGA, result, in reducing arithmetical operation number, also makes the mux quantity increasing reduce, and even some situation can not increase mux; Also can avoid occurring that combined loop produces the error result of data stream conflict in resource sharing process simultaneously.
Brief description of the drawings
Fig. 1 is the process flow diagram for the area-optimized priority resource share method of FPGA provided by the invention;
Fig. 2 is the schematic diagram of RLT comprehensive network Biao Zhongliangge mutual exclusion branch in Fig. 1;
Fig. 3 is the schematic diagram of the arithmetical operation that in Fig. 1, in the comprehensively middle mutual exclusion of RTL branch, mark is identical;
Fig. 4 describes and does not adopt the net of resource sharing to represent intention according to the hdl file of first embodiment of the invention;
Fig. 5 is the shared result schematic diagram according to the resource share method that does not adopt priority of first embodiment of the invention;
Fig. 6 is the result schematic diagram according to the employing priority resource sharing of first embodiment of the invention;
Fig. 7 describes and does not adopt the net of resource sharing to represent intention according to the hdl file of second embodiment of the invention;
Fig. 8 is the shared result schematic diagram that does not adopt priority resource sharing according to second embodiment of the invention;
Fig. 9 is the result schematic diagram according to the employing priority resource share method of second embodiment of the invention;
Figure 10 a is the schematic diagram before two sequential mutual exclusion totalizers are optimized;
Figure 10 b is the schematic diagram that two sequential mutual exclusion totalizer resource sharing steps are decomposed;
Figure 10 c is the result schematic diagram after two sequential mutual exclusion totalizers are optimized.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the process flow diagram for the area-optimized priority resource share method of FPGA provided by the invention, and the method comprises the following steps:
Step S1, read the comprehensive intermediate data structure net of RTL table, search and collecting net table in the branch of all sequential mutual exclusions;
At any time, sequential mutual exclusion branch only has at most a branch to carry out in every group.These branches mainly comprise the different branches of if, else branch and case, also comprise the difference input branch of mux in structural level description, and as shown in Figure 2, two add operations are one group of sequential mutual exclusion branch, only have at most at any time a totalizer to carry out.
Concrete operations in the branch of step S2, the mutual exclusion of analysis sequential, detect and collect arithmetical operation identical in the branch of sequential mutual exclusion;
The present invention just shares for complicated arithmetical operation, does not consider logical operation.As shown in Figure 3, the identical add operation between mark Liang Ge mutual exclusion branch.
Step S3, preferentially to there being identical output, the arithmetical operation that is connected to same mux is shared.
As shown in Figure 4, do not adopt the result of resource sharing in this first embodiment, comprise 3 totalizer ADD1, ADD2 and ADD3, wherein the output of ADD2 and ADD3 is connected to same mux, preferentially ADD2 and ADD3 is shared.
Shared concrete operations are divided into the following steps: two or more arithmetical operation mesh mergings that (1) first can merge Mei Zu mutual exclusion branch are an arithmetical operation A, as shown in Figure 10 a; (2) secondly between the identical arithmetical operation of detection Mei Zu mutual exclusion branch, have and there is no public input port, public port is connected to an input of A; (3) mux of output terminal is moved to input end, select the driving signal of non-public input port, as shown in Figure 10 b.Result after optimization is as shown in Figure 10 c.
Secondly step S4, the arithmetical operation of only having public input port is shared, two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation A, public port is connected to an input of A, mux of another one input end interpolation selects the driving signal of non-public input port, and output terminal drives multiple modules.
Step S5, finally the arithmetical operation that there is no public port is shared, two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation A, two input ends add respectively a mux and select to drive signal, and output terminal drives multiple modules.
Advantage of the present invention is as follows:
One compares with common resource sharing, provided by the inventionly can reduce mux quantity for the area-optimized priority resource share method of FPGA.As shown in Figure 4, the result of not carrying out resource sharing in this first embodiment comprises 3 totalizers, 1 mux; If do not adopt the resource sharing of priority approach, as shown in Figure 5, in this first embodiment, ADD1 and ADD3 share, result: 2 totalizers and 3 mux; The resource share method that adopts priority, as shown in Figure 6, in this first embodiment, ADD2 and ADD3 share, and result only has two totalizers and two mux, compares reduced by a totalizer with Fig. 4, compares reduced by a mux with Fig. 5.
Two, avoid data stream collision error.The second embodiment of the present invention as shown in Figure 7, does not adopt the synthesis result of resource sharing to contain 4 totalizers and 1 mux.If do not adopt the resource share method of priority, as shown in Figure 8, in this second embodiment, ADD1 and ADD4 share result, and ADD2 and ADD3 share, and can produce 2 totalizers and 5 mux, and there will be combined loop, produce the error result of data stream conflict.Adopt the resource sharing of priority, as shown in Figure 9, in this second embodiment, ADD2 and ADD4 share result, ADD1 and ADD3 share, and result contains 2 totalizers and 3 mux, compares reduced by 2 totalizers with Fig. 7, and there will not be combined loop, compare with Fig. 8 and reduced by 2 mux.
Provided by the invention for the area-optimized priority resource share method of FPGA, its result is compared with common resource sharing, can reduce the quantity of mux, better realizes area-optimized; In some cases, when reducing mux, also reduced the progression of mux time delay, sequential result is better.The method also can be avoided data stream conflict, prevents from sharing the error result that combined loop appears in result.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (6)
1. for the area-optimized priority resource share method of FPGA, it is characterized in that, comprising:
Read the comprehensive intermediate data structure net of RTL table, search and collecting net table in the branch of all sequential mutual exclusions;
Concrete operations in the branch of analysis sequential mutual exclusion, detect and collect arithmetical operation identical in the branch of sequential mutual exclusion; And
Preferentially the arithmetical operation that has identical output is shared, secondly the arithmetical operation of only having public input port is shared, finally the arithmetical operation that there is no public port is shared.
2. according to claim 1 for the area-optimized priority resource share method of FPGA, it is characterized in that, the described comprehensive intermediate data structure net of the RTL table that reads, search and collecting net table in the step of branch of all sequential mutual exclusions, at any time, in every group, sequential mutual exclusion branch only has at most a branch to carry out, and these branches comprise the different branches of if, else branch and case, and comprises the difference input branch of mux in structural level description.
3. according to claim 1 for the area-optimized priority resource share method of FPGA, it is characterized in that, concrete operations in the branch of described analysis sequential mutual exclusion, detect and collect in the step of arithmetical operation identical in the branch of sequential mutual exclusion, only share for complicated arithmetical operation, do not consider logical operation.
4. according to claim 1 for the area-optimized priority resource share method of FPGA, it is characterized in that, described is preferentially the arithmetical operation that is connected to same mux to be shared preferentially to there being the arithmetical operation of identical output to carry out in shared step, and shared concrete operations comprise:
Two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation A;
Secondly between the identical arithmetical operation of detection Mei Zu mutual exclusion branch, have and there is no public input port, public port is connected to an input of A;
The mux of output terminal is moved to input end, select the driving signal of non-public input port.
5. according to claim 1ly it is characterized in that for the area-optimized priority resource share method of FPGA, described the arithmetical operation of only having public input port carried out to shared step, comprising:
Two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation, public port is connected to an input of this arithmetical operation, mux of another one input end interpolation selects the driving signal of non-public input port, and output terminal drives multiple modules.
6. according to claim 1ly it is characterized in that for the area-optimized priority resource share method of FPGA, described the arithmetical operation that there is no public port carried out to shared step, comprising:
Two or more arithmetical operation mesh mergings that first Mei Zu mutual exclusion branch can be merged are an arithmetical operation, and two input ends add respectively a mux and select to drive signal, and output terminal drives multiple modules.
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| CN105930609A (en) * | 2016-05-04 | 2016-09-07 | 华中科技大学 | FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation |
| CN111027267A (en) * | 2019-11-13 | 2020-04-17 | 广东高云半导体科技股份有限公司 | Method, device and system for realizing optimization of adder in FPGA (field programmable Gate array) logic synthesis |
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| CN104809302A (en) * | 2015-05-07 | 2015-07-29 | 上海安路信息科技有限公司 | Resource sharing method and resource sharing system thereof in RTL (Register Transfer Level) circuit synthesis |
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| CN105930609A (en) * | 2016-05-04 | 2016-09-07 | 华中科技大学 | FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation |
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| CN111027267A (en) * | 2019-11-13 | 2020-04-17 | 广东高云半导体科技股份有限公司 | Method, device and system for realizing optimization of adder in FPGA (field programmable Gate array) logic synthesis |
| CN111027267B (en) * | 2019-11-13 | 2021-01-19 | 广东高云半导体科技股份有限公司 | Method, device and system for realizing optimization of adder in FPGA (field programmable Gate array) logic synthesis |
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