CN105930609A - FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation - Google Patents
FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Abstract
The invention discloses a FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation. The FPGA time sequence optimization method comprises the following steps: carrying out assembly line design on the FPGA; judging whether a path of which the total time delay exceeds a time delay threshold value [Delta] is in the presence or not; judging whether a specific value k of logic time delay and wiring time delay in a target path is greater than or equal to a time delay proportion threshold value [Epsilon] or not; setting an algorithm in an algorithm module corresponding to the target path as a method of exhaustion, and storing all possible calculation results of the algorithm module in a read-only memory; and resetting the maximum fanout of the FPGA until the maximum value of the total time delay of all paths is smaller than or equal to the time delay threshold value [Delta]. Through a logic optimization method, the problem that the assembly line design can not be used for carrying out optimization due to feedback or iteration operation is solved. The method stores all possible calculation results in the read-only memory, so that logic series in the path are reduced by the method of exhaustion, and the real-time processing efficiency of the FPGA is improved.
Description
Technical field
The invention belongs to field programmable gate array (FPGA) and signal Real-time demodulation field, more specifically
Ground, relates to a kind of FPGA timing optimization method for coherent demodulation.
Background technology
Use advanced modulation formats and coherent reception mode to promote optical fiber telecommunications system transmission capacity, become
For one of mainstream technology scheme.During coherent reception, signal inevitably sustains damage, bag
Include dispersion, polarization mode dispersion, frequency shift (FS) and phase noise etc..The coherent receiver of prior art
Digital Signal Processing block diagram is as it is shown in figure 1, this system includes optical mixer unit, balanced detector, ADC
And FPGA, wherein the outfan of optical mixer unit connects the input of balanced detector, balanced detector
Outfan connect the input of ADC, the outfan of ADC connects FPGA.At digital signal
Reason FPGA unit include again serioparallel exchange, dispersion compensation, polarization demultiplexing, frequency deviation compensate and
The functional modules such as phase noise compensation, wherein serioparallel exchange outfan connects dispersion compensation input, color
Dissipating and compensate outfan connection polarization demultiplexing input, polarization demultiplexing outfan connects frequency deviation and compensates defeated
Entering end, frequency deviation compensates outfan and connects phase noise compensation input.The optical signal of input mixes through light
Frequently device, obtains after balanced detector simulating I, Q signal, is then passed through ADC sampling and obtains numeral letter
Number, by serioparallel exchange, high-speed serial signals is converted into speed parallel signals, the demodulation (color of this signal
Dissipate compensations, polarization demultiplexing, frequency deviation compensation, phase noise compensation) it is placed in FPGA and carries out.By
In field programmable gate array (FPGA), there is stronger handling capacity and character more flexibly, generally
Use the platform that FPGA designs as coherent demodulation system.
When FPGA carries out Real-time demodulation to signal, hardware handles speed " bottleneck " can be faced, thus
The process that realizes causing real time algorithm is obstructed.And the parallel processing of FPGA and time FPGA is carried out
Sequence optimizes, it is possible to solve this problem.The development process of digital information processing system based on FPGA
As in figure 2 it is shown, comprise: parts selection, design input, functional simulation, comprehensively, optimize, realize
Generate and several parts such as code stream download with placement-and-routing, code stream.Parts selection refers to according to system
Process in real time frequency, resource, the cost etc. of complexity and required FPGA are estimated, and select
Suitably FPGA model；Design input refers to set required algorithm with software development form
Meter exploitation；Functional simulation refers to the circuit of user's design is carried out functional verification, and the result of emulation is with literary composition
Part and waveform export；Comprehensively refer to be converted into the description of senior level the description of rudimentary level；
Optimize and refer to that FPGA carries out the pipeline design, logic optimization or Wiring optimization to be processed in real time to meet
The demand of frequency；Carry out subsequently realizing downloading then complete with placement-and-routing, code stream generation and code stream
The design of FPGA.
Wherein, what the quality of optimization can affect FPGA processes frequency in real time.But, prior art
FPGA algoritic module have employed substantial amounts of on-the-spot calculating method (according to the flow scheme design circuit of certain algorithm,
This circuit, for input signal carries out computing, exports the result after computing), the method realizes the way of escape
Logic progression in footpath is more, and logical time delay is longer, operation when causing FPGA to realize real time algorithm
Inefficient.Such as Amado, article " the Clock and that S.B. etc. is published on SPIE for 2014
Carrier recovery in high-speed coherent optical communication systems " (" at a high speed
Coherent optical communication system realizes clock and carrier auxiliary "), owing to the method does not takes effective way pair
FPGA carries out logic optimization and Wiring optimization, is only capable of realizing the relevant solution of 1.25Gb/s QPSK signal
Adjust.
Summary of the invention
For disadvantages described above and the Improvement requirement of prior art, the invention provides a kind of for relevant solution
The FPGA timing optimization method adjusted, its object is to by the pipeline design, logic optimization and cloth
Line optimizes, and that improves FPGA processes frequency in real time, thus realizes the demodulation of higher rate signal.
According to one aspect of the present invention, it is provided that a kind of FPGA timing optimization for coherent demodulation
Method, comprises the following steps:
S1. FPGA is carried out the pipeline design；
S2. judge whether that total time delay exceedes the path of delay threshold δ, the most then choose this path
As destination path, and enter step S3, if it is not, then timing optimization terminates, wherein, described always prolong
Time by logical time delay and wiring time delay form；
S3. judge in destination path, whether logical time delay and the ratio k connecting up time delay are more than or equal to time delay ratio
Example threshold epsilon, the most then enter step S4, if it is not, then enter S5；
S4. the algorithm in described destination path correspondence algoritic module is set to the method for exhaustion, and by this algorithm
The all possible result of calculation of module is stored in read only memory, comprehensive wiring again, returns step
S2；
S5. the maximum fan-out of FPGA is reset until the maximum of the total time delay in all paths is less than or equal to
Delay threshold δ, again comprehensive wiring, return step S2.
Preferably, described time delay proportion threshold value ε is 1:4～2:3.
Preferably, described step S5 particularly as follows:
S51. i=1, k are madeiFor current maximum fan-out, AiBe maximum fan-out be kiTime, corresponding all roads
The maximum of the total time delay in footpath；
S52. k is madei+1=[ki/ 2], comprehensive wiring again, wherein, ki+1Attach most importance to newly-installed maximum fan-out,
[] expression rounds downwards；
If S53. Ai+1≤ δ, then return step S2, otherwise i=i+1, return step S52.
Preferably, described S1 is particularly as follows: judge whether to exist in overall circuit feedback circuit or iteration
Computing, is to keep constant, otherwise chooses the combinational logic circuit in overall circuit, and at described group
Between logic circuit adjacent in combinational logic circuit, depositor is set, for storing the logic electricity of previous stage
The result of calculation on road.
Preferably, described delay threshold δ≤1/f, f be FPGA process frequency in real time.
In general, by the contemplated above technical scheme of the present invention compared with prior art, pass through
The pipeline design, logical time delay and the optimization of wiring time delay, improve FPGA and process frequency in real time,
Can obtain following beneficial effect:
1, all possible for this algoritic module result of calculation is stored in read only memory, uses exhaustive
Method decreases the logic progression in path, thus solve because have feedback or interative computation and can not
The problem being optimized by the pipeline design, improve FPGA processes frequency in real time；
2, by limiting the maximum fan-out of FPGA, thus solve and affect FPGA cloth because fan-out is excessive
Line stabilization causes connecting up the problem that time delay is bigger so that device load reduces, and improves FPGA's
Process frequency in real time；
3, which needs preferentially to use by the current FPGA of ratio in judgement of logical time delay with wiring time delay
Step is optimized, thus chooses technological means more efficiently, improves the effect of optimization；
4, the method that have employed the pipeline design, between logic circuit adjacent in combinational logic circuit
Arranging depositor, complex logic feature operation is divided into multiple cycle to be completed, and improves handling up of data
Amount, thus improve FPGA process frequency in real time.
Accompanying drawing explanation
Fig. 1 is coherent receiver Digital Signal Processing block diagram；
Fig. 2 is the development process figure of FPGA；
Fig. 3 is FPGA timing optimization method flow chart of the present invention；
Fig. 4 is not use streamline schematic diagram；
Fig. 5 is to use streamline schematic diagram；
Fig. 6 is that in the frequency deviation backoff algorithm that the embodiment of the present invention 1 provides, multistage complex multiplication does not uses stream
Waterline schematic diagram；
Fig. 7 is that in the frequency deviation backoff algorithm that the embodiment of the present invention 1 provides, multistage complex multiplication uses flowing water
Line schematic diagram；
Fig. 8 is the on-the-spot calculating method view that the embodiment of the present invention 1 provides；
Fig. 9 is the method for exhaustion Design view that the embodiment of the present invention 1 provides；
Figure 10 is the fan-out that provides of the embodiment of the present invention 1 hardware circuit implementation when being 26；
Figure 11 is the fan-out that provides of the embodiment of the present invention 1 hardware circuit implementation when being 13.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing
And embodiment, the present invention is further elaborated.Should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.Additionally, it is disclosed below
Just may be used as long as technical characteristic involved in each embodiment of the present invention does not constitutes conflict each other
To be mutually combined.
After the designing and developing and complete with comprehensive wiring of FPGA, FPGA processes frequency in real time by path
Total delay, total time delay in each path by logical time delay and wiring time delay form.The present invention carries
Supplied a kind of FPGA timing optimization method for coherent demodulation, with reduce path logical time delay and
Wiring time delay, as it is shown on figure 3, comprise the following steps:
S1. the pipeline design
Judge whether overall circuit exists feedback circuit or interative computation, be, keep constant, no
Then choose the combinational logic circuit in overall circuit, and logic adjacent in described combinational logic circuit
Depositor is set between circuit, for storing the result of calculation of the logic circuit of previous stage；
The method shortens the signal time by overall circuit within a cycle, so that FPGA
The signal frequency that processes in real time be improved.If Fig. 4 is the overall electricity being provided without the pipeline design
Road schematic diagram, it can be seen that data through two logic circuits (logic circuit 1, logic circuit 2, and
The time delay of each logic circuit is a) to need 2a, then a clock (CLK) in the cycle total by this
The time delay of body circuit is 2a.Fig. 5 is the overall circuit schematic diagram using streamline, at each point
Insert depositor in the middle of level (logic circuit 1, logic circuit 2), then pass through first clock cycle
Logic circuit 1, the next clock cycle, then passing through within a clock cycle should through logic circuit 2
Overall circuit time delay is a.Use the pipeline design to decrease the process time delay of overall circuit, thus improve
FPGA processes frequency in real time.
S2. judge whether that total time delay exceedes the path of delay threshold δ, be, choose this path conduct
Destination path, enters step S3, and otherwise timing optimization terminates；
S3. use the condition of streamline be whole data process be single current to, i.e. overall circuit does not has
Feedback circuit or interative computation, otherwise can not use the scheme of the pipeline design to be optimized.Work as mesh
Total time delay in mark path exceedes delay threshold δ (δ≤1/f, f are FPGA process frequency in real time), and
And logical time delay and the ratio k of wiring time delay are more than time delay proportion threshold value ε in this path, ε is 1:4～2:3,
Its comprehensive out circuit logic progression may be more than tens of level, needs that destination path is carried out logic excellent
Change；
S4. logic optimization
Algorithm in destination path correspondence algoritic module is set to the method for exhaustion, will this algoritic module institute
Possible result of calculation is stored in read only memory, when the method for exhaustion calculates, it is only necessary to from input letter
Number value map the address of corresponding result of calculation in read only memory, further take out the result of calculation of its correspondence,
Thus decrease logic progression.Again, after comprehensive wiring, the time delay in each path can change, now
Return S2, re-start inspection；
Such as, if the formula of the algorithm of algoritic module is y=x originally4, wherein x is input signal,
X=1,2,3,4 or 5, y is output signal, and y to be obtained is firstly the need of calculating x × x=x2, then
By x2×x2=y obtains y.If the algorithm in this algoritic module being set to the method for exhaustion, it is only necessary to can
Obtainable result 1,16,81,256,625 is stored in read only memory, when carrying out at signal
During reason, directly according to input signal x, a step corresponding result can be taken out.
S5. Wiring optimization
Wiring time delay is in close relations with fan-out, and fan-out (Fanout) refers to that module is directly connected to the subordinate driven
The number of module, many fan-outs are commonly referred to as individual node and drive multiple lower logical devices.If fan
Go out numerical value and reach more than tens of, now can affect the stability of FPGA wiring, directly translate into wiring
Time delay is relatively big, is unfavorable for timing closure；
In such scheme, use synthesis tool can limit maximum fan-out, combine after exceeding maximum fan-out value
Depositor will automatically be replicated by conjunction instrument, thus realize Wiring optimization.
Reset the maximum fan-out of FPGA until the maximum of the total time delay in all paths is less than or equal to prolonging
Time threshold value δ, again after comprehensive wiring, the time delay in each path can change, and now returns S2, weight
Newly test.The method particularly as follows:
S51. i=1, k are madeiFor current maximum fan-out, AiBe maximum fan-out be kiTime, corresponding all roads
The maximum of the total time delay in footpath；
S52. k is madei+1=[ki/ 2], comprehensive wiring again；
If S53. Ai+1≤ δ, then enter next step, otherwise i=i+1, returns step S52.
Embodiment 1
The present embodiment uses FPGA 10GBaud QPSK signal carries out coherent demodulation and (include frequency
Offset compensation and phase noise compensation), the development process of FPGA uses 32 tunnel parallel processings, then
The real time signal processing frequency of FPGA should reach 10G/32=312.5MHz (now threshold value δ is 3.2ns)
Above, then the timing optimization method of the present embodiment comprises the following steps:
S1. the pipeline design:
Judge whether overall circuit exists feedback circuit or interative computation.If Fig. 6 is the present embodiment
The QPSK signal frequency deviation compensation provided is overall with the multistage complex multiplication in phase noise compensation algorithm
Circuit, this overall circuit includes 3 logic circuits (i.e. 3 complex multiplier DSP48 unit), should
There is not feedback circuit or interative computation in combinational logic circuit, the method for the pipeline design can be used to enter
Row optimizes.Can be seen that, before optimizing, the complex multiplication of each level logic circuit postponed as a, a clock week
Phase is interior is 3a by this overall circuit time delay.
Between neighbor logic circuit, insert depositor, above-mentioned overall circuit be divide into 3 grades.Fig. 7
Overall circuit for the present embodiment makes the schematic diagram after being optimized in aforementioned manners, it can be seen that each two
Increase a depositor between neighbor logic circuit and be used for storing the result of the logic circuit of previous stage,
It is a by this overall circuit time delay in one clock cycle.
Use the pipeline design can reduce three complex multipliers and be grouped the bigger of combinational logic circuit generation
Time delay, makes the logical operation substep of complexity complete, thus improve FPGA process frequency in real time.
S2. judge whether that total time delay exceedes the path of delay threshold δ, due to the present embodiment FPGA
Real time signal processing frequency f should reach more than 312.5MHz, delay threshold δ and be necessarily less than equal to 1/f
(i.e. 3.2ns).Total time delay before optimization is 5.038ns, the most first finds out the target road that this total time delay is corresponding
The details in footpath, now this destination path correspondence Unwrap module, as shown in table 1:
The delay path details of table 1Unwrap module
S3. logical time delay and ratio k ≈ 0.75 of wiring time delay in this destination path, due to this destination path
K exceeded 2:3, then need to carry out logic optimization.
S4. the logic before Fig. 8 optimizes for the on-the-spot calculating method design Unwrap module that the present embodiment provides
Structure chart, it is known that using on-the-spot calculating method electrical combination logic progression is 14 grades, causes fpga logic
Time delay is bigger than normal.The algorithm in algoritic module corresponding by described destination path (Unwrap module) is arranged
For the method for exhaustion, will all possible result of calculation of this algoritic module be stored in read only memory.Fig. 8
For according to said method optimize after Unwrap module diagram, when this module carries out real time signal processing
Time, the value of input signal maps corresponding address in read only memory, then takes out calculating knot from this address
Really, the method for exhaustion can reduce the logic progression that algoritic module is corresponding.It may be seen that optimize in Fig. 9
Logic progression within rear combination logic greatly reduces, and reduces to 3 grades from 14 grades, due to logical time delay
It is directly proportional to logic progression, it may thus be appreciated that logical time delay is obviously reduced.
After logic optimization, need comprehensive wiring again herein, and judge whether that still suffering from total time delay surpasses
Cross the path of delay threshold δ.Now, the path still having total time delay to be 3.547ns, as shown in table 2,
Due to 3.547ns >=δ, and ratio k=0.08 of logical time delay corresponding to this path and wiring time delay, therefore
Need to carry out next step, i.e. Wiring optimization.
Table 2 time delay specifying information table
S4. from table 2 it can be seen that the current maximum fan-out of FPGA is 500, and high fan-out is to cause cloth
The main cause that line time delay is excessive, can realize Wiring optimization by reducing fan-out.If Figure 10 is fan-out limit
It is made as hardware circuit implementation when 26, it can be seen that depositor 1 needs to drive load 1, load 2 ... load
26 (i.e. elementary logic circuit unit), its load driven is many and causes wiring delay.When limiting
(fan-out is limited to 13, then certain signal driver part is less than 13) after big fan-out, Tu11Shi
Hardware circuit implementation when fan-out is 13, it can be seen that it increases a depositor 2 makes load be divided into two parts,
Depositor 1 drives load to be load 1, load 2 ... load 13, and depositor 2 drives load for load
14, load 15 ... load 26, the minimizing of the number of loads that each depositor drives makes wiring delay drop
Low, thus improve FPGA process frequency in real time.
Table 3 is that the QPSK signal frequency deviation that the present embodiment provides compensates and phase noise compensation algorithm designs
Middle maximum fan-out and the relation of wiring delay, when fan-out reduces, this depositor drives number of loads to subtract
Little, its wiring time delay reduces the most accordingly, and the frequency that processes in real time of FPGA is improved.By data in table
Understanding along with the reduction of fan-out, its wiring time delay reduces the most therewith.
The maximum fan-out of table 3 and wiring time delay
In concrete operations, can be by maximum fan-out value being halved, and observe the total of all paths every time
The change of the maximum of time delay, such as:
S51. i=1, k are madeiFor current maximum fan-out, AiBe maximum fan-out be kiTime, corresponding all roads
The maximum of the total time delay in footpath；
S52. k is madei+1=[ki/ 2], comprehensive wiring again；
If S53. Ai+1≤ δ, then enter next step, otherwise i=i+1, returns step S52.
After table 4 carries out the pipeline design, logic optimization for the present embodiment and limits maximum fan-out, when
Front maximum fan-out and temporal constraint and running frequency relation, it is known that by the inventive method to FPGA
Carry out that timing optimization significantly improves FPGA processes frequency in real time, and now this FPGA's is all
Total time delay in path is respectively less than delay threshold, then timing optimization terminates.
The current fan-out size of table 4 and temporal constraint and running frequency relation
| Fan-out limits | 300 | 150 | 75 | 37 | 18 | 9 |
| Temporal constraint (ns) | 3.5 | 3.4 | 3.3 | 3.3 | 3.1 | 3 |
| Running frequency (MHZ) | 285.71 | 294.12 | 303.03 | 303.03 | 322.58 | 333.33 |
As it will be easily appreciated by one skilled in the art that and the foregoing is only presently preferred embodiments of the present invention,
Not in order to limit the present invention, all made within the spirit and principles in the present invention any amendment, etc.
With replacement and improvement etc., should be included within the scope of the present invention.
Claims (5)
1. the FPGA timing optimization method for coherent demodulation, it is characterised in that include following
Step:
S1. FPGA is carried out the pipeline design；
S2. judge whether that total time delay exceedes the path of delay threshold δ, the most then choose this path
As destination path, and enter step S3, if it is not, then timing optimization terminates, wherein, described always prolong
Time by logical time delay and wiring time delay form；
S3. judge in destination path, whether logical time delay and the ratio k connecting up time delay are more than or equal to time delay ratio
Example threshold epsilon, the most then enter step S4, if it is not, then enter S5；
S4. the algorithm in described destination path correspondence algoritic module is set to the method for exhaustion, and by this algorithm
The all possible result of calculation of module is stored in read only memory, returns step S2；
S5. the maximum fan-out of FPGA is reset until the maximum of the total time delay in all paths is less than or equal to
Delay threshold δ, returns step S2.
2. FPGA timing optimization method as claimed in claim 1, it is characterised in that described S1
Particularly as follows: judge whether overall circuit exists feedback circuit or interative computation, it is, keeps constant,
Otherwise choose the combinational logic circuit in overall circuit, and adjacent patrolling in described combinational logic circuit
Collect and between circuit, depositor is set.
3. FPGA timing optimization method as claimed in claim 1, it is characterised in that described time delay
Proportion threshold value ε is 1:4～2:3.
4. FPGA timing optimization method as claimed in claim 1, it is characterised in that described step
S5 particularly as follows:
S51. i=1, k are madeiFor current maximum fan-out, AiBe maximum fan-out be kiTime corresponding all paths
The maximum of total time delay；
S52. k is madei+1=[ki/ 2], comprehensive wiring again, wherein, ki+1Attach most importance to newly-installed maximum fan-out,
[] expression rounds downwards；
If S53. Ai+1≤ δ, then return step S2, otherwise i=i+1, return step S52.
5. FPGA timing optimization method as claimed in claim 1, it is characterised in that described time delay
Threshold value δ≤1/f, f be FPGA process frequency in real time.
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| CN110442885B (en) * | 2018-05-02 | 2023-04-07 | 中国科学院微电子研究所 | Optimization method and device of sub-threshold combinational logic circuit |
| CN112685982A (en) * | 2020-12-31 | 2021-04-20 | 海光信息技术股份有限公司 | Circuit detection method, circuit detection device, storage medium and electronic equipment |
| CN113486612A (en) * | 2021-06-29 | 2021-10-08 | 海光信息技术股份有限公司 | Integrated circuit design method, device, electronic equipment and readable storage medium |
| CN113486612B (en) * | 2021-06-29 | 2023-06-06 | 海光信息技术股份有限公司 | Integrated circuit design method, apparatus, electronic device, and readable storage medium |
| CN113781354A (en) * | 2021-09-18 | 2021-12-10 | 北京环境特性研究所 | Image noise point suppression method and device, computing equipment and storage medium |
| CN113781354B (en) * | 2021-09-18 | 2023-09-22 | 北京环境特性研究所 | Image noise suppression method, device, computing equipment and storage medium |
| CN115392166A (en) * | 2022-10-24 | 2022-11-25 | 北京智芯微电子科技有限公司 | Transistor width determination method and device, electronic equipment and medium |
| CN115392166B (en) * | 2022-10-24 | 2023-01-20 | 北京智芯微电子科技有限公司 | Transistor width determination method and device, electronic equipment and medium |
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