CN113781354B - Image noise suppression method, device, computing equipment and storage medium - Google Patents
Image noise suppression method, device, computing equipment and storage medium Download PDFInfo
- Publication number
- CN113781354B CN113781354B CN202111096686.5A CN202111096686A CN113781354B CN 113781354 B CN113781354 B CN 113781354B CN 202111096686 A CN202111096686 A CN 202111096686A CN 113781354 B CN113781354 B CN 113781354B
- Authority
- CN
- China
- Prior art keywords
- image processing
- timing
- constraint
- path
- time sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 230000001629 suppression Effects 0.000 title claims abstract description 24
- 238000012545 processing Methods 0.000 claims abstract description 89
- 238000005516 engineering process Methods 0.000 claims description 14
- 238000004590 computer program Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000004458 analytical method Methods 0.000 claims description 8
- 230000006870 function Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000012300 Sequence Analysis Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G06T5/70—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
Abstract
The invention provides an image noise suppression method, an image noise suppression device, computing equipment and a storage medium, wherein the method comprises the following steps: determining whether a timing violation exists in an image processing program executed by the FPGA; if the timing violations exist, determining paths with the timing violations, and carrying out timing constraint on the paths with the timing violations; if no time sequence violation exists, determining a plurality of image processing paths related to image processing, determining a target image processing path with longest delay from the plurality of image processing paths, determining a resource allowance of a register corresponding to the target image processing path, and keeping the delay of the target image processing path not larger than a set delay threshold according to the resource allowance. According to the scheme, the image noise can be suppressed.
Description
Technical Field
The embodiment of the invention relates to the technical field of image processing, in particular to an image noise suppression method, an image noise suppression device, computing equipment and a storage medium.
Background
In an image processing system, an FPGA (Field Programmable Gate Array ) is flexibly configured due to its reconfigurability, and thus is generally used as a core processing chip for image processing. However, in the image processing system based on the FPGA, since the FPGA may have timing violations, noise phenomenon may occur in the image processed by the FPGA, which affects not only visual impression but also recognition and processing of the target based on the image.
At present, a related inhibition solution method does not exist based on the problem of image noise caused by FPGA. In view of this, there is a need to provide an image noise suppression method for an FPGA-based image processing system.
Disclosure of Invention
The embodiment of the invention provides an image noise suppression method, an image noise suppression device, computing equipment and a storage medium, which can suppress image noise.
In a first aspect, an embodiment of the present invention provides an image noise suppression method, including:
s1: determining whether a timing violation exists in an image processing program executed by the FPGA; if the timing violation exists, S2 is executed; if no timing violation exists, executing S3-S5;
s2: determining paths with timing violations, and performing timing constraint on the paths with the timing violations;
s3: determining a plurality of image processing paths associated with image processing;
s4: determining a target image processing path with longest delay from the plurality of image processing paths;
s5: and determining a resource allowance of a register corresponding to the target image processing path, and according to the resource allowance, setting the delay of the target image processing path to be not more than a delay threshold.
Preferably, after the determining that the path with the timing violation exists, before the performing timing constraint on the path with the timing violation exists, the method further includes:
determining a cause of the timing violation for the path where the timing violation exists; the reasons include not adding at least one of a period constraint to the pixel clock of the input image, a logic level greater than a set level threshold, and a signal fan-out coefficient greater than a set fan-out threshold.
Preferably, the reasons include not adding a period constraint to the pixel clock of the input image;
the timing constraint on the paths with timing violations comprises: and determining a clock signal corresponding to the path with the timing violation, and adding the period constraint added to the clock signal into a constraint file.
Preferably, the cause includes the logical progression being greater than a set progression threshold;
the timing constraint on the paths with timing violations comprises:
determining whether a target segment program corresponding to the path with the time sequence violation in the image processing program is encoded by adopting a pipeline technology, if not, receiving a modified image processing program, wherein the target segment program in the modified image processing program is encoded by adopting the pipeline technology;
and/or the number of the groups of groups,
determining whether an if statement nesting layer number is larger than a set layer number threshold value in a target section program corresponding to the path with the time sequence violation in the image processing program, if so, receiving a modified image processing program, wherein the if statement in the target section program corresponding to the path with the time sequence violation in the modified image processing program is replaced by a case statement.
Preferably, the cause comprises the signal fanout coefficient being greater than a set fanout threshold;
the timing constraint on the paths with timing violations comprises:
copying the generation logic of the driving signals in the paths with the time sequence violations so that at least two paths of driving signals with the same frequency and the same phase obtained by copying drive circuits in the paths with the time sequence violations;
and/or the number of the groups of groups,
determining relevant logic in the path where the timing violation exists, and performing region constraint on the relevant logic to place the relevant logic in the same region.
Preferably, after the timing constraint is performed on the path with the timing violation, the method further includes:
compiling the image processing program subjected to time sequence constraint, determining whether time sequence violations in the compiled image processing program are eliminated, if not, deleting a netlist file generated in the compiling process, and executing S2 until the time sequence violations in the compiled image processing program are eliminated.
Preferably, the delaying the target image processing path according to the resource margin is not greater than a set delay threshold, including:
when the resource allowance is not smaller than the set resource threshold, carrying out layout wiring constraint on the target image processing path, so that after the layout wiring constraint, the delay of the target image processing path is not larger than the set delay threshold; the delay threshold is 0.5 clock cycles.
In a second aspect, an embodiment of the present invention further provides an image noise suppression apparatus, including:
a timing analysis unit for determining whether a timing violation exists in an image processing program executed by the FPGA; if the time sequence violations exist, triggering the time sequence constraint unit to execute corresponding operations; if no timing violation exists, triggering the layout wiring constraint unit to execute corresponding operation;
the time sequence constraint unit is used for determining paths with time sequence violations and performing time sequence constraint on the paths with the time sequence violations;
the layout wiring constraint unit is used for determining a plurality of image processing paths related to image processing; determining a target image processing path with longest delay from the plurality of image processing paths; and determining a resource allowance of a register corresponding to the target image processing path, and according to the resource allowance, setting the delay of the target image processing path to be not more than a delay threshold.
In a third aspect, an embodiment of the present invention further provides a computing device, including a memory and a processor, where the memory stores a computer program, and the processor implements a method according to any embodiment of the present specification when executing the computer program.
In a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform a method according to any of the embodiments of the present specification.
The embodiment of the invention provides an image noise suppression method, an image noise suppression device, a computing device and a storage medium, which are used for determining whether a timing violation exists in an image processing program executed by an FPGA (field programmable gate array) so as to conduct timing constraint when the timing violation exists, and when the timing violation does not exist, noise is probably caused by excessively high delay of an image processing path related to image processing, so that the delay of a target image processing path is reduced by analyzing the resource margin of the target image processing path with the longest delay so as to enable the delay of the target image processing path to be not larger than a set delay threshold, and therefore, the image noise caused by the FPGA can be suppressed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for suppressing image noise according to an embodiment of the present invention;
FIG. 2 is a hardware architecture diagram of a computing device according to one embodiment of the present invention;
fig. 3 is a block diagram of an image noise suppression device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
In the FPGA chip, netlist information is generated each time the image processing program is compiled, and the netlist is used for recording the layout and wiring conditions inside the FPGA in the compiling process. Each time the image processing program is compiled, the layout and wiring conditions inside the FPGA may be different, and the FPGA includes a plurality of banks inside, each bank includes a plurality of registers, and signals are transmitted between the registers. Each register has a setup time and a hold time, and if the setup time or the hold time of the register is not satisfactory, a timing violation is determined to exist. If a timing violation occurs, the data transmission may be erroneous, resulting in noise in the image data. Based on the above, when the image noise is caused by the timing violation when the FPGA executes the image processing program, the timing constraint needs to be performed on the timing violation, and if the timing violation does not exist when the FPGA executes the image processing program, the cause of the image noise needs to be further analyzed, so as to further inhibit.
Specific implementations of the above concepts are described below.
Referring to fig. 1, an embodiment of the present invention provides an image noise suppression method, which includes:
s1: determining whether a timing violation exists in an image processing program executed by the FPGA; if the timing violation exists, S2 is executed; if no timing violation exists, executing S3-S5;
s2: determining paths with timing violations, and performing timing constraint on the paths with the timing violations;
s3: determining a plurality of image processing paths associated with image processing;
s4: determining a target image processing path with longest delay from the plurality of image processing paths;
s5: and determining a resource allowance of a register corresponding to the target image processing path, and according to the resource allowance, setting the delay of the target image processing path to be not more than a delay threshold.
In the embodiment of the invention, whether the timing violations exist in the image processing program executed by the FPGA is determined, so that the timing constraint is carried out when the timing violations exist, and when the timing violations do not exist, the noise is probably caused by the fact that the delay of the image processing path related to the image processing is too high, so that the delay of the target image processing path is reduced by analyzing the resource margin of the target image processing path with the longest delay, so that the delay of the target image processing path is not more than the set delay threshold, and the image noise caused by the FPGA can be suppressed.
The manner in which the individual steps shown in fig. 1 are performed is described below.
First, for S1, it is determined whether there is a timing violation of an image processing program executed by the FPGA.
Timing violations are classified into two types, namely setup time violations and hold time violations. The setup time refers to the time that data must remain stable before the clock rising edge arrives, and the hold time refers to the time that data must remain stable after the clock rising edge arrives. And (3) establishing that the time margin is smaller than 0 or the holding time margin is smaller than 0, namely generating a time sequence violation, and indicating that the image data is wrong in the transmission process of the FPGA, so that the noise of the image processed by the FPGA is generated.
In the embodiment of the present invention, in step S1, it is determined whether the image processing program has a timing violation, and static timing analysis is performed on the image processing program processed by the FPGA by using timing analysis software to determine the setup time and the hold time on each path.
The Timing analysis software may use Static Timing in ISE software, and by starting a Timing Analyzer, an accurate delay may be obtained in the Static Timing after PAR (plane And Route) is integrated, and a critical path related to image processing may be determined in a Timing report.
Then, for S2, a path for which a timing violation exists is determined, and timing constraint is performed on the path for which the timing violation exists.
In the embodiment of the invention, if the setup time margin is smaller than 0 or the hold time margin is smaller than 0, determining that the path has a timing violation.
When a timing violation exists on a certain path, timing constraint needs to be performed on the path with the timing violation, and analysis needs to be performed on the reason of the timing violation generated by the path, so after the path with the timing violation is determined, and before the timing constraint is performed on the path with the timing violation, the method further comprises: determining a cause of the timing violation for the path where the timing violation exists; the reasons include not adding at least one of a period constraint to the pixel clock of the input image, a logic level greater than a set level threshold, and a signal fan-out coefficient greater than a set fan-out threshold.
The timing constraints corresponding to the above three reasons are described below, respectively.
1. The reasons include that no period constraint is added to the pixel clock of the input image.
Then the timing constraint on the paths with timing violations in this step S2 may include: and determining a clock signal corresponding to the path with the timing violation, and adding the period constraint added to the clock signal into a constraint file.
The period constraint is to constrain the period of the clock to ensure that the timing of all synchronous components within the clock region meet the requirements. When the image processing program is programmed, not all clocks are subjected to period constraint, and when time sequence analysis is performed, if time sequence violations are caused by that a certain clock is not added with the period constraint, a clock signal which enables a path to generate the time sequence violations can be determined according to time sequence analysis software, and the period constraint can be added to the clock signal at the moment so as to ensure that the clock signal can meet the time sequence requirements. Wherein the added period constraint is added to the constraint file to implement the constraint on the clock signal.
2. The reasons include that the logical progression is greater than the set progression threshold.
In FPGA design, the set progression threshold may be set based on empirical values. If the logic level is greater than the set level threshold, the code of the image processing program needs to be modified to improve the performance, and the solution may include at least two kinds of:
first kind: determining whether a target segment program corresponding to the path with the timing violation in the image processing program is encoded by adopting a pipeline technology, and if not, receiving a modified image processing program, wherein the target segment program in the modified image processing program is encoded by adopting the pipeline technology.
The original logic structure can be simplified by using the pipeline technology to encode and inserting the register into the combinational logic. Therefore, the target segment program corresponding to the path with the timing violation can be located, the target segment program is determined to be encoded by adopting the pipeline technology, if yes, other solutions are selected, if not, the modified image processing program is received, the modified image processing program can be obtained by manual encoding, for example, when the target segment program is determined not to be encoded by adopting the pipeline technology, a user is prompted to modify the image processing program, the modified image processing program is input after the user modification is completed, and the target segment program is encoded by adopting the pipeline technology.
Second kind: determining whether an if statement nesting layer number of the target segment program corresponding to the path with the time sequence violation in the image processing program is larger than a set layer number threshold, if so, receiving a modified image processing program, wherein the if statement in the target segment program corresponding to the path with the time sequence violation in the modified image processing program is replaced by a case statement.
Compared with case sentences, if sentences have better readability, the order of conditional sentences in the case sentences is unimportant, the execution process of the case sentences is closer to a parallel mode, the if sentences have priority, a plurality of conditions are needed to be judged in one clock period, and the problem of time sequence violations is easily caused, so that the conditional sentences in the target section program are replaced by the case sentences, the nesting level of the if sentences is reduced, and the problem of the time sequence violations can be solved.
3. The reasons include that the signal fanout coefficient is greater than the set fanout threshold.
The fan-out coefficient refers to the number of gates of the same type driven by the output of one gate, or the load capacity. The fan-out coefficient of the gate is typically 8, and the fan-out coefficient of the driver can reach 25. The fan-out factor represents the loading capability of the gate. If the fan-out coefficient is too high, the signal transmission path is prolonged, wiring delay is too high, and a timing violation phenomenon occurs. For this case, it can be solved by at least two methods:
first kind: and copying the generation logic of the driving signals in the paths with the time sequence violations so that at least two paths of the driving signals with the same frequency and the same phase obtained by copying drive circuits in the paths with the time sequence violations.
If a certain driving signal needs to drive many cells at the later stage, the fan-out of the driving signal is very large, then in order to increase the driving capability of the driving signal, a method is to insert multiple stages of buffers, but this can increase the driving capability, but also increase the path delay of the signal. In order to avoid the situation, the generation logic of the driving signal can be duplicated, and a plurality of driving signals with the same frequency and the same phase are used for driving a subsequent circuit, so that the fan-out of each path is reduced, the requirement of increasing the driving capability can be met without inserting a Buffer, and the path delay of the signal is saved.
In one embodiment of the invention, the objectives may be achieved by manual copying in HDL code or by setting in an integration tool.
Second kind: determining relevant logic in the path where the timing violation exists, and performing region constraint on the relevant logic to place the relevant logic in the same region.
Wherein, the area constraint can be performed by using the Floorplaning software to place the related logic in the same area, thereby solving the problem of timing violations.
In one embodiment of the present invention, after the above timing constraint is performed on the path with the timing violation, the method further includes: compiling the image processing program subjected to time sequence constraint, determining whether time sequence violations in the compiled image processing program are eliminated, if not, deleting a netlist file generated in the compiling process, and executing S2 until the time sequence violations in the compiled image processing program are eliminated.
If the time sequence violation condition still exists after compiling, the time sequence constraint needs to be carried out again, at the moment, the netlist information file needs to be deleted, the time sequence constraint is continued until the time sequence violation is eliminated after the deletion, and at the moment, the fact that the image noise point is restrained can be determined.
It should be noted that, after the timing violation problem is solved, in order to further ensure that the image noise is suppressed, S3-S5 may be further executed to further suppress the image noise by using S3-S5.
And finally, determining a plurality of image processing paths related to image processing according to the S3', determining a target image processing path with longest delay from the plurality of image processing paths according to the S4, determining a resource allowance of a register corresponding to the target image processing path according to the S5, and simultaneously describing that the delay of the target image processing path is not more than a set delay threshold according to the resource allowance.
When it is determined in S1 that the timing violation does not occur in the image processing program, then the noise may be generated because the critical path delay is too high, and thus a plurality of image processing paths related to the image processing need to be determined. It can be determined in the timing analysis software which paths are paths related to the image processing, i.e. which paths are paths for transmitting and processing the image data.
For each image processing path, backtracking can be performed from the output end of the image data, delay analysis is performed at the same time, the target image processing path with the largest delay is searched layer by layer, and the target image processing path with the largest delay can be used as a key path for generating noise points.
The reason for the excessively high delay of the target image processing path may include the following two cases:
case one: the resource allowance is insufficient;
and a second case: the placement and routing require constraints.
In order to determine whether the delay of the target image processing path is too high, it is necessary to determine whether the resource margin of the register corresponding to the target image processing path is not less than a set resource threshold, specifically, determine the register type at both ends of the target image processing path, for example, the register type is RAM, or, if the register type is RAM, determine whether the RAM resource margin in the Slice is sufficient, for example, determine whether the RAM resource margin in the Slice is not less than the set RAM resource threshold, if so, determine that the RAM resource margin in the Slice is sufficient. If the Slice type is the Slice type, determining whether the Slice resource allowance is enough, for example, determining whether the Slice resource allowance is not smaller than a set Slice resource threshold, if so, determining that the Slice resource allowance is enough.
When the resource allowance is insufficient, in the first case, the layout and wiring constraint cannot be performed at this time, so that the delay of the target image processing path related to the noise cannot be optimized, and the FPGA chip with richer resources needs to be replaced or the design is changed, so that the resource consumption is reduced.
When the resource allowance is enough, the second situation is the above, and the layout and wiring constraint is carried out on the target image processing path, so that after the layout and wiring constraint, the delay of the target image processing path is not more than the set delay threshold; the delay threshold is 0.5 clock cycles.
After solving the above two cases, the image noise caused by the FPGA can be suppressed.
As shown in fig. 2 and 3, an embodiment of the present invention provides an image noise suppression device. The apparatus embodiments may be implemented by software, or may be implemented by hardware or a combination of hardware and software. In terms of hardware, as shown in fig. 2, a hardware architecture diagram of a computing device where an image noise suppression apparatus provided in an embodiment of the present invention is located, where the computing device where the embodiment is located may include other hardware, such as a forwarding chip responsible for processing a packet, in addition to the processor, the memory, the network interface, and the nonvolatile memory shown in fig. 2. Taking a software implementation as an example, as shown in fig. 3, as a device in a logic sense, the device is formed by reading a corresponding computer program in a nonvolatile memory into a memory by a CPU of a computing device where the device is located. The image noise suppression device provided in this embodiment includes:
a timing analysis unit 301 for determining whether or not there is a timing violation of an image processing program executed by the FPGA; if the time sequence violations exist, triggering the time sequence constraint unit to execute corresponding operations; if no timing violation exists, triggering the layout wiring constraint unit to execute corresponding operation;
the timing constraint unit 302 is configured to determine a path with a timing violation, and perform timing constraint on the path with the timing violation;
the layout wiring constraint unit 303 is configured to determine a plurality of image processing paths related to image processing; determining a target image processing path with longest delay from the plurality of image processing paths; and determining a resource allowance of a register corresponding to the target image processing path, and according to the resource allowance, setting the delay of the target image processing path to be not more than a delay threshold.
In one embodiment of the present invention, after the determining the path with the timing violation, before the performing timing constraint on the path with the timing violation, the method further includes: determining a cause of the timing violation for the path where the timing violation exists; the reasons include not adding at least one of a period constraint to the pixel clock of the input image, a logic level greater than a set level threshold, and a signal fan-out coefficient greater than a set fan-out threshold.
In one embodiment of the invention, the reasons include not adding a period constraint to the pixel clock of the input image;
the timing constraint unit 302 specifically includes: and determining a clock signal corresponding to the path with the timing violation, and adding the period constraint added to the clock signal into a constraint file.
In one embodiment of the invention, the cause includes the logic level being greater than a set level threshold;
the timing constraint unit 302 specifically includes: determining whether a target segment program corresponding to the path with the time sequence violation in the image processing program is encoded by adopting a pipeline technology, if not, receiving a modified image processing program, wherein the target segment program in the modified image processing program is encoded by adopting the pipeline technology; and/or determining whether an if statement nesting layer number is larger than a set layer number threshold in a target segment program corresponding to the path with the time sequence violation in the image processing program, if so, receiving a modified image processing program, wherein if statement in the target segment program corresponding to the path with the time sequence violation in the modified image processing program is replaced by a case statement.
In one embodiment of the invention, the reasons include that the signal fanout coefficient is greater than a set fanout threshold;
the timing constraint unit 302 specifically includes: copying the generation logic of the driving signals in the paths with the time sequence violations so that at least two paths of driving signals with the same frequency and the same phase obtained by copying drive circuits in the paths with the time sequence violations; and/or determining relevant logic in the path with the timing violation, and performing region constraint on the relevant logic to place the relevant logic in the same region.
In one embodiment of the present invention, the timing analysis unit 301 is further configured to compile the image processing program after the timing constraint is performed on the path with the timing violation, determine whether the timing violation in the compiled image processing program is eliminated, if not, delete the netlist file generated in the compiling process, and trigger the timing constraint unit 302 to perform a corresponding operation until it is determined that the timing violation in the compiled image processing program is eliminated.
In one embodiment of the present invention, the layout wiring constraint unit 303, when executing the delay of the target image processing path according to the resource margin is not greater than a set delay threshold, specifically includes: when the resource allowance is not smaller than the set resource threshold, carrying out layout wiring constraint on the target image processing path, so that after the layout wiring constraint, the delay of the target image processing path is not larger than the set delay threshold; the delay threshold is 0.5 clock cycles.
It should be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation of an image noise suppression apparatus. In other embodiments of the invention, an image noise suppression device may include more or fewer components than shown, or may combine certain components, or may split certain components, or may have a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
The content of information interaction and execution process between the modules in the device is based on the same conception as the embodiment of the method of the present invention, and specific content can be referred to the description in the embodiment of the method of the present invention, which is not repeated here.
The embodiment of the invention also provides a computing device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the image noise suppression method in any embodiment of the invention when executing the computer program.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium is stored with a computer program, and the computer program when being executed by a processor, causes the processor to execute the image noise suppression method in any embodiment of the invention.
Specifically, a system or apparatus provided with a storage medium on which a software program code realizing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be caused to read out and execute the program code stored in the storage medium.
In this case, the program code itself read from the storage medium may realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code form part of the present invention.
Examples of the storage medium for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer by a communication network.
Further, it should be apparent that the functions of any of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform part or all of the actual operations based on the instructions of the program code.
Further, it is understood that the program code read out by the storage medium is written into a memory provided in an expansion board inserted into a computer or into a memory provided in an expansion module connected to the computer, and then a CPU or the like mounted on the expansion board or the expansion module is caused to perform part and all of actual operations based on instructions of the program code, thereby realizing the functions of any of the above embodiments.
It is noted that relational terms such as first and second, and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of additional identical elements in a process, method, article or apparatus that comprises the element.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: various media in which program code may be stored, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. An image noise suppression method, characterized by comprising:
s1: determining whether a timing violation exists in an image processing program executed by the FPGA; if the timing violation exists, S2 is executed; if no timing violation exists, executing S3-S5;
s2: determining paths with timing violations, and performing timing constraint on the paths with the timing violations;
s3: determining a plurality of image processing paths associated with image processing;
s4: determining a target image processing path with longest delay from the plurality of image processing paths;
s5: determining a resource allowance of a register corresponding to the target image processing path, and when the resource allowance is not smaller than a set resource threshold, carrying out layout wiring constraint on the target image processing path so that after the layout wiring constraint, the delay of the target image processing path is not larger than a set delay threshold; the delay threshold is 0.5 clock cycles.
2. The method of claim 1, wherein after the determining the path for which the timing violation exists, before the timing constraint is applied to the path for which the timing violation exists, further comprising:
determining a cause of the timing violation for the path where the timing violation exists; the reasons include not adding at least one of a period constraint to the pixel clock of the input image, a logic level greater than a set level threshold, and a signal fan-out coefficient greater than a set fan-out threshold.
3. The method of claim 2, wherein the reason includes not adding a period constraint to a pixel clock of the input image;
the timing constraint on the paths with timing violations comprises: and determining a clock signal corresponding to the path with the timing violation, and adding the period constraint added to the clock signal into a constraint file.
4. The method of claim 2, wherein the cause comprises a logic level greater than a set level threshold;
the timing constraint on the paths with timing violations comprises:
determining whether a target segment program corresponding to the path with the time sequence violation in the image processing program is encoded by adopting a pipeline technology, if not, receiving a modified image processing program, wherein the target segment program in the modified image processing program is encoded by adopting the pipeline technology;
and/or the number of the groups of groups,
determining whether an if statement nesting layer number is larger than a set layer number threshold value in a target section program corresponding to the path with the time sequence violation in the image processing program, if so, receiving a modified image processing program, wherein the if statement in the target section program corresponding to the path with the time sequence violation in the modified image processing program is replaced by a case statement.
5. The method of claim 2, wherein the cause comprises a signal fanout coefficient greater than a set fanout threshold;
the timing constraint on the paths with timing violations comprises:
copying the generation logic of the driving signals in the paths with the time sequence violations so that at least two paths of driving signals with the same frequency and the same phase obtained by copying drive circuits in the paths with the time sequence violations;
and/or the number of the groups of groups,
determining relevant logic in the path where the timing violation exists, and performing region constraint on the relevant logic to place the relevant logic in the same region.
6. The method of any of claims 1-5, further comprising, after said subjecting the paths for which timing violations exist to timing constraints:
compiling the image processing program subjected to time sequence constraint, determining whether time sequence violations in the compiled image processing program are eliminated, if not, deleting a netlist file generated in the compiling process, and executing S2 until the time sequence violations in the compiled image processing program are eliminated.
7. An image noise suppression apparatus, comprising:
a timing analysis unit for determining whether a timing violation exists in an image processing program executed by the FPGA; if the time sequence violations exist, triggering the time sequence constraint unit to execute corresponding operations; if no timing violation exists, triggering the layout wiring constraint unit to execute corresponding operation;
the time sequence constraint unit is used for determining paths with time sequence violations and performing time sequence constraint on the paths with the time sequence violations;
the layout wiring constraint unit is used for determining a plurality of image processing paths related to image processing; determining a target image processing path with longest delay from the plurality of image processing paths; determining a resource allowance of a register corresponding to the target image processing path, and when the resource allowance is not smaller than a set resource threshold, carrying out layout wiring constraint on the target image processing path so that after the layout wiring constraint, the delay of the target image processing path is not larger than a set delay threshold; the delay threshold is 0.5 clock cycles.
8. The apparatus of claim 7, wherein the timing constraint unit is further configured to determine, after the determining the path with the timing violation, a cause of the timing violation for the path with the timing violation before the timing constraint is applied to the path with the timing violation; the reasons include not adding at least one of a period constraint to the pixel clock of the input image, a logic level greater than a set level threshold, and a signal fan-out coefficient greater than a set fan-out threshold.
9. The apparatus of claim 8, wherein the reason comprises not adding a period constraint to a pixel clock of the input image;
the time sequence constraint unit specifically comprises the following steps when time sequence constraint is carried out on a path with time sequence violations: and determining a clock signal corresponding to the path with the timing violation, and adding the period constraint added to the clock signal into a constraint file.
10. The apparatus of claim 8, wherein the cause comprises a logic level greater than a set level threshold;
the time sequence constraint unit specifically comprises the following steps when time sequence constraint is carried out on a path with time sequence violations:
determining whether a target segment program corresponding to the path with the time sequence violation in the image processing program is encoded by adopting a pipeline technology, if not, receiving a modified image processing program, wherein the target segment program in the modified image processing program is encoded by adopting the pipeline technology;
and/or the number of the groups of groups,
determining whether an if statement nesting layer number is larger than a set layer number threshold value in a target section program corresponding to the path with the time sequence violation in the image processing program, if so, receiving a modified image processing program, wherein the if statement in the target section program corresponding to the path with the time sequence violation in the modified image processing program is replaced by a case statement.
11. The apparatus of claim 8, wherein the cause comprises a signal fanout coefficient greater than a set fanout threshold;
the time sequence constraint unit specifically comprises the following steps when time sequence constraint is carried out on a path with time sequence violations:
copying the generation logic of the driving signals in the paths with the time sequence violations so that at least two paths of driving signals with the same frequency and the same phase obtained by copying drive circuits in the paths with the time sequence violations;
and/or the number of the groups of groups,
determining relevant logic in the path where the timing violation exists, and performing region constraint on the relevant logic to place the relevant logic in the same region.
12. The apparatus according to any one of claims 7-11, wherein the timing analysis unit is further configured to compile the image processing program after the timing constraint is performed on the path with the timing violation, determine whether the timing violation in the compiled image processing program is eliminated, if not, delete the netlist file generated in the compiling process, and continue to execute the path with the timing violation until it is determined that the timing violation in the compiled image processing program is eliminated.
13. A computing device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the method of any of claims 1-6 when the computer program is executed.
14. A computer readable storage medium having stored thereon a computer program which, when executed in a computer, causes the computer to perform the method of any of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111096686.5A CN113781354B (en) | 2021-09-18 | 2021-09-18 | Image noise suppression method, device, computing equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111096686.5A CN113781354B (en) | 2021-09-18 | 2021-09-18 | Image noise suppression method, device, computing equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113781354A CN113781354A (en) | 2021-12-10 |
| CN113781354B true CN113781354B (en) | 2023-09-22 |
Family
ID=78851993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111096686.5A Active CN113781354B (en) | 2021-09-18 | 2021-09-18 | Image noise suppression method, device, computing equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113781354B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114861578B (en) * | 2022-07-05 | 2022-10-11 | 飞腾信息技术有限公司 | Method, device, equipment and storage medium for repairing hold time violation |
| CN115796093B (en) * | 2023-01-03 | 2023-08-08 | 摩尔线程智能科技(北京)有限责任公司 | Circuit time sequence optimization method and device, electronic equipment and storage medium |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294783A (en) * | 1997-12-26 | 2001-05-09 | 株式会社日立制作所 | Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit |
| JP2011164740A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Apparatus and method for circuit design |
| CN105930609A (en) * | 2016-05-04 | 2016-09-07 | 华中科技大学 | FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation |
| WO2016206225A1 (en) * | 2015-06-24 | 2016-12-29 | 深圳市中兴微电子技术有限公司 | Strong filtering cancellation method and apparatus, and computer storage medium |
| CN106547929A (en) * | 2015-09-16 | 2017-03-29 | 马云利 | A kind of FPGA clock networks design |
| WO2018076735A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Method and device for repairing hold time violation, and computer storage medium |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN109583103A (en) * | 2018-12-04 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of time sequence repairing method based on time margin |
| CN109859713A (en) * | 2019-03-22 | 2019-06-07 | 惠科股份有限公司 | A kind of driving method of display panel, driving circuit and display device |
| CN110377922A (en) * | 2018-04-12 | 2019-10-25 | 龙芯中科技术有限公司 | Retention time fault restorative procedure, device and equipment |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN111950214A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Time sequence analysis method, device and equipment and computer storage medium |
| CN112100959A (en) * | 2020-09-21 | 2020-12-18 | Oppo广东移动通信有限公司 | EDA (electronic design automation) tool-based time sequence analysis method and device and storage medium |
| CN112115664A (en) * | 2020-11-18 | 2020-12-22 | 北京滕华软件有限公司 | Multi-mode multi-clock domain chip integrated control system |
| CN112232016A (en) * | 2020-11-19 | 2021-01-15 | 深圳安捷丽新技术有限公司 | Efficient bus design iteration method, system and platform for SSD (solid State disk) master control chip |
-
2021
- 2021-09-18 CN CN202111096686.5A patent/CN113781354B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1294783A (en) * | 1997-12-26 | 2001-05-09 | 株式会社日立制作所 | Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit |
| JP2011164740A (en) * | 2010-02-05 | 2011-08-25 | Renesas Electronics Corp | Apparatus and method for circuit design |
| WO2016206225A1 (en) * | 2015-06-24 | 2016-12-29 | 深圳市中兴微电子技术有限公司 | Strong filtering cancellation method and apparatus, and computer storage medium |
| CN106547929A (en) * | 2015-09-16 | 2017-03-29 | 马云利 | A kind of FPGA clock networks design |
| CN105930609A (en) * | 2016-05-04 | 2016-09-07 | 华中科技大学 | FPGA (Field Programmable Gate Array) time sequence optimization method used for coherent demodulation |
| WO2018076735A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Method and device for repairing hold time violation, and computer storage medium |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN110377922A (en) * | 2018-04-12 | 2019-10-25 | 龙芯中科技术有限公司 | Retention time fault restorative procedure, device and equipment |
| CN109583103A (en) * | 2018-12-04 | 2019-04-05 | 珠海市微半导体有限公司 | A kind of time sequence repairing method based on time margin |
| CN109859713A (en) * | 2019-03-22 | 2019-06-07 | 惠科股份有限公司 | A kind of driving method of display panel, driving circuit and display device |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN111950214A (en) * | 2020-08-14 | 2020-11-17 | Oppo广东移动通信有限公司 | Time sequence analysis method, device and equipment and computer storage medium |
| CN112100959A (en) * | 2020-09-21 | 2020-12-18 | Oppo广东移动通信有限公司 | EDA (electronic design automation) tool-based time sequence analysis method and device and storage medium |
| CN112115664A (en) * | 2020-11-18 | 2020-12-22 | 北京滕华软件有限公司 | Multi-mode multi-clock domain chip integrated control system |
| CN112232016A (en) * | 2020-11-19 | 2021-01-15 | 深圳安捷丽新技术有限公司 | Efficient bus design iteration method, system and platform for SSD (solid State disk) master control chip |
Non-Patent Citations (5)
| Title |
|---|
| Dynamic Checking and Solution to Temporal Violations in Concurrent Workflow Processes;YanHua Du等;《IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART A: SYSTEMS AND HUMANS》;第41卷(第6期);第1166-1181页 * |
| MCMM 技术在SOC FD_Z801 模块中的运用;蔡沅坤等;《电气开关》(第4期);第10-13、18页 * |
| 双频双模导航基带芯片的静态时序分析;常江等;《微电子学》;41(03);第350-353、358页 * |
| 基于7nm工艺GPU核心计算单元的后端设计;李瑞;《中国优秀硕士学位论文全文数据库 信息科技辑》;I137-39 * |
| 基于FPGA平台的嵌入式视觉处理器原型验证;梅亮;《中国优秀硕士学位论文全文数据库 信息科技辑》(第（2021）05期);I138-1046 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113781354A (en) | 2021-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7086023B2 (en) | System and method for probabilistic criticality prediction of digital circuits | |
| US6952812B2 (en) | Design analysis tool for path extraction and false path identification and method thereof | |
| CN113781354B (en) | Image noise suppression method, device, computing equipment and storage medium | |
| US8161439B2 (en) | Method and apparatus for processing assertions in assertion-based verification of a logic design | |
| US11726545B2 (en) | Methods and apparatus for selectively extracting and loading register states | |
| US8146034B2 (en) | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. | |
| US8407654B2 (en) | Glitch power reduction | |
| US9633148B2 (en) | Static timing analysis in circuit design | |
| US7765503B2 (en) | Half cycle common path pessimism removal method | |
| US9483597B1 (en) | Opportunistic candidate path selection during physical optimization of a circuit design for an IC | |
| US8627263B2 (en) | Gate configuration determination and selection from standard cell library | |
| US6643829B1 (en) | Reducing clock skew in clock gating circuits | |
| US20110296361A1 (en) | Circuit analysis method | |
| US8612911B2 (en) | Estimating power consumption of an electronic circuit | |
| US6681377B2 (en) | Timing resynthesis in a multi-clock emulation system | |
| US7237208B1 (en) | Managing formal verification complexity of designs with datapaths | |
| US8776003B2 (en) | System and method for employing side transition times from signoff-quality timing analysis information to reduce leakage power in an electronic circuit and an electronic design automation tool incorporating the same | |
| US6378113B1 (en) | Black box transparency in a circuit timing model | |
| US7082582B1 (en) | Reducing clock skew in clock gating circuits | |
| US7028273B2 (en) | Delay optimization designing system and delay optimization designing method for a logic circuit and control program | |
| US10817633B2 (en) | Timing model, timing model building method, and related top-level analysis method | |
| CN113935264A (en) | Low power consumption synthesis method and device thereof | |
| US11256838B2 (en) | Establishing method for timing model | |
| US9852259B2 (en) | Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks | |
| US7418684B1 (en) | Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |