CN105870186A - P-type dynamic threshold transistor, fabrication method and method for improving working voltage - Google Patents
P-type dynamic threshold transistor, fabrication method and method for improving working voltage Download PDFInfo
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- CN105870186A CN105870186A CN201610237267.1A CN201610237267A CN105870186A CN 105870186 A CN105870186 A CN 105870186A CN 201610237267 A CN201610237267 A CN 201610237267A CN 105870186 A CN105870186 A CN 105870186A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 238000002360 preparation method Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 210000000746 body region Anatomy 0.000 abstract 3
- 238000002955 isolation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a P-type dynamic threshold transistor, a fabrication method and a method for improving a working voltage. The P-type dynamic threshold transistor at least comprises a substrate structure, a P-channel metal oxide semiconductor (PMOS) device and a positive negative (PN) junction device, wherein an N region of the PN junction device is connected with a body region of the PMOS device, and a P region of the PN junction device is connected with a gate of the PMOS device. The fabrication method comprises the following steps of carrying out P-type heavy doping to respectively form a source region, a drain region and the body region of the PMOS device in an N-type intrinsic region, and simultaneously forming the PN junction device; sequentially forming a gate oxide layer and a poly-silicon layer above a channel region, and carrying out P-type heavy doping on the poly-silicon layer to form the gate; and connecting the gate of the PMOS device with the P region of the PN junction device by through holes and metal. By forming a reverse biased PN junction on a gate body connection path, the body region voltage is increased, the threshold voltage is reduced, the driving current is increased, the working voltage is increased, and the application value of the P-type dynamic threshold transistor in the field of designing a low-power-consumption circuit is increased.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly relate to a kind of p-type dynamic threshold transistor, preparation method and carry
The method of high working voltage.
Background technology
At whole semicon industry during the development of new generation of semiconductor device, chip manufacturer is faced with stern challenge.
Concretely, produce high performance chips manufacturer's facing challenges to speed faster, temperature lower chip design need
Ask.For the chip manufacturer of Mobile solution it is desirable that the less semiconductor devices of power consumption.In order to tackle these challenges, mostly
The leading device manufacturer of number all have selected silicon-on-insulator (SOI, the Silicon On with low-power consumption advantage at high speed
Insulator) technology.
The body district of silicon-on-insulator can with floating, or draw receive on a fixed potential position.When body district voltage raises, device
Part threshold voltage reduces, and can effectively increase large-drive-current.1994, first dynamic threshold transistor was carried by IBM Corporation
Go out, just cause the broad interest of researcher.SOI dynamic threshold transistor (DTMOS, Dynamic Threshold Metal
Oxide Semiconductor) Shi Jiangti district and grid connect, it is achieved the dynamic adjustment of threshold voltage.The type device threshold moves
State is variable, and when device is opened, body district voltage raises, and causes threshold value to reduce, and current driving ability improves, when device is in pass
During disconnected state, there is higher threshold voltage, thus reduce leakage current.But the PN junction that body district is formed with source, drain region, if
When grid voltage is higher than this PN junction conducting voltage, causes electric current to increase suddenly, cause the increase of power consumption.Due to these parasitic two poles
The existence of pipe, causes dynamic threshold transistor operating voltage relatively low, typically at below 0.7V, and therefore can not be with traditional crystal
Pipe shares supply voltage, also limit the application of dynamic threshold transistor.
Radio-frequency technique is to power consumption and performance rdativery sensitive, although SOI DTMOS transistor can provide relatively low power consumption and higher
Performance, but its operating voltage is relatively low, for operating voltage higher time can not directly use.
Therefore, the operating voltage how improving SOI dynamic threshold transistor has become those skilled in the art's problem demanding prompt solution
One of.
Summary of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of p-type dynamic threshold transistor, preparation
Method and the method improving operating voltage are low for solving the operating voltage of SOI dynamic threshold transistor in prior art, it is impossible to
Share supply voltage with traditional transistor, limit the problems such as application.
For achieving the above object and other relevant purposes, the present invention provides a kind of p-type dynamic threshold transistor, and described p-type is dynamic
Threshold transistor at least includes:
Substrat structure, is positioned at the PMOS device on described substrat structure and PN junction device；
The channel region of described PMOS device be N-type intrinsic region, body district be p-type heavily doped region；Described PN junction device is with described
The channel region of PMOS device is as N district, using the body district of described PMOS device as P district；The N district of described PN junction device
With the connection in the body district of described PMOS device, the P district of described PN junction device is connected with the grid of described PMOS device.
Preferably, described substrat structure at least includes semiconductor base and is positioned at the oxide layer on described semiconductor base.
Preferably, described PMOS device is n PMOS in parallel, and n is the natural number more than or equal to 1.
It is highly preferred that n the PN junction diode that the PMOS that described PN junction device is in parallel with n connects one to one.
It is highly preferred that described PN junction device is 1 PN junction diode.
Preferably, described PMOS device also includes the gate oxide between described channel region and grid, and is positioned at channel region
The source region of both sides and drain region；Wherein, described grid are p-type heavily doped region, and described source region and described drain region are p-type heavily doped region.
Preferably, described PMOS device and described PN junction device are connected by through hole and metal.
For achieving the above object and other relevant purposes, the present invention also provides for the preparation method of a kind of p-type dynamic threshold transistor,
The preparation method of described p-type dynamic threshold transistor at least includes:
One substrat structure is provided, described substrat structure is prepared N-type intrinsic region；
P-type heavy doping is carried out to form the source of PMOS device, drain region and body district respectively in described N-type intrinsic region, described
Being channel region between the source of PMOS device, drain region, the channel region of described PMOS device and body district are respectively as N district and P district
Forming PN junction device, the N district of described PN junction device is connected with the body district of described PMOS device；
Above the channel region of described PMOS device, form gate oxide, described gate oxide forms polysilicon layer, to institute
State polysilicon layer and carry out p-type heavy doping to form the grid of described PMOS device；
The P district of the grid of described PMOS device with described PN junction device is connected with metal by through hole.
For achieving the above object and other relevant purposes, the present invention also provides for a kind of improving p-type dynamic threshold transistor operating voltage
Method, the method for described raising p-type dynamic threshold transistor operating voltage at least includes:
Connecting PN junction device between the Shan Heti district of PMOS device, the anode of described PN junction device connects described PMOS
The grid of device, the negative electrode of described PN junction device connects the body district of described PMOS device；Wherein, the body of described PMOS device
District is p-type heavily doped region, and simultaneously as the P district of described PN junction device, the channel region of described PMOS device is N-type intrinsic
District, simultaneously as the N district of described PN junction device；So that the body district voltage of described PMOS device raises, and then reduce threshold value
Voltage, raising drive electric current, it is achieved the raising of operating voltage.
As it has been described above, the p-type dynamic threshold transistor of the present invention, preparation method and the method for raising operating voltage, have following
Beneficial effect:
The method of the p-type dynamic threshold transistor of the present invention, preparation method and raising operating voltage is by grid body connecting path
Form a reverse biased pn junction, carry out lifting body district voltage, reduce threshold voltage, raising driving electric current, it is achieved carrying of operating voltage
Height, extends the p-type dynamic threshold transistor using value at low consumption circuit design field.
Accompanying drawing explanation
Fig. 1 is shown as the schematic top plan view of the p-type dynamic threshold transistor domain of the embodiment of the present invention one and embodiment three.
Fig. 2 is shown as the AA ' of the p-type dynamic threshold transistor domain of the embodiment of the present invention one to cross-sectional schematic.
Fig. 3 is shown as many finger-cross structure domain of the p-type dynamic threshold transistor of the embodiment of the present invention two.
Fig. 4 is shown as the principle schematic of the method for the raising p-type dynamic threshold transistor operating voltage of the embodiment of the present invention four.
Element numbers explanation
1 p-type dynamic threshold transistor
11 substrat structures
111 semiconductor bases
112 oxide layers
12 PMOS device
121 channel regions
122 gate oxides
123 grid
124 source regions
125 drain regions
126 body districts
13 PN junction devices
131 N districts
132 P districts
14 through holes
15 metals
16 shallow trench isolation
S1～S4 step
Detailed description of the invention
Below by way of specific instantiation, embodiments of the present invention being described, those skilled in the art can be by disclosed by this specification
Content understand other advantages and effect of the present invention easily.The present invention can also be added by the most different detailed description of the invention
To implement or application, the every details in this specification can also be based on different viewpoints and application, in the essence without departing from the present invention
Various modification or change is carried out under god.
Refer to Fig. 1～Fig. 4.It should be noted that the diagram provided in the present embodiment illustrates the present invention's the most in a schematic way
Basic conception, the most graphic in component count time only display with relevant assembly in the present invention rather than is implemented according to reality, shape and
Size is drawn, and during its actual enforcement, the kenel of each assembly, quantity and ratio can be a kind of random change, and its assembly layout type
State is likely to increasingly complex.
Embodiment one
As shown in Fig. 1～Fig. 2, the present invention provides a kind of p-type dynamic threshold transistor 1, described p-type dynamic threshold transistor 1
At least include:
Substrat structure 11, is positioned at the PMOS device 12 on described substrat structure 11 and PN junction device 13.
As in figure 2 it is shown, described substrat structure 11 is positioned at bottom, as the substrate preparing semiconductor devices.
Specifically, as in figure 2 it is shown, in the present embodiment, described substrat structure 11 at least includes semiconductor base 111 and is positioned at
Oxide layer 112 on described semiconductor base 111.Described semiconductor base 111 includes but not limited to the material such as silicon, silica
Material.Described substrat structure 11 can also include that other improve the semiconductor layer of device performance, is not limited with the present embodiment.
As shown in Fig. 1～Fig. 2, described PMOS device 12 is positioned on described substrat structure 11, including channel region 121, grid oxygen
Change floor 122, grid 123, source region 124, drain region 125 and body district 126.
Specifically, as in figure 2 it is shown, described channel region 121 is positioned on described substrat structure 11, described channel region 121 is N
Type intrinsic region.Described gate oxide 122 is positioned on described channel region 121, and in the present embodiment, described gate oxide 122 is adopted
With the material of high-k.Described grid 123 are positioned at above described gate oxide 122, and described grid 123 are that p-type is heavily doped
Polysilicon, wherein right part does not carries out p-type heavy doping to play the effect of isolation.As it is shown in figure 1, described source region 124 He
Described drain region 125 lays respectively at the both sides of described channel region 121, is the second p-type heavily doped region.Described body district 126 is with described
Channel region 121 connects, and described body district 126 is the first p-type heavily doped region.
As shown in Fig. 1～Fig. 2, described PN junction device 13 is positioned on described substrat structure 11, including district 132 of N district 131 and P.
Specifically, as in figure 2 it is shown, described N district 131 is shared with the channel region 121 of described PMOS device, described P district
132 is shared with the body district 121 of described PMOS device, and described P district 132 is connected with described N district 131, forms PN junction.
As shown in Fig. 1～Fig. 2, the N district 131 of described PN junction device 13 and the company in the body district 126 of described PMOS device 12
Connecing, the P district 132 of described PN junction device 13 is connected by through hole 14 and metal 15 with the grid 123 of described PMOS device 12
Connect.
It should be noted that for the p-type dynamic threshold transistor of the present embodiment, it is more suitable for being designed as one and has T-shaped
The SOI p-type dynamic threshold transistor of grid, is used for improving and improving operating voltage, when this is owing to drawing in SOI technology body district,
There is multiple lead-out mode, and T-shaped grid are the modes being most widely used, grid T-shaped for SOI, relative to common crystal
Pipe, its area consumption is less, can improve the integrated level of chip in the case of effective body district draws.
Embodiment two
As it is shown on figure 3, in the present embodiment, it is provided that the p-type dynamic threshold transistor of a kind of many finger-cross structure, meet radio frequency
The gain of transistor and power requirement.
Specifically, the p-type dynamic threshold transistor of described many finger-cross structure includes the PMOS that n PMOS in parallel is formed
Device, and PN junction device, n is the natural number more than or equal to 1.In the present embodiment, n value is 4, in actual design
In, determine the occurrence of n with the requirement of gain and power, be not limited with the present embodiment.Described PN junction device can be 1
The PN junction diode that the individual Shan Heti district with n PMOS is connected respectively, it is also possible to be the PMOS in parallel with n one by one
Corresponding n the PN junction diode connected.Described PMOS device and the structure of described PN junction diode and annexation and reality
Execute example one consistent, repeat the most one by one at this.
Embodiment three
As in figure 2 it is shown, the present invention also provides for the preparation method of a kind of p-type dynamic threshold transistor, described p-type dynamic threshold is brilliant
The preparation method of body pipe at least includes:
Step S1: provide a substrat structure 11, prepares N-type intrinsic region on described substrat structure 11.
Specifically, as in figure 2 it is shown, in the present embodiment, described substrat structure 11 includes semiconductor base 111 and is positioned at described
Oxide layer 112 on semiconductor base 111.Described substrat structure 11 can also include that other improve the semiconductor layer of device performance,
It is not limited with the present embodiment.
Step S2: carry out in described N-type intrinsic region p-type heavy doping with formed respectively PMOS device 12 source region 124,
Drain region 125 and body district 126, be channel region 121 between the source region 124 of described PMOS device, drain region 125, described PMOS
Channel region 121 and the body district 126 of device 12 form PN junction device 13, described PN respectively as district 132 of N district 131 and P
The N district 131 of junction device 13 is connected with the body district 126 of described PMOS device 12.
Specifically, as in figure 2 it is shown, in the present embodiment, described N-type intrinsic region carries out p-type heavy doping for the first time and is formed
The body district 126 of described PMOS device 12, forms PN junction device 13, wherein N simultaneously as P district 132 and N-type intrinsic region
Type intrinsic region is as the N district 131 of PN junction device 13.In described N-type intrinsic region, carry out second time p-type heavy doping formed
The source region 124 of PMOS device 12 and drain region 125 (not showing in Fig. 2).
Step S3: form gate oxide 122 above the channel region 121 of described PMOS device 12, at described gate oxide
Form polysilicon layer on 122, described polysilicon layer is carried out p-type heavy doping to form the grid 123 of described PMOS device 12.
Specifically, at the channel region 121 disposed thereon high dielectric constant material of described PMOS device 12 to form gate oxide
122.Deposit polycrystalline silicon layer on described gate oxide 122, carries out p-type heavy doping to form described PMOS to described polysilicon layer
The grid 123 of device 12, wherein, the polysilicon layer closing on part with described body district 126 does not carries out p-type heavy doping, with by first
The doping of secondary p-type and second time p-type doping isolation.
Step S4: by through hole 14 and metal 15 by the grid 123 of described PMOS device 12 and described PN junction device 13
P district 132 is connected.
The body district 126 of described PMOS device 12 by STI (Shallow Trench Isolation, shallow trench isolation) and other
Device isolation.
Embodiment four
As shown in Figure 4, the present invention also provides for a kind of method improving p-type dynamic threshold transistor operating voltage, described raising P
The method of type dynamic threshold transistor operating voltage at least includes:
Connecting PN junction device 13 between the Shan Heti district of PMOS device 12, the negative electrode of described PN junction device 13 connects institute
Stating the grid of PMOS device 12, the anode of described PN junction device 13 connects the body district of described PMOS device 12；Wherein,
The body district of described PMOS device 12 is p-type heavily doped region, simultaneously as the N district of described PN junction device 13, described PMOS
The channel region of device 12 is N-type intrinsic region, simultaneously as the P district of described PN junction device 13；So that described PMOS device
The body district voltage of 12 raises, and then reduces threshold voltage, improves driving electric current, it is achieved the raising of operating voltage.
Specifically, as shown in Figure 4, the reverse-biased grid in described PMOS device 12 of described PN junction device 13, body connecting path
On, when grid voltage is negative voltage, and when reaching the threshold voltage of PMOS device 12, PMOS device 12 is opened, grid
The change of voltage will affect the voltage of channel region；Owing to PN junction can bear bigger voltage, flow through the electricity of this PN junction device 13
Flowing the least, PN junction device 13 is not turned on, and is equivalent to access a capacitor element between the grid, body of PMOS device 12,
When grid voltage increases (i.e. negative voltage absolute value increases), channel region voltage increases the most therewith, and body district is connected with channel region,
Therefore body district voltage can necessarily be promoted；During simultaneously as grid voltage and body district voltage all increase, PMOS device
The threshold voltage of 12 reduces, and it drives electric current to have also been obtained raising, so that the p-type dynamic threshold transistor work electricity of the present invention
Pressure improves, and reaches about 0.7V, it is possible to share supply voltage with traditional transistor, extends p-type dynamic threshold transistor
Application.In order to meet gain and the power requirement of RF transistors, described PMOS device 12 can include n also
The PMOS of connection, n is the natural number more than or equal to 1, in actual design, determines n's with the requirement of gain and power
Occurrence.
In sum, the present invention provides a kind of p-type dynamic threshold transistor, preparation method and the method improving operating voltage, logical
Cross one reverse biased pn junction of formation on grid body connecting path, carry out lifting body district voltage, reduce threshold voltage, raising driving electric current,
Realize the raising of operating voltage, extend the p-type dynamic threshold transistor using value at low consumption circuit design field.So,
The present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The principle of above-described embodiment only illustrative present invention and effect thereof, not for limiting the present invention.Any it is familiar with this skill
Above-described embodiment all can be modified under the spirit and the scope of the present invention or change by the personage of art.Therefore, such as
All that in art, tool usually intellectual is completed under without departing from disclosed spirit and technological thought etc.
Effect is modified or changes, and must be contained by the claim of the present invention.
Claims (9)
1. a p-type dynamic threshold transistor, it is characterised in that described p-type dynamic threshold transistor at least includes:
Substrat structure, is positioned at the PMOS device on described substrat structure and PN junction device；
The channel region of described PMOS device be N-type intrinsic region, body district be p-type heavily doped region；Described PN junction device with
The channel region of described PMOS device is as N district, using the body district of described PMOS device as P district；Described PN junction device
The N district of part is connected with the body district of described PMOS device, the P district of described PN junction device and the grid of described PMOS device
Connect.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that: described substrat structure at least includes semiconductor
Substrate and be positioned at the oxide layer on described semiconductor base.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that: described PMOS device is n parallel connection
PMOS, n is the natural number more than or equal to 1.
P-type dynamic threshold transistor the most according to claim 3, it is characterised in that: described PN junction device is in parallel with n
N PN junction diode connecting one to one of PMOS.
5. according to the p-type dynamic threshold transistor described in claim 1 or 3, it is characterised in that: described PN junction device is 1 PN
Junction diode.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that: described PMOS device also includes being positioned at
Gate oxide between described channel region and grid, and it is positioned at source region and the drain region of channel region both sides；Wherein, described grid are P
Type heavily doped region, described source region and described drain region are p-type heavily doped region.
P-type dynamic threshold transistor the most according to claim 1, it is characterised in that: described PMOS device and described PN junction
Device is connected by through hole and metal.
8. the preparation method of a p-type dynamic threshold transistor, it is characterised in that: the preparation method of described p-type dynamic threshold transistor
At least include:
One substrat structure is provided, described substrat structure is prepared N-type intrinsic region；
N-type heavy doping is carried out to form the source of PMOS device, drain region and body district, institute respectively in described N-type intrinsic region
Stating between the source of PMOS device, drain region is channel region, and the channel region of described PMOS device and body district are respectively as N district
Forming PN junction device with P district, the N district of described PN junction device is connected with the body district of described PMOS device；
Above the channel region of described PMOS device, form gate oxide, described gate oxide formed polysilicon layer,
Described polysilicon layer is carried out p-type heavy doping to form the grid of described PMOS device；
The P district of the grid of described PMOS device with described PN junction device is connected with metal by through hole.
9. the method improving p-type dynamic threshold transistor operating voltage, it is characterised in that described raising p-type dynamic threshold crystal
The method of pipe operating voltage at least includes:
Connecting PN junction device between the Shan Heti district of PMOS device, the anode of described PN junction device connects described PMOS
The grid of device, the negative electrode of described PN junction device connects the body district of described PMOS device；Wherein, described PMOS device
Body district be p-type heavily doped region, simultaneously as the P district of described PN junction device, the channel region of described PMOS device is N
Type intrinsic region, simultaneously as the N district of described PN junction device；So that the body district voltage of described PMOS device raises, enter
And reduce threshold voltage, improve driving electric current, it is achieved the raising of operating voltage.
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| CN101090122A (en) * | 2006-06-16 | 2007-12-19 | 中国科学院微电子研究所 | Method for grid connecting with SOI dynamic threshold transistor through anti-off schottky |
| CN104362174A (en) * | 2014-11-21 | 2015-02-18 | 中国科学院上海微系统与信息技术研究所 | SOI dynamic threshold transistor |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
| CN105161500A (en) * | 2015-08-11 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | Insulator-on-silicon (SOI) radio-frequency device structure |
-
2016
- 2016-04-15 CN CN201610237267.1A patent/CN105870186B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101090122A (en) * | 2006-06-16 | 2007-12-19 | 中国科学院微电子研究所 | Method for grid connecting with SOI dynamic threshold transistor through anti-off schottky |
| CN104362174A (en) * | 2014-11-21 | 2015-02-18 | 中国科学院上海微系统与信息技术研究所 | SOI dynamic threshold transistor |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
| CN105161500A (en) * | 2015-08-11 | 2015-12-16 | 上海华虹宏力半导体制造有限公司 | Insulator-on-silicon (SOI) radio-frequency device structure |
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