CN105870015B - The preparation method and power device of power device - Google Patents
The preparation method and power device of power device Download PDFInfo
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- CN105870015B CN105870015B CN201510030728.3A CN201510030728A CN105870015B CN 105870015 B CN105870015 B CN 105870015B CN 201510030728 A CN201510030728 A CN 201510030728A CN 105870015 B CN105870015 B CN 105870015B
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Abstract
A kind of preparation method the present invention provides power device includes: to form channel；P-type heavily doped region is formed in channel；Form the first silicon nitride layer；First silicon nitride layer of channel and oxide layer is performed etching, to form the first silicon nitride spacer；P-type heavily doped region is performed etching；Carry out N-type injection；Form the second silicon nitride layer；Second silicon nitride layer of channel and oxide layer is performed etching, to form the second silicon nitride spacer；N-type heavily doped region is performed etching to substrate；Carry out thermal oxidation；Polysilicon layer is formed in the region of thermal oxide layer；Remove the first silicon nitride spacer and the second silicon nitride spacer；It is rectangular at oxide layer on the polysilicon layer；It forms metal layer and is made annealing treatment, to form metal contact layer；Form metal connection.The present invention also provides a kind of power devices, according to the technical solution of the present invention, effectively reduce channel resistance, ensure that the Performance And Reliability of device while reducing device size.
Description
Technical field
The present invention relates to technical field of semiconductors, preparation method and a kind of function in particular to a kind of power device
Rate device.
Background technique
In related semiconductor technology, vertical bilateral diffusion field-effect tranisistor (Vertical Double-Diffused
Metal Oxide Semiconductor, abbreviation VDMOS) it is a kind of power device that purposes is very extensive, the power device
It is vertically disposed for draining between source electrode, so that electric current is circulated in power device internal vertical, current density is increased, to change
It has been apt to rated current.The most important performance parameter of vertical bilateral diffusion field-effect tranisistor is exactly working loss, and working loss can
To be divided into conduction loss, cut-off loss and switching loss three parts.Wherein, conduction loss is determined by conducting resistance, cut-off loss
It is influenced by reverse leakage current size, parasitic capacitance charge and discharge bring is lost during switching loss refers to devices switch.In order to
Meet the requirement that power device adapts to frequency applications, reduces the switching loss of power device, improve the working efficiency of device, have
Important meaning.
Therefore, how design power device production method and structure with reduce power device channel resistance and conducting damage
Consumption becomes technical problem urgently to be resolved.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, proposes the preparation method and one kind of a kind of power device
Power device.
In view of this, the invention proposes a kind of preparation methods of power device, comprising: forming P-doped zone, oxidation
On the substrate of layer, processing is performed etching to form channel to the P-doped zone；P-type heavy doping ion is carried out in the channel
Injection, to form p-type heavily doped region；The first silicon nitride layer is formed on the substrate for forming the p-type heavily doped region；To institute
First silicon nitride for stating channel and the oxide layer performs etching, to form the first silicon nitride spacer；To the p-type
Heavily doped region performs etching, using the exposure P-doped zone as the N-doped zone of ion to be implanted；To it is described it is to be implanted from
The N-doped zone of son carries out N-type injection；The second silicon nitride layer is formed on the substrate for forming the N-type heavily doped region；It is right
Second silicon nitride layer of the channel and the oxide layer performs etching, to form the second silicon nitride spacer；To institute
N-type heavily doped region is stated to perform etching to the substrate；Thermal oxidation is carried out to the substrate through over etching；In the hot oxygen
Change and forms polysilicon layer in the region of layer；Remove first silicon nitride spacer and second silicon nitride spacer；Described more
Oxide layer is formed above crystal silicon layer；It forms metal layer and is made annealing treatment, contacted using forming metal silicide layer as metal
Layer；The metal contact layer is carried out to thicken processing, to form metal connection.
In the technical scheme, by the first silicon nitride spacer of preparation and the second silicon nitride spacer structure, photoetching is reduced
Technique limits the limitation to groove width, and the lithographic equipment minimum without line width can be realized the preparation of the groove of small size, have
Effect reduces the cost of manufacture of power device, and due to the reduction of groove dimensions, the quantity of unit area interior raceway groove increases, Ye Jizeng
The big width of groove ensure that the performance and reliably of device to reduce channel resistance while reducing device size
Property.
It is worth noting that compared to the preparation of vertical bilateral diffusion field-effect tranisistor constant power device in the related technology
Method, the present invention are formd the metal contact of the active area of power device using self-aligned technology, reduce two photoetching works
Skill effectively reduces technique and realizes the complexity of process, and improves the compatibility of power device and standard technology, provides
A possibility that batch production.
In the above-mentioned technical solutions, it is preferable that the element of the N-doped zone includes one of nitrogen, phosphorus and arsenic or more
Any combination of kind.
In the above-mentioned technical solutions, it is preferable that the element of the P-doped zone and the p-type heavily doped region include boron and/
Or aluminium.
In the above-mentioned technical solutions, it is preferable that the formation N-doped zone, the P-doped zone and the p-type weight
The substrate of doped region is made annealing treatment.
In the above-mentioned technical solutions, it is preferable that annealing is between 700 degrees Celsius to 1200 degrees Celsius, at annealing
The duration of reason is between 10 minutes to 40 minutes.
In the above-mentioned technical solutions, it is preferable that the thickness of first silicon nitride spacer be in 0.5 micron to 3 microns it
Between.
In the above-mentioned technical solutions, it is preferable that the thickness of second silicon nitride spacer be in 0.1 micron to 1 micron it
Between.
In the above-mentioned technical solutions, it is preferable that the p-type mixes formation above the oxide layer and the polysilicon in area
The thickness of oxide layer is between 1 micron to 10 microns.
According to the second aspect of the invention, it is also proposed that a kind of power device, the power device are used as any of the above-described
The preparation method of power device described in item technical solution is prepared.
Light is reduced by the first silicon nitride spacer of preparation and the second silicon nitride spacer structure by above technical scheme
Carving technology limits the limitation to groove width, and the preparation of the groove of small size can be realized in the lithographic equipment minimum without line width,
The cost of manufacture for effectively reducing power device, due to the reduction of groove dimensions, the quantity of unit area interior raceway groove increases, namely
Increase the width of groove, to reduce channel resistance, ensure that while reducing device size device performance and can
By property.
It is worth noting that compared to the preparation of vertical bilateral diffusion field-effect tranisistor constant power device in the related technology
Method, the present invention are formd the metal contact of the active area of power device using self-aligned technology, reduce two photoetching works
Skill effectively reduces technique and realizes the complexity of process, and improves the compatibility of power device and standard technology, provides
A possibility that batch production.
Detailed description of the invention
Fig. 1 shows the flow diagram of the preparation method of the power device of embodiment according to the present invention；
Fig. 2 to Figure 13 shows the diagrammatic cross-section of the preparation method of the power device of embodiment according to the present invention,
In, appended drawing reference and its corresponding structure are entitled: 1 substrate, 2 oxide layers, 3 polysilicon layers, 4P type heavily doped region, the doping of 5N type
Area, 6 thermal oxide layers, 7P type doped region, 8 metal contact layers, 9 silicon nitride layers (the first silicon nitride spacer, the second silicon nitride spacer).
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
To be implemented using other than the one described here other modes, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 1 shows the flow diagram of the preparation method of the power device of embodiment according to the present invention.
As shown in Figure 1, the preparation method of the power device of embodiment according to the present invention, comprising: step 102, forming P
Type doped region, oxide layer substrate on, to the P-doped zone perform etching processing to form channel；Step 104, described
Channel carries out the injection of p-type heavy doping ion, to form p-type heavily doped region；Step 106, in the institute for forming the p-type heavily doped region
It states and forms the first silicon nitride layer on substrate；Step 108, to first silicon nitride of the channel and the oxide layer into
Row etching, to form the first silicon nitride spacer；Step 110, the p-type heavily doped region is performed etching, is mixed with the exposure p-type
N-doped zone of the miscellaneous area as ion to be implanted；Step 112, N-type injection is carried out to the N-doped zone of the ion to be implanted；
Step 114, the second silicon nitride layer is formed on the substrate for forming the N-type heavily doped region；Step 116, to the channel
It is performed etching with second silicon nitride layer of the oxide layer, to form the second silicon nitride spacer；Step 118, to institute
N-type heavily doped region is stated to perform etching to the substrate；Step 120, thermal oxidation is carried out to the substrate through over etching；Step
Rapid 122, polysilicon layer is formed in the region of the thermal oxide layer；Step 124, first silicon nitride spacer and described is removed
Second silicon nitride spacer；Step 126, oxide layer is formed above the polysilicon layer；Step 128, it forms metal layer and carries out
Annealing, to form metal silicide layer as metal contact layer；Step 130, the metal contact layer is carried out thickening place
Reason, to form metal connection.
In the technical scheme, by the first silicon nitride spacer of preparation and the second silicon nitride spacer structure, photoetching is reduced
Technique limits the limitation to groove width, and the lithographic equipment minimum without line width can be realized the preparation of the groove of small size, have
Effect reduces the cost of manufacture of power device, and due to the reduction of groove dimensions, the quantity of unit area interior raceway groove increases, Ye Jizeng
The big width of groove ensure that the performance and reliably of device to reduce channel resistance while reducing device size
Property.
It is worth noting that compared to the preparation of vertical bilateral diffusion field-effect tranisistor constant power device in the related technology
Method, the present invention are formd the metal contact of the active area of power device using self-aligned technology, reduce two photoetching works
Skill effectively reduces technique and realizes the complexity of process, and improves the compatibility of power device and standard technology, provides
A possibility that batch production.
In the above-mentioned technical solutions, it is preferable that the element of the N-doped zone includes one of nitrogen, phosphorus and arsenic or more
Any combination of kind.
In the above-mentioned technical solutions, it is preferable that the element of the P-doped zone and the p-type heavily doped region include boron and/
Or aluminium.
In the above-mentioned technical solutions, it is preferable that the formation N-doped zone, the P-doped zone and the p-type weight
The substrate of doped region is made annealing treatment.
In the above-mentioned technical solutions, it is preferable that annealing is between 700 degrees Celsius to 1200 degrees Celsius, at annealing
The duration of reason is between 10 minutes to 40 minutes.
In the above-mentioned technical solutions, it is preferable that the thickness of first silicon nitride spacer be in 0.5 micron to 3 microns it
Between.
In the above-mentioned technical solutions, it is preferable that the thickness of second silicon nitride spacer be in 0.1 micron to 1 micron it
Between.
In the above-mentioned technical solutions, it is preferable that the p-type mixes formation above the oxide layer and the polysilicon in area
The thickness of oxide layer is between 1 micron to 10 microns.
According to the second aspect of the invention, it is also proposed that a kind of power device, comprising: such as any of the above-described technical solution institute
The preparation method for the power device stated is prepared.
Below with reference to Fig. 2 to Figure 13 pairs, the preparation method of the power device of embodiment according to the present invention is illustrated.
As shown in Fig. 2, carrying out P-type ion injection on 1 surface of substrate, P-doped zone 7 is formed, in the upper of P-doped zone 7
Rectangular to be patterned processing to oxide layer 2 at oxide layer 2, to form groove, the bottom-exposed of groove goes out P-doped zone 7.
As shown in figure 3, performing etching processing to P-doped zone 7, wherein etching processing includes dry etching and/or wet process
Etching.
As shown in figure 4, carrying out the injection of p-type heavy doping ion to P-doped zone 7, p-type heavily doped region 4 is formed.
As shown in figure 5, forming silicon nitride layer 9.
As shown in fig. 6, etching processing, removes the silicon nitride layer 9 on 2 surface of removing oxide layer and the silicon nitride layer 9 of channel bottom, carve
P-type heavily doped region 4 is divided into two parts heavily doped region of separation by the groove after erosion, forms the first silicon nitride spacer.
As shown in fig. 7, N-type ion injection is carried out to P-doped zone 7, to form N-doped zone 5.
As shown in figure 8, preparing silicon nitride layer 9.
As shown in figure 9, being performed etching to second silicon nitride layer of 2 top of channel and oxide layer, to form the second nitrogen
The bottom of SiClx side wall, the channel is located in substrate 1.
As shown in Figure 10, thermal oxide layer 6 is formed.
As shown in figure 11, polysilicon layer 3 is formed.
As shown in figure 12, after etches polycrystalline silicon layer 3 to the horizontal position of N-doped zone 5, thermal oxidation is carried out, is formed
Closed thermal oxide layer 6.
As shown in figure 13, it forms metal layer and is made annealing treatment, to form metal silicide layer as metal contact layer
8, metal contact layer 8 is carried out to thicken processing, to form metal connection.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, it is contemplated that how what is proposed in the related technology designs
The technical issues of channel resistance and conduction loss of the production method and structure of power device to reduce power device.Therefore, originally
Invention propose a kind of power device preparation method and a kind of power device, pass through the first silicon nitride spacer of preparation and the second nitrogen
SiClx sidewall structure reduces limitation of the photoetching process limitation to groove width, and the lithographic equipment minimum without line width can be real
The preparation of the groove of existing small size, effectively reduces the cost of manufacture of power device, due to the reduction of groove dimensions, unit area
The quantity of interior raceway groove increases, namely increases the width of groove, so that channel resistance is reduced, while reducing device size
It ensure that the Performance And Reliability of device.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of preparation method of power device characterized by comprising
On the substrate for forming P-doped zone, oxide layer, processing is performed etching to form channel to the P-doped zone；
The injection of p-type heavy doping ion is carried out in the channel, to form p-type heavily doped region；
The first silicon nitride layer is formed on the substrate for forming the p-type heavily doped region；
First silicon nitride of the channel and the oxide layer is performed etching, to form the first silicon nitride spacer；
The p-type heavily doped region is performed etching, using the exposure P-doped zone as the N-doped zone of ion to be implanted；
N-type injection is carried out to the N-doped zone of the ion to be implanted, to form N-type heavily doped region；
The second silicon nitride layer is formed on the substrate for forming the N-type heavily doped region；
Second silicon nitride layer of the channel and the oxide layer is performed etching, to form the second silicon nitride side
Wall；
The N-type heavily doped region is performed etching to the substrate；
Thermal oxidation is carried out to the substrate through over etching；
Polysilicon layer is formed in the region of the thermal oxide layer；
Remove first silicon nitride spacer and second silicon nitride spacer；
Oxide layer is formed above the polysilicon layer；
It forms metal layer and is made annealing treatment, to form metal silicide layer as metal contact layer；
The metal contact layer is carried out to thicken processing, to form metal connection.
2. the preparation method of power device according to claim 1, which is characterized in that the element packet of the N-doped zone
Include one of nitrogen, phosphorus and arsenic or a variety of any combination.
3. the preparation method of power device according to claim 2, which is characterized in that the P-doped zone and the p-type
The element of heavily doped region includes boron and/or aluminium.
4. the preparation method of power device according to claim 3, which is characterized in that the formation N-doped zone, institute
The substrate for stating P-doped zone and the p-type heavily doped region is made annealing treatment.
5. the preparation method of power device according to any one of claim 1 to 3, which is characterized in that at annealing
Between 700 degrees Celsius to 1200 degrees Celsius, the duration of annealing is between 10 minutes to 40 minutes.
6. the preparation method of power device according to any one of claim 1 to 4, which is characterized in that first nitrogen
The thickness of SiClx side wall is between 0.5 micron to 3 microns.
7. the preparation method of power device according to any one of claim 1 to 4, which is characterized in that second nitrogen
The thickness of SiClx side wall is between 0.1 micron to 1 micron.
8. the preparation method of power device according to any one of claim 1 to 4, which is characterized in that the p-type doping
The thickness of the oxide layer formed above oxide layer and the polysilicon above area is between 1 micron to 10 microns.
9. a kind of power device, which is characterized in that the power device uses such as function described in any item of the claim 1 to 8
The preparation method of rate device is prepared.
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| CN201510030728.3A CN105870015B (en) | 2015-01-21 | 2015-01-21 | The preparation method and power device of power device |
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| CN201510030728.3A CN105870015B (en) | 2015-01-21 | 2015-01-21 | The preparation method and power device of power device |
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| CN105870015B true CN105870015B (en) | 2018-12-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442214A (en) * | 1994-08-09 | 1995-08-15 | United Microelectronics Corp. | VDMOS transistor and manufacturing method therefor |
| CN102770947A (en) * | 2009-10-20 | 2012-11-07 | 维西埃-硅化物公司 | Super-high density power trench MOSFET |
| CN103377929A (en) * | 2012-04-19 | 2013-10-30 | 北大方正集团有限公司 | Perpendicular double-diffusion metal oxide semiconductor transistor and manufacturing method thereof |
-
2015
- 2015-01-21 CN CN201510030728.3A patent/CN105870015B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442214A (en) * | 1994-08-09 | 1995-08-15 | United Microelectronics Corp. | VDMOS transistor and manufacturing method therefor |
| CN102770947A (en) * | 2009-10-20 | 2012-11-07 | 维西埃-硅化物公司 | Super-high density power trench MOSFET |
| CN103377929A (en) * | 2012-04-19 | 2013-10-30 | 北大方正集团有限公司 | Perpendicular double-diffusion metal oxide semiconductor transistor and manufacturing method thereof |
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| CN105870015A (en) | 2016-08-17 |
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Effective date of registration: 20220721 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |