CN105870015A - Power device manufacturing method and power device - Google Patents
Power device manufacturing method and power device Download PDFInfo
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- CN105870015A CN105870015A CN201510030728.3A CN201510030728A CN105870015A CN 105870015 A CN105870015 A CN 105870015A CN 201510030728 A CN201510030728 A CN 201510030728A CN 105870015 A CN105870015 A CN 105870015A
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Abstract
The invention provides a power device manufacturing method. The method comprises steps: a channel is formed; a P-type heavily-doped region is formed in the channel; a first silicon nitride layer is formed; the first silicon nitride layer above the channel and an oxidation layer is etched to form a first silicon nitride side wall; the P-type heavily-doped region is etched; n-type injection is carried out; a second silicon nitride layer is formed; the second silicon nitride layer above the channel and the oxidation layer is etched to form a second silicon nitride side wall; an N-type heavily-doped region is etched to a substrate; thermal oxidation treatment is carried out; a polycrystalline silicon layer is formed in the thermal oxidation region; the first silicon nitride side wall and the second silicon nitride side wall are removed; an oxidation layer is formed above the polycrystalline silicon layer; a metal layer is formed and annealing treatment is carried out to form a metal contact layer; and metal connection is formed. The invention also provides a power device. Through the technical scheme of the invention, channel resistance can be effectively reduced, and while the size of the device is reduced, the performance and the reliability of the device are ensured.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the preparation side of a kind of power device
Method and a kind of power device.
Background technology
In related semiconductor technology, vertical bilateral diffusion field-effect tranisistor (Vertical Double-
Diffused Metal Oxide Semiconductor, is called for short VDMOS) be a kind of purposes widely
Power device, be vertically disposed between drain electrode and the source electrode of this power device, make electric current at power
Device inside vertically circulates, and adds current density, thus improves rated current.Vertical double diffusion
The most important performance parameter of field-effect transistor is exactly working loss, and working loss can be divided into conducting
Loss, cut-off loss and switching loss three part.Wherein, conduction loss is determined by conducting resistance, cuts
Stopping loss consumption to be affected by reverse leakage current size, during switching loss refers to devices switch, parasitic capacitance is filled
The loss that electric discharge brings.Adapt to the requirement of frequency applications in order to meet power device, reduce power device
Switching loss, improve device operating efficiency, have great importance.
Therefore, how the preparation method of design power device and structure to reduce the raceway groove electricity of power device
Resistance and conduction loss become technical problem urgently to be resolved hurrily.
Summary of the invention
The present invention is based at least one above-mentioned technical problem, it is proposed that the preparation of a kind of power device
Method and a kind of power device.
In view of this, the present invention proposes the preparation method of a kind of power device, including: forming P
Type doped region, oxide layer substrate on, described p-type doped region is performed etching process to form ditch
Road；P-type heavy doping ion injection is carried out, to form p-type heavily doped region at described raceway groove；Formed
The first silicon nitride layer is formed on the described substrate of described p-type heavily doped region；To described raceway groove and described oxygen
Change described first silicon nitride above layer to perform etching, to form the first silicon nitride spacer；To described P
Type heavily doped region performs etching, and mixes as the N-type of ion to be implanted exposing described p-type doped region
Miscellaneous district；The n-type doping district of described ion to be implanted is carried out N-type injection；Forming described N-type
The second silicon nitride layer is formed on the described substrate of heavily doped region；To described raceway groove and described oxide layer
Described second silicon nitride layer perform etching, to form the second silicon nitride spacer；Heavily doped to described N-type
Miscellaneous district performs etching to described substrate；Described substrate through over etching is carried out thermal oxidation；Institute
Polysilicon layer is formed in stating the region of thermal oxide layer；Remove described first silicon nitride spacer and described second
Silicon nitride spacer；Oxide layer is formed above described polysilicon layer；Form metal level and carry out at annealing
Reason, to form metal silicide layer as metal contact layer；Described metal contact layer is thickened place
Reason, to form metal connection.
In this technical scheme, by preparing the first silicon nitride spacer and the second silicon nitride spacer structure,
Reduce photoetching process and limit restriction to groove width, it is not necessary to the minimum lithographic equipment of live width can be real
The preparation of existing undersized groove, effectively reduces the cost of manufacture of power device, due to groove dimensions
Reduction, the increasing number of raceway groove in unit are, namely increase the width of groove, thus reduce
Channel resistance, ensure that the Performance And Reliability of device while reducing device size.
It is worthy of note, compared to the vertical bilateral diffusion field-effect tranisistor constant power in correlation technique
The preparation method of device, the present invention uses self-aligned technology to define the gold of the active area of power device
Belong to contact, decrease two photoetching processes, effectively reduce technique and realize the complexity of process, and
Improve the compatibility of power device and standard technology, it is provided that the possibility of batch production.
In technique scheme, it is preferable that the element in described n-type doping district includes nitrogen, phosphorus and arsenic
In any combination of one or more.
In technique scheme, it is preferable that described p-type doped region and described p-type heavily doped region
Element includes boron and/or aluminium.
In technique scheme, it is preferable that the described n-type doping district of formation, described p-type are mixed
The described substrate of miscellaneous district and described p-type heavily doped region makes annealing treatment.
In technique scheme, it is preferable that be in 700 degrees Celsius Celsius to 1200
Between degree, the duration of annealing is between 10 minutes to 40 minutes.
In technique scheme, it is preferable that it is micro-that the thickness of described first silicon nitride spacer is in 0.5
Rice is between 3 microns.
In technique scheme, it is preferable that it is micro-that the thickness of described second silicon nitride spacer is in 0.1
Rice is between 1 micron.
In technique scheme, it is preferable that the thickness of described silicon gate structure is in 0.3 micron to 3
Between Wei meter.
In technique scheme, it is preferable that the thickness of described oxide layer be in 1 micron micro-to 10
Between meter.
According to the second aspect of the invention, it is also proposed that a kind of power device, described power device uses
The preparation method of the power device as described in above-mentioned any one technical scheme is prepared from.
By above technical scheme, tie by preparing the first silicon nitride spacer and the second silicon nitride spacer
Structure, reduces photoetching process and limits restriction to groove width, it is not necessary to the minimum lithographic equipment of live width is i.e.
The preparation of undersized groove can be realized, effectively reduce the cost of manufacture of power device, due to groove
The reduction of size, the increasing number of raceway groove in unit are, namely increase the width of groove, thus
Reduce channel resistance, while reducing device size, ensure that the Performance And Reliability of device.
It is worthy of note, compared to the vertical bilateral diffusion field-effect tranisistor constant power in correlation technique
The preparation method of device, the present invention uses self-aligned technology to define the gold of the active area of power device
Belong to contact, decrease two photoetching processes, effectively reduce technique and realize the complexity of process, and
Improve the compatibility of power device and standard technology, it is provided that the possibility of batch production.
Accompanying drawing explanation
Fig. 1 shows the flow process signal of the preparation method of power device according to an embodiment of the invention
Figure；
Fig. 2 to Figure 13 shows cuing open of the preparation method of power device according to an embodiment of the invention
Face schematic diagram, wherein, the structure name of reference and correspondence thereof is referred to as: 1 substrate, 2 oxide layers, and 3
Polysilicon layer, 4P type heavily doped region, 5N type doped region, 6 thermal oxide layers, 7P type doped region, 8
Metal contact layer, 9 silicon nitride layers (the first silicon nitride spacer, the second silicon nitride spacer).
Detailed description of the invention
In order to be more clearly understood that the above-mentioned purpose of the present invention, feature and advantage, below in conjunction with attached
The present invention is further described in detail by figure and detailed description of the invention.It should be noted that not
In the case of conflict, the feature in embodiments herein and embodiment can be mutually combined.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but,
The present invention can implement to use other to be different from other modes described here, therefore, and the present invention
Protection domain do not limited by following public specific embodiment.
Fig. 1 shows the flow process signal of the preparation method of power device according to an embodiment of the invention
Figure.
As it is shown in figure 1, the preparation method of power device according to an embodiment of the invention, including: step
Rapid 102, on the substrate forming p-type doped region, oxide layer, described p-type doped region is carved
Erosion processes to form raceway groove；Step 104, carries out p-type heavy doping ion injection at described raceway groove, with
Form p-type heavily doped region；Step 106, shape on the described substrate forming described p-type heavily doped region
Become the first silicon nitride layer；Step 108, to described raceway groove and described first nitrogen of described oxide layer
SiClx performs etching, to form the first silicon nitride spacer；Step 110, to described p-type heavily doped region
Perform etching, to expose the described p-type doped region n-type doping district as ion to be implanted；Step
112, the n-type doping district of described ion to be implanted is carried out N-type injection；Step 114, is being formed
The second silicon nitride layer is formed on the described substrate of described N-type heavily doped region；Step 116, to described ditch
Described second silicon nitride layer of road and described oxide layer performs etching, to form the second silicon nitride side
Wall；Step 118, performs etching to described substrate described N-type heavily doped region；Step 120 is right
Thermal oxidation is carried out through the described substrate of over etching；Step 122, in the region of described thermal oxide layer
Interior formation polysilicon layer；Step 124, removes described first silicon nitride spacer and described second silicon nitride
Side wall；Step 126, forms oxide layer above described polysilicon layer；Step 128, forms metal
Layer also makes annealing treatment, to form metal silicide layer as metal contact layer；Step 130 is right
Described metal contact layer carries out thickening process, to form metal connection.
In this technical scheme, by preparing the first silicon nitride spacer and the second silicon nitride spacer structure,
Reduce photoetching process and limit restriction to groove width, it is not necessary to the minimum lithographic equipment of live width can be real
The preparation of existing undersized groove, effectively reduces the cost of manufacture of power device, due to groove dimensions
Reduction, the increasing number of raceway groove in unit are, namely increase the width of groove, thus reduce
Channel resistance, ensure that the Performance And Reliability of device while reducing device size.
It is worthy of note, compared to the vertical bilateral diffusion field-effect tranisistor constant power in correlation technique
The preparation method of device, the present invention uses self-aligned technology to define the gold of the active area of power device
Belong to contact, decrease two photoetching processes, effectively reduce technique and realize the complexity of process, and
Improve the compatibility of power device and standard technology, it is provided that the possibility of batch production.
In technique scheme, it is preferable that the element in described n-type doping district includes nitrogen, phosphorus and arsenic
In any combination of one or more.
In technique scheme, it is preferable that described p-type doped region and described p-type heavily doped region
Element includes boron and/or aluminium.
In technique scheme, it is preferable that the described n-type doping district of formation, described p-type are mixed
The described substrate of miscellaneous district and described p-type heavily doped region makes annealing treatment.
In technique scheme, it is preferable that be in 700 degrees Celsius Celsius to 1200
Between degree, the duration of annealing is between 10 minutes to 40 minutes.
In technique scheme, it is preferable that it is micro-that the thickness of described first silicon nitride spacer is in 0.5
Rice is between 3 microns.
In technique scheme, it is preferable that it is micro-that the thickness of described second silicon nitride spacer is in 0.1
Rice is between 1 micron.
In technique scheme, it is preferable that the thickness of described silicon gate structure is in 0.3 micron to 3
Between Wei meter.
In technique scheme, it is preferable that the thickness of described oxide layer be in 1 micron micro-to 10
Between meter.
According to the second aspect of the invention, it is also proposed that a kind of power device, including: as any of the above-described
The preparation method of item power device described in technical scheme is prepared from.
Below in conjunction with Fig. 2 to Figure 13 pair, the preparation side of power device according to an embodiment of the invention
Method illustrates.
As in figure 2 it is shown, carry out p-type ion implanting on substrate 1 surface, form p-type doped region 7,
Above p-type doped region 7, form oxide layer 2, oxide layer 2 is patterned process, with shape
Becoming groove, the bottom-exposed of groove goes out p-type doped region 7.
As it is shown on figure 3, p-type doped region 7 is performed etching process, wherein, etching processing includes doing
Method etching and/or wet etching.
As shown in Figure 4, p-type doped region 7 is carried out p-type heavy doping ion injection, form p-type weight
Doped region 4.
As it is shown in figure 5, form silicon nitride layer 9.
As shown in Figure 6, etching processing, remove silicon nitride layer 9 and the channel bottom on removing oxide layer 2 surface
Silicon nitride layer 9, p-type heavily doped region 4 is divided into two parts heavy doping of separation by the groove after etching
District, forms the first silicon nitride spacer.
As it is shown in fig. 7, p-type doped region 7 is carried out N-type ion implanting, to form n-type doping
District 5.
As shown in Figure 8, silicon nitride layer 9 is prepared.
As it is shown in figure 9, described second silicon nitride layer above raceway groove and oxide layer 2 is performed etching,
To form the second silicon nitride spacer, the bottom of described raceway groove is positioned in substrate 1.
As shown in Figure 10, thermal oxide layer 6 is formed.
As shown in figure 11, polysilicon layer 3 is formed.
As shown in figure 12, after the horizontal level in etches polycrystalline silicon layer 3 to n-type doping district 5, carry out
Thermal oxidation, forms the thermal oxide layer 6 closed.
As shown in figure 13, form metal level and make annealing treatment, to form metal silicide layer work
For metal contact layer 8, metal contact layer 8 is thickened process, to form metal connection.
Technical scheme is described in detail, it is contemplated that correlation technique proposes above in association with accompanying drawing
The preparation method of how design power device and structure to reduce channel resistance and the conducting of power device
The technical problem of loss.Therefore, the present invention proposes the preparation method of a kind of power device and a kind of merit
Rate device, by preparing the first silicon nitride spacer and the second silicon nitride spacer structure, reduces photoetching work
Skill limits restriction to groove width, it is not necessary to the minimum lithographic equipment of live width can realize undersized ditch
The preparation of groove, effectively reduces the cost of manufacture of power device, due to the reduction of groove dimensions, unit
The increasing number of raceway groove in area, namely increase the width of groove, thus reduce channel resistance,
The Performance And Reliability of device is ensure that while reducing device size.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for
For those skilled in the art, the present invention can have various modifications and variations.All essences in the present invention
Within god and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention
Protection domain within.
Claims (10)
1. the preparation method of a power device, it is characterised in that including:
On the substrate forming p-type doped region, oxide layer, described p-type doped region is performed etching place
Reason is to form raceway groove；
P-type heavy doping ion injection is carried out, to form p-type heavily doped region at described raceway groove；
The described substrate forming described p-type heavily doped region forms the first silicon nitride layer；
Described first silicon nitride of described raceway groove and described oxide layer is performed etching, to form
One silicon nitride spacer；
Described p-type heavily doped region is performed etching, using expose described p-type doped region as to be implanted from
The n-type doping district of son；
The n-type doping district of described ion to be implanted is carried out N-type injection；
The described substrate forming described N-type heavily doped region forms the second silicon nitride layer；
Described second silicon nitride layer of described raceway groove and described oxide layer is performed etching, to be formed
Second silicon nitride spacer；
Described N-type heavily doped region is performed etching to described substrate；
Described substrate through over etching is carried out thermal oxidation；
Polysilicon layer is formed in the region of described thermal oxide layer；
Remove described first silicon nitride spacer and described second silicon nitride spacer；
Oxide layer is formed above described polysilicon layer；
Form metal level and make annealing treatment, to form metal silicide layer as metal contact layer；
Described metal contact layer is thickened process, to form metal connection.
The preparation method of power device the most according to claim 1, it is characterised in that described
The element in n-type doping district includes any combination of one or more in nitrogen, phosphorus and arsenic.
The preparation method of power device the most according to claim 2, it is characterised in that described
The element of p-type doped region and described p-type heavily doped region includes boron and/or aluminium.
The preparation method of power device the most according to claim 3, it is characterised in that to shape
The described substrate becoming described n-type doping district, described p-type doped region and described p-type heavily doped region enters
Row annealing.
The preparation method of power device the most according to any one of claim 1 to 4, it is special
Levy and be, be between 700 degrees Celsius to 1200 degrees Celsius, continuing of annealing
Time is between 10 minutes to 40 minutes.
The preparation method of power device the most according to any one of claim 1 to 4, it is special
Levying and be, the thickness of described first silicon nitride spacer is between 0.5 micron to 3 microns.
The preparation method of power device the most according to any one of claim 1 to 4, it is special
Levying and be, the thickness of described second silicon nitride spacer is between 0.1 micron to 1 micron.
The preparation method of power device the most according to any one of claim 1 to 4, it is special
Levying and be, the thickness of described silicon gate structure is between 0.3 micron to 3 microns.
The preparation method of power device the most according to any one of claim 1 to 4, it is special
Levying and be, the thickness of described oxide layer is between 1 micron to 10 microns.
10. a power device, it is characterised in that described power device use such as claim 1 to
The preparation method of the power device according to any one of 9 is prepared from.
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| CN201510030728.3A CN105870015B (en) | 2015-01-21 | 2015-01-21 | The preparation method and power device of power device |
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| CN105870015B CN105870015B (en) | 2018-12-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442214A (en) * | 1994-08-09 | 1995-08-15 | United Microelectronics Corp. | VDMOS transistor and manufacturing method therefor |
| CN102770947A (en) * | 2009-10-20 | 2012-11-07 | 维西埃-硅化物公司 | Super-high density power trench MOSFET |
| CN103377929A (en) * | 2012-04-19 | 2013-10-30 | 北大方正集团有限公司 | Perpendicular double-diffusion metal oxide semiconductor transistor and manufacturing method thereof |
-
2015
- 2015-01-21 CN CN201510030728.3A patent/CN105870015B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5442214A (en) * | 1994-08-09 | 1995-08-15 | United Microelectronics Corp. | VDMOS transistor and manufacturing method therefor |
| CN102770947A (en) * | 2009-10-20 | 2012-11-07 | 维西埃-硅化物公司 | Super-high density power trench MOSFET |
| CN103377929A (en) * | 2012-04-19 | 2013-10-30 | 北大方正集团有限公司 | Perpendicular double-diffusion metal oxide semiconductor transistor and manufacturing method thereof |
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| CN105870015B (en) | 2018-12-28 |
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Effective date of registration: 20220721 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |