CN105868067A - Debugging interface switching circuit - Google Patents
Debugging interface switching circuit Download PDFInfo
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- CN105868067A CN105868067A CN201610275422.9A CN201610275422A CN105868067A CN 105868067 A CN105868067 A CN 105868067A CN 201610275422 A CN201610275422 A CN 201610275422A CN 105868067 A CN105868067 A CN 105868067A
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- debugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
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- General Engineering & Computer Science (AREA)
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- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses a debugging interface switching circuit and relates to a debugging technique of a chip or a circuit module. The debugging interface switching circuit comprises a debugging signal input interface selection circuit and a debugging signal output interface circuit, wherein the debugging signal input interface selection circuit comprises a first-class debugging signal input interface, a second-class debugging signal input interface, a switching control signal input end and a first debugged circuit connecting end; the debugging signal output interface circuit comprises a second debugged circuit connecting end, a first-class debugging signal output interface and a second-class debugging signal output interface; the debugging signal output interface circuit is used for outputting signals from the second debugged circuit connecting end to the first-class debugging signal output interface and the second-class debugging signal output interface simultaneously.
Description
Technical field
The invention belongs to digital circuit technique, particularly to chip or the debugging technique of circuit module.
Background technology
In general international standard (such as CPCI, VPX etc.), when after a circuit module access system, the debugging interface of this circuit module is usually located in the power connector being connected with system chassis backboard, by backboard, the debugging interface of module is transferred to cabinet panel, cabinet panel connects external debugger module is debugged.But in actual design, the convenience debugged for single circuit module (not having backboard), generally also need the debugging interface of this circuit module to export the front panel (opposite side relative with backboard) of circuit module, directly external debugger is connected to module faceplate and debugs.
Present way is that by resistance jumper connection or directly the debugging interface holding wire of circuit module is connected to cabinet panel by the way of bifurcated or/and module front panel, it is achieved the front panel of module is or/and cabinet panel debugging.
Being not difficult to suspect, existing debugging interface circuit scheme there is problems in that
1. resistance jumper connection scheme is easily caused module BOM(BOM: BOM during debugging and after debug) inconsistent, jumper connection resistance could be operated after dismounting module housing may be needed simultaneously, process is numerous and diverse；
2. directly bifurcated scheme is easily generated problems of Signal Integrity (signal integrity: refer to the quality of signal), thus causes debugging interface obstructed or unstable or speed is slow.
Summary of the invention
In order to solve above-mentioned technical problem, the invention provides the circuit module debugging interface switching circuit of a kind of convenient switching.
The technical solution used in the present invention includes debugging signal input interface selection circuit and debugging signal output interface circuit, wherein,
Debugging signal input interface selection circuit includes that first kind debugging signal input interface, Equations of The Second Kind debugging signal input interface, switch-over control signal input and first are adjusted circuit connecting end；Debugging signal input interface selection circuit exports first for the signal that the first kind debugs under the effect of switch-over control signal signal input interface and is adjusted circuit connecting end or Equations of The Second Kind is debugged the signal of signal input interface export first and adjusted circuit connecting end；
Described debugging signal output interface circuit includes that second is adjusted circuit connecting end, first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface；Debugging signal output interface circuit is for being simultaneously outputting to first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface by second by the signal adjusting circuit connecting end.
Further, debugging signal input interface selection circuit includes at least one MUX；Each MUX includes first input end, the second input, switching control end and outfan, wherein first input end is as a first kind debugging signal input interface, second input is as an Equations of The Second Kind debugging signal input interface, and outfan is adjusted circuit connecting end as one first；The switching control end of each MUX is connected together as switch-over control signal input.
Further, debugging signal output interface circuit includes the driver of at least one 2bit bit wide；Each driver has two inputs and two outfans；Two inputs are connected together as one second and are adjusted circuit connecting end, and an outfan is as a first kind debugging signal output interface, and another outfan is as an Equations of The Second Kind debugging signal output interface.
In sum, owing to have employed technique scheme, the invention has the beneficial effects as follows:
The present invention can be simultaneously connected with module front panel debugging interface and cabinet panel debugging interface, can the most easily select to use any debugging interface that circuit module is debugged by switch-over control signal, solve the BOM problem of management of traditional scheme, numerous and diverse dismounting working-procedure problem and potential problems of Signal Integrity, make debugging interface flexible, stable, at a high speed, reliably, improve debugging efficiency, reduce module because of the risk of debugging interface problem reprint (change module hardware design again).
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is schematic block circuit diagram of the present invention.
Fig. 2 is the schematic block circuit diagram of one specific embodiment of the present invention.
Fig. 3 is the truth table of MUX.
Detailed description of the invention
All features disclosed in this specification, or disclosed all methods or during step, in addition to mutually exclusive feature and/or step, all can combine by any way.
Any feature disclosed in this specification, unless specifically stated otherwise, all can be by other equivalences or there is the alternative features of similar purpose replaced.I.e., unless specifically stated otherwise, an example during each feature is a series of equivalence or similar characteristics.
As it is shown in figure 1, the present invention includes debugging signal input interface selection circuit and debugging signal output interface circuit.
Debugging signal input interface selection circuit includes that first kind debugging signal input interface, Equations of The Second Kind debugging signal input interface, switch-over control signal input and first are adjusted circuit connecting end；Debugging signal input interface selection circuit exports first for the signal that the first kind debugs under the effect of switch-over control signal signal input interface and is adjusted circuit connecting end or Equations of The Second Kind is debugged the signal of signal input interface export first and adjusted circuit connecting end.
See circuit on the left of Fig. 1, the present embodiment have employed two and above MUX.Each MUX includes input I0, input I1, switching control end S and outfan Z, wherein input I0As a first kind debugging signal input interface, input I1As an Equations of The Second Kind debugging signal input interface, outfan Z is adjusted circuit connecting end as one first；The switching control end S of each MUX is connected together as switch-over control signal input.
Wherein, the truth table of MUX such as Fig. 3, when S end is low level, MUX is by input I0Signal export on outfan Z, when S end is high level, MUX is by input I1Signal export on outfan Z.
Described debugging signal output interface circuit includes that second is adjusted circuit connecting end, first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface；Debugging signal output interface circuit is for being simultaneously outputting to first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface by second by the signal adjusting circuit connecting end.
See the right side circuit of Fig. 1, the present embodiment is debugged signal output interface circuit and includes the driver of at least one 2bit bit wide；Each driver has two ports of A1, A2 and two ports of B1, B2, and A1 port is connected by bi-directional drive element with B1 port, and A2 port is connected by bi-directional drive element with B2 port；Two ports of A1, A2 are connected together as one second and are adjusted circuit connecting end, and B1 port is as a first kind debugging signal output interface, and B2 port is as an Equations of The Second Kind debugging signal output interface.Each bi-directional drive element can be arranged to the bi-directional drive element of driver in some direction one-way conduction, such as the present embodiment and both be set to A1 port to B1 port one-way transmission signal, and A2 port is to B2 port one-way transmission signal.
The debugging circuit that the present invention mentions can be the chips such as FPGA, DSP, CPU.
Seeing Fig. 2, the present embodiment, as a example by the debugging interface (jtag interface) of FPGA, is expanded on further the use process of the present invention.
All kinds of inputs of the jtag interface of FPGA that will be adjusted, including mode selection terminal TMS, clock signal terminal TCK and data input pin TDI, adjusted with debugging three first of signal input interface selection circuit that circuit connecting end is corresponding to be connected, three first kind debugging signal input interfaces of debugging signal input interface selection circuit and three of the module front panel debugging interface corresponding connections of debugging signal output part, three Equations of The Second Kind debugging signal input interfaces are connected with three debugging signal output parts of cabinet panel debugging interface, switch-over control signal input is connected with the selection signal pins of module front panel debugging interface.
The outfan of the jtag interface of FPGA that will be adjusted, including data output end TDO, circuit connecting end is adjusted to be connected with one second of debugging signal output interface circuit, the first kind debugging signal output interface of debugging signal output interface circuit is connected with the debugging signal input part of module front panel debugging interface, and Equations of The Second Kind debugging signal output interface is connected with the debugging signal input part of cabinet panel debugging interface.
After connection, by the selection signal pins output logic signal 0 or 1 of module front panel debugging interface, the debugging of module front panel or cabinet panel modulation can be selected easily.
The invention is not limited in aforesaid detailed description of the invention.The present invention expands to any new feature disclosed in this manual or any new combination, and the arbitrary new method that discloses or the step of process or any new combination.
Claims (3)
1. a debugging interface switching circuit, it is characterised in that include debugging signal input interface selection circuit and debugging signal output interface circuit, wherein,
Debugging signal input interface selection circuit includes that first kind debugging signal input interface, Equations of The Second Kind debugging signal input interface, switch-over control signal input and first are adjusted circuit connecting end；Debugging signal input interface selection circuit exports first for the signal that the first kind debugs under the effect of switch-over control signal signal input interface and is adjusted circuit connecting end or Equations of The Second Kind is debugged the signal of signal input interface export first and adjusted circuit connecting end；
Described debugging signal output interface circuit includes that second is adjusted circuit connecting end, first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface；Debugging signal output interface circuit is for being simultaneously outputting to first kind debugging signal output interface and Equations of The Second Kind debugging signal output interface by second by the signal adjusting circuit connecting end.
A kind of debugging interface switching circuit the most according to claim 1, it is characterised in that debugging signal input interface selection circuit includes at least one MUX；Each MUX includes first input end, the second input, switching control end and outfan, wherein first input end is as a first kind debugging signal input interface, second input is as an Equations of The Second Kind debugging signal input interface, and outfan is adjusted circuit connecting end as one first；The switching control end of each MUX is connected together as switch-over control signal input.
A kind of debugging interface switching circuit the most according to claim 1, it is characterised in that debugging signal output interface circuit includes the driver of at least one 2bit bit wide；Each driver has two inputs and two outfans；Two inputs are connected together as one second and are adjusted circuit connecting end, and an outfan is as a first kind debugging signal output interface, and another outfan is as an Equations of The Second Kind debugging signal output interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610275422.9A CN105868067B (en) | 2016-04-29 | 2016-04-29 | A kind of debugging interface switching circuit |
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| CN201610275422.9A CN105868067B (en) | 2016-04-29 | 2016-04-29 | A kind of debugging interface switching circuit |
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| CN105868067A true CN105868067A (en) | 2016-08-17 |
| CN105868067B CN105868067B (en) | 2018-09-18 |
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| JP2002268913A (en) * | 2001-03-09 | 2002-09-20 | Sharp Corp | Inspection instrument |
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| CN101359307A (en) * | 2007-08-03 | 2009-02-04 | 英业达股份有限公司 | Test device of SAS channel and test method thereof |
| CN102289419A (en) * | 2010-06-17 | 2011-12-21 | 珠海全志科技有限公司 | Multiplex SOC(system on a chip) integrated circuit for functional interface and debugging interface |
| CN103136138A (en) * | 2011-11-24 | 2013-06-05 | 炬力集成电路设计有限公司 | Chip, chip debugging method and communication method for chip and external devices |
| CN103389932A (en) * | 2012-05-07 | 2013-11-13 | 鸿富锦精密工业（深圳）有限公司 | Interface testing device |
| CN104484268A (en) * | 2014-11-21 | 2015-04-01 | 厦门美图移动科技有限公司 | Debugging method and mobile terminal |
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2016
- 2016-04-29 CN CN201610275422.9A patent/CN105868067B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002268913A (en) * | 2001-03-09 | 2002-09-20 | Sharp Corp | Inspection instrument |
| EP1932788A1 (en) * | 2006-12-01 | 2008-06-18 | Morelli Handling and Robotic Systems S.a.s. di Morelli Massimo & C. | Automatic conveyor apparatus for feeding articles towards a pick up station |
| CN101359307A (en) * | 2007-08-03 | 2009-02-04 | 英业达股份有限公司 | Test device of SAS channel and test method thereof |
| CN102289419A (en) * | 2010-06-17 | 2011-12-21 | 珠海全志科技有限公司 | Multiplex SOC(system on a chip) integrated circuit for functional interface and debugging interface |
| CN103136138A (en) * | 2011-11-24 | 2013-06-05 | 炬力集成电路设计有限公司 | Chip, chip debugging method and communication method for chip and external devices |
| CN103389932A (en) * | 2012-05-07 | 2013-11-13 | 鸿富锦精密工业（深圳）有限公司 | Interface testing device |
| CN104484268A (en) * | 2014-11-21 | 2015-04-01 | 厦门美图移动科技有限公司 | Debugging method and mobile terminal |
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