CN105845591A - Method of monitoring iron implantation angle - Google Patents
Method of monitoring iron implantation angle Download PDFInfo
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- CN105845591A CN105845591A CN201510023599.5A CN201510023599A CN105845591A CN 105845591 A CN105845591 A CN 105845591A CN 201510023599 A CN201510023599 A CN 201510023599A CN 105845591 A CN105845591 A CN 105845591A
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Abstract
The invention provides a method of monitoring the ion implantation angle, comprising the following steps: providing a monitoring wafer, wherein the monitoring wafer includes a semiconductor substrate, a trench formed in the front of the semiconductor substrate and a polycrystalline silicon layer covering the bottom and sidewalls of the trench and the surface of the semiconductor substrate, and the polycrystalline silicon layer is not doped; carrying out inclined ion implantation along a direction on the polycrystalline silicon layer, wherein the acute included angle between the direction of inclined ion implantation and the vertical direction is defined as an implantation angle Alpha; removing the undoped polycrystalline silicon layer, and measuring the width w of the removed undoped polycrystalline silicon layer on the bottom of the trench and the height h of the remaining doped polycrystalline silicon layer on the sidewalls of the trench; and calculating the angle Alpha based on a formula. The monitoring wafer is provided to monitor the ion implantation angle through a non-electrical method. The method provided by the invention is simple and easy to operate, the analysis period is short, and the measurement data is accurate.
Description
Technical field
The present invention relates to technical field of semiconductors, monitor ion implanting angle in particular to one
The method of degree.
Background technology
Ion implanting is the very important technology of one during modern integrated circuits manufactures, and it utilizes
Ion implantation apparatus realizes the doping of quasiconductor, will specifically foreign atom with the side of acceleration of ions
Formula is injected in silicon semiconductor crystal and is changed its conductive characteristic and ultimately form transistor arrangement.
Impurity be accurately positioned the key factor being to ensure that advanced device optimal operational condition.
For ion implanting, dosage, energy and ion implantation angle are required for being accurately controlled,
The performance of the semiconductor device that guarantee is formed meets technological requirement, and ion implantation angle is different
Will result in the ion implanting degree of depth to change and affect the electrical quantity of device, therefore, to ion implanting angle
Degree implementation is accurately controlled the most necessary.
The monitoring method of the implant angle that traditional angle-tilt ion is injected is typically by 9 platelets
Circle carries out TW (thermal wave) heat wave and measures or sheet resistance Rs measurement after annealing, and then
Draw V-curve define the fluctuation of implant angle and how to correct.But said method analysis
Cycle is long, operation complexity, it is impossible to directly and be accurately monitored implant angle.
Therefore, it is necessary to propose a kind of new monitoring method, to solve the deficiencies in the prior art.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will be concrete real
Execute in mode part and further describe.The Summary of the present invention is not meant to
Attempt to limit key feature and the essential features of technical scheme required for protection, less
Mean the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, the present invention provides a kind of monitoring ion implantation angle
Method, including:
Thering is provided monitoring wafer, described monitoring wafer includes Semiconductor substrate and is formed at described half
The groove of conductor substrate face and cover described channel bottom and sidewall and described quasiconductor
The polysilicon layer of substrate surface, wherein, described polysilicon layer is not doped；
Described polysilicon layer carries out angle-tilt ion in one direction inject, wherein, define institute
The acute angle stating angle-tilt ion injection direction and vertical direction is implant angle α；
Remove undoped polysilicon layer, and measurement is positioned at the removed of described channel bottom and does not mixes
The width w of miscellaneous polysilicon layer, and the residue doped polysilicon layer being positioned on described trenched side-wall
Height h；
Calculating described implant angle α with formula, wherein said formula is:
Further, the ammonia spirit etching using dilution removes described undoped polysilicon layer.
Further, the depth-to-width ratio of described groove is more than or equal to 1.
Further, the value of described w is less than or equal to the width of groove.
Further, the value of described h is less than or equal to the degree of depth of groove.
Further, the making step of described monitoring wafer includes:
Semiconductor substrate is provided, the surface of described Semiconductor substrate is formed hard mask layer；
It is sequentially etched described hard mask layer and described Semiconductor substrate, to form groove；
Remove remaining described hard mask layer；
The surface of the bottom of described groove and sidewall and described Semiconductor substrate is formed many
Crystal silicon layer, described polysilicon layer is not doped.
Further, described hard mask layer includes the folded of oxide skin(coating) from bottom to top and nitride layer
Layer.
Further, use thermal oxidation method to form described oxide skin(coating).
Further, described nitride layer is silicon nitride layer.
In sum, the method according to the invention, it is provided that monitoring wafer is supervised by non-electrical method
Measured ion implant angle, the method is simple, easily operates, and analytical cycle is short, and measurement data is accurate.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached
Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-1D shows that the making step of monitoring wafer used herein implements institute successively
Obtain the generalized section of device；
It is right that Fig. 2 A-2C shows that the method for the monitoring ion implantation angle of the present invention is implemented successively
The generalized section of wafer should be monitored；
Fig. 3 shows the graph of a relation of implant angle α Yu w and h；
Fig. 4 shows the flow process that the method for the monitoring ion implantation angle of the present invention is implemented successively
Figure.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide to the present invention more
Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention
Can be carried out without these details one or more.In other example, in order to keep away
Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, it is open thoroughly with complete to provide these embodiments to make
Entirely, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
In order to clear, the size in Ceng He district and relative size may be exaggerated.The most identical attached
Figure labelling represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... adjacent ", " connect
To " or " being coupled to " other element or during layer, its can directly on other element or layer,
Adjacent thereto, be connected or coupled to other element or layer, or can exist element between two parties or
Layer.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " directly connect
Receive " or " being directly coupled to " other element or during layer, the most there is not element between two parties or layer.
Although it should be understood that and term first, second, third, etc. can being used to describe various element, portion
Part, district, floor and/or part, these elements, parts, district, floor and/or part the most should be by
These terms limit.These terms are used merely to distinguish an element, parts, district, floor or portion
Divide and another element, parts, district, floor or part.Therefore, without departing from present invention teach that
Under, the first element discussed below, parts, district, floor or part be represented by the second element,
Parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ...
Under ", " ... on ", " above " etc., here can describe for convenience and be used
Thus shown in figure a element or feature and other element or the relation of feature are described.Should
Understanding, in addition to the orientation shown in figure, spatial relationship term is intended to also include using and grasping
The different orientation of the device in work.Such as, if the device upset in accompanying drawing, then, describe
To take for " below other element " or " under it " or " under it " element or feature
To for other element or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " upper and lower two orientations can be included.Device can additionally be orientated (90-degree rotation or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this
Bright restriction.When using at this, " ", " " and " described/to be somebody's turn to do " of singulative
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " forms " and/or " including ", when using in this specification, determine described feature,
The existence of integer, step, operation, element and/or parts, but be not excluded for one or more its
The existence of its feature, integer, step, operation, element, parts and/or group or interpolation.
When using at this, term "and/or" includes any and all combination of relevant Listed Items.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to
The technical scheme that the explaination present invention proposes.Presently preferred embodiments of the present invention is described in detail as follows, so
And in addition to these describe in detail, the present invention can also have other embodiments.
Exemplary embodiment
Below with reference to Figure 1A-1D, Fig. 2 A-2C, Fig. 3 and Fig. 4 to the monitoring of the present invention from
The method of sub-implant angle is described in detail.
First, step 401 is performed, it is provided that monitoring wafer, described monitoring wafer includes quasiconductor
Substrate and be formed at the groove in described Semiconductor substrate front and cover described channel bottom
And sidewall and the polysilicon layer of described semiconductor substrate surface, wherein, described polysilicon layer is not
It is doped.
Exemplarily, with reference to Figure 1A-1D, a kind of production method of monitoring wafer is done further
Describe.
As shown in Figure 1A, it is provided that Semiconductor substrate 100.Semiconductor substrate 100 can be with
Under at least one in the material that is previously mentioned: silicon, silicon-on-insulator (SOI), insulator upper strata
Stacking SiGe (S-SiGeOI), germanium on insulator SiClx on folded silicon (SSOI), insulator
And germanium on insulator (GeOI) etc. (SiGeOI).As an example, described partly lead
Body substrate 100 is silicon substrate.
Then, as shown in Figure 1B, the surface of described Semiconductor substrate 100 is formed firmly cover
Film layer.Exemplarily, described hard mask layer includes oxide skin(coating) 101 from bottom to top and nitridation
The lamination of nitride layer 102.Alternatively, described oxide skin(coating) 101 is silicon oxide layer.Can be selected for
The methods such as chemical gaseous phase deposition, magnetron sputtering, thermal oxide form described silicon oxide layer.This reality
Execute in example, preferably use thermal oxidation method to form described oxide skin(coating).Alternatively, described nitridation
Nitride layer 102 is silicon nitride layer.Any deposition process shape well known to those skilled in the art can be used
Become described nitride layer, such as, Plasma Enhanced Chemical Vapor Deposition (PECVD) etc..
Although it is noted that Figure 1B showing in positive and negative the two of Semiconductor substrate 100
Face is each formed with hard mask layer, it is contemplated that only become the one side of groove in preboarding
Formation hard mask layer.
Then, as shown in Figure 1 C, described hard mask layer and described Semiconductor substrate it are sequentially etched
100, to form groove 103.
Any applicable lithographic method can be used to carry out described etching, such as wet etching or dry method
Etching, dry method etch technology includes but not limited to: the erosion of reactive ion etching (RIE), ion beam
Quarter, plasma etching or cut.Enter preferably by one or more RIE step
Row dry etching.Wet etch method can use hydrofluoric acid solution, such as buffer oxide etch agent
(buffer oxide etchant (BOE)) or Fluohydric acid. buffer solution
(buffer solution of hydrofluoric acid(BHF)).Alternatively, etch at groove 103
During, control the depth-to-width ratio of groove more than or equal to 1.
Removing remaining hard mask layer, the method that can use wet-cleaning, therefore not to repeat here.
Then, as shown in figure ip, at the bottom of described groove 103 and sidewall and described half
Forming polysilicon layer 104 on the surface of conductor substrate 100, described polysilicon layer 104 is not carried out
Doping.
The forming method of polysilicon layer 104 can be selected for low-pressure chemical vapor phase deposition (LPCVD) work
Skill.The process conditions forming described polysilicon layer include: reacting gas is silane (SiH4), institute
The range of flow stating silane can be 100～200 cc/min (sccm), such as 150sccm；
In reaction chamber, temperature range can be 700～750 degrees Celsius；Reaction cavity pressure can be 250～
350 millis millimetres of mercury (mTorr), such as 300mTorr；Described reacting gas may also include buffering
Gas, described buffer gas can be helium (He) or nitrogen, the flow model of described helium and nitrogen
Enclosing can be 5～20 liters/min (slm), such as 8slm, 10slm or 15slm.
Monitoring wafer can be obtained by above-mentioned steps.
Then, perform step 402, described polysilicon layer is carried out inclination in one direction from
Son injects, and wherein, the acute angle defining described angle-tilt ion injection direction and vertical direction is
Implant angle α.
By monitoring wafer, implant angle α can be entered before conventional ion injection processing procedure is carried out
Row monitoring, to ensure that subsequent ion injects controllability and the accuracy of implant angle of processing procedure.
As shown in Figure 2 A, after performing the ion implanting that implant angle is α, wafer 20 is monitored
On Polysilicon layer portions undoped formation undoped polysilicon layer 104b, part be doped
Form doped polysilicon layer 104a.Dopant ion can use the ion that semiconductor applications is conventional,
Such as BF2。
Then, perform step 403, remove undoped polysilicon layer, and measurement is positioned at described ditch
The width w of the removed undoped polysilicon layer of trench bottom, and it is positioned at described trenched side-wall
On residue doped polysilicon layer height h.
Exemplarily, use undoped polysilicon layer that doped polysilicon layer and Semiconductor substrate are had
There is the solution of high etching selection ratio, remove described for doped polysilicon layer.In the present embodiment,
Ammonia spirit preferably with dilution removes described undoped polysilicon layer.
The depth-to-width ratio of groove affects the degree of depth and the scope of ion implanting, in one example, such as figure
Shown in 2B, after removing unadulterated polysilicon layer, measure the quilt being positioned at described channel bottom
The width w of undoped polysilicon layer removed, and the residue being positioned on described trenched side-wall mixes
The height h of miscellaneous polysilicon layer, in this example, width w less than the width of groove, and due to
Doped polysilicon layer on trenched side-wall all remains, therefore height h and the deep equality of groove.
In another example, as shown in Figure 2 C, the undoped polysilicon layer of channel bottom is by entirely
Portion removes, and therefore width w is approximately equal to the width of groove, is positioned on described trenched side-wall
The height h of residue doped polysilicon layer is less than the degree of depth of groove.
Then, perform step 404, calculate described implant angle α with formula.
As it is shown on figure 3, implant angle α and the width w defined in abovementioned steps and height h
Between relation can represent with tangent, and then derive obtain implant angle α computing formula:
By measuring in step 403 in obtained width w value and height h value substitution
State formula, the value of implant angle α can be obtained, and then realize the monitoring to ion implantation angle.
In sum, the method according to the invention, it is provided that monitoring wafer is supervised by non-electrical method
Measured ion implant angle, the method is simple, easily operates, and analytical cycle is short, and measurement data is accurate.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a method for monitoring ion implantation angle, including:
Thering is provided monitoring wafer, described monitoring wafer includes Semiconductor substrate and is formed at described half
The groove of conductor substrate face and cover described channel bottom and sidewall and described quasiconductor
The polysilicon layer of substrate surface, wherein, described polysilicon layer is not doped；
Described polysilicon layer carries out angle-tilt ion in one direction inject, wherein, define institute
The acute angle stating angle-tilt ion injection direction and vertical direction is implant angle α；
Remove undoped polysilicon layer, and measurement is positioned at the removed of described channel bottom and does not mixes
The width w of miscellaneous polysilicon layer, and the residue doped polysilicon layer being positioned on described trenched side-wall
Height h；
Calculating described implant angle α with formula, wherein said formula is:
Method the most according to claim 1, it is characterised in that use the ammonia of dilution
Solution etches removes described undoped polysilicon layer.
Method the most according to claim 1, it is characterised in that the deep width of described groove
Ratio is more than or equal to 1.
Method the most according to claim 1, it is characterised in that the value of described w is less than
Width equal to groove.
Method the most according to claim 1, it is characterised in that the value of described h is less than
The degree of depth equal to groove.
Method the most according to claim 1, it is characterised in that described monitoring wafer
Making step includes:
Semiconductor substrate is provided, the surface of described Semiconductor substrate is formed hard mask layer；
It is sequentially etched described hard mask layer and described Semiconductor substrate, to form groove；
Remove remaining described hard mask layer；
The surface of the bottom of described groove and sidewall and described Semiconductor substrate is formed many
Crystal silicon layer, described polysilicon layer is not doped.
Method the most according to claim 6, it is characterised in that described hard mask layer bag
Include the lamination of oxide skin(coating) from bottom to top and nitride layer.
Method the most according to claim 7, it is characterised in that use thermal oxidation method shape
Become described oxide skin(coating).
Method the most according to claim 7, it is characterised in that described nitride layer is
Silicon nitride layer.
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| CN201510023599.5A CN105845591B (en) | 2015-01-16 | 2015-01-16 | A kind of method of monitoring ion implantation angle |
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| CN201510023599.5A CN105845591B (en) | 2015-01-16 | 2015-01-16 | A kind of method of monitoring ion implantation angle |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115372802A (en) * | 2022-10-24 | 2022-11-22 | 江西兆驰半导体有限公司 | Photoelectric detection method and system for wafer |
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| JPH1123497A (en) * | 1997-07-01 | 1999-01-29 | Nec Corp | Preparation of sample for secondary ion mass spectrometry |
| US20070145298A1 (en) * | 2005-12-12 | 2007-06-28 | Axcelis Technologies, Inc. | Ion beam angle measurement systems and methods for ion implantation systems |
| US20100203732A1 (en) * | 2009-02-10 | 2010-08-12 | International Business Machines Corporation | Fin and finfet formation by angled ion implantation |
| CN102800604A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for obtaining parameters of ion implantation technology, monitoring wafer and manufacturing method thereof |
| CN104091767A (en) * | 2014-06-25 | 2014-10-08 | 京东方科技集团股份有限公司 | Ion implantation monitoring method |
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2015
- 2015-01-16 CN CN201510023599.5A patent/CN105845591B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1123497A (en) * | 1997-07-01 | 1999-01-29 | Nec Corp | Preparation of sample for secondary ion mass spectrometry |
| US20070145298A1 (en) * | 2005-12-12 | 2007-06-28 | Axcelis Technologies, Inc. | Ion beam angle measurement systems and methods for ion implantation systems |
| US20100203732A1 (en) * | 2009-02-10 | 2010-08-12 | International Business Machines Corporation | Fin and finfet formation by angled ion implantation |
| CN102800604A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Method for obtaining parameters of ion implantation technology, monitoring wafer and manufacturing method thereof |
| CN104091767A (en) * | 2014-06-25 | 2014-10-08 | 京东方科技集团股份有限公司 | Ion implantation monitoring method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115372802A (en) * | 2022-10-24 | 2022-11-22 | 江西兆驰半导体有限公司 | Photoelectric detection method and system for wafer |
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