CN110364475A - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
- Publication number
- CN110364475A CN110364475A CN201810312387.2A CN201810312387A CN110364475A CN 110364475 A CN110364475 A CN 110364475A CN 201810312387 A CN201810312387 A CN 201810312387A CN 110364475 A CN110364475 A CN 110364475A
- Authority
- CN
- China
- Prior art keywords
- manufacturing
- semiconductor devices
- density plasma
- semiconductor substrate
- devices according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, which comprises provides semiconductor substrate；Groove is formed in the semiconductor substrate；Isolated material is filled in the trench using high density plasma CVD technique, to form fleet plough groove isolation structure, wherein, the high density plasma CVD technique successively includes heating period and depositional phase, does not include oxygen in process gas used in the heating period.The manufacturing method of semiconductor devices provided by the invention, oxygen is not included in process gas used in the high density plasma CVD technique heating period wherein, avoid the semiconductor substrate of oxygen and trenched side-wall that oxidation reaction occurs and induces lattice defect, so as to avoid the generation of element leakage phenomenon.
Description
Technical field
The present invention relates to semiconductor design and manufacturing process, in particular to a kind of manufacturing method of semiconductor devices.
Background technique
With being pushed further into for Moore's Law, the integrated level of integrated circuit is higher and higher, and the downsizing of component makes
Isolation structure between component also must scaled down, this also means that the difficulty of isolation is higher and higher.Due to tradition
Field oxidation method isolation have the reasons such as beak effect, in 90 nanometers and following technique, shallow trench isolation (Shallow Trench
Isolation, STI) it has been widely used.
With the continuous development of integrated circuit technique, the depth-to-width ratio (Aspect Ratio) of shallow trench isolation is increasing,
The trench depth of 40 nanometers or less shallow trench isolations is generally in 2000 Ethylmercurichlorendimides or so, but width is only 400 to 800 Ethylmercurichlorendimides, deep
Width is than being only 4:1, even up to 8:1, and under such high-aspect-ratio, common depositing operation far can not have been completed intact
Sunken filling.Fill process used at present is usually high-density plasma (HDP) chemical vapor deposition process.High density
Plasma activated chemical vapour deposition technique has excellent trench fill, and can fill deep width at relatively low temperature
Than big gap, and it is preferable using the film quality of high density plasma CVD process deposits, impurity content is low,
Advantageously ensure that the working range and stability of device.However, using high density plasma CVD technique institute shape
At the side wall of fleet plough groove isolation structure be easy to appear lattice defect, leak electricity so as to cause device.
Accordingly, it is desirable to provide a kind of manufacturing method of new semiconductor devices, to solve the above problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention in order to overcome the problems, such as presently, there are at least one, provide a kind of manufacturing method of semiconductor devices,
Include:
Semiconductor substrate is provided；
Groove is formed in the semiconductor substrate；
Isolated material is filled in the trench using high density plasma CVD technique, to form shallow ridges
Recess isolating structure, wherein the high density plasma CVD technique successively includes heating period and depositional phase,
Oxygen is not included in process gas used in the heating period.
Illustratively, process gas used in the heating period is inert gas.
Illustratively, the inert gas is argon gas.
Illustratively, isolated material is being filled in the trench using high density plasma CVD technique
The step of before, further includes: form the laying for covering the channel bottom and side wall.
Illustratively, the laying is oxide skin(coating).
Illustratively, isolated material is being filled in the trench using high density plasma CVD technique
The step of before, further includes: execute annealing process, to eliminate generated stress in the laying growth course.
Illustratively, patterned hard mask layer is formed in the semiconductor substrate.
Illustratively, in the trench fill isolated material the step of include:
Using high density plasma CVD technique, is formed and cover the hard mask layer and fill the full ditch
The isolated material of slot；
Chemical mechanical milling tech is executed, the part that the isolated material is located above the hard mask layer is removed.
It illustratively, further include that removal is described patterned after the step of executing the chemical mechanical milling tech
The step of hard mask layer.
Illustratively, after the step of removing the patterned hard mask layer, further includes:
Form the protective layer for covering the semiconductor substrate；
Trap ion implanting is carried out to the semiconductor substrate；And
Remove the protective layer.
The manufacturing method of semiconductor devices provided by the invention, wherein high density plasma CVD technique adds
Do not include oxygen in process gas used in the hot stage, avoids the semiconductor substrate of oxygen and trenched side-wall that oxidation reaction occurs
And lattice defect is induced, so as to avoid the generation of element leakage phenomenon.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 is the schematic flow chart according to the manufacturing method of the semiconductor devices of one embodiment of the invention；
Fig. 2A-Fig. 2 F is each step device obtained in the manufacturing method according to the semiconductor devices of one embodiment of the invention
The schematic cross sectional view of part.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
The standard technology of current large scale integrated circuit specifically includes that offer semiconductor substrate first, in semiconductor substrate
Then one layer of pad oxide of upper formation grows one layer of hard mask layer as buffer layer on the pad oxide, then pass through photoetching
The groove for accommodating fleet plough groove isolation structure is formed with etching；Liner is formed in channel bottom and side wall using thermal oxidation method
Layer；Isolated material is filled in the trench；Remove the pad oxide and hard mask layer；It is served as a contrast using sacrificial oxidation process in semiconductor
Layer of oxide layer is grown on bottom, the protective layer as subsequent trap ion implanting；Eventually form grid, source-drain area and interconnection layer
Deng.
Wherein, filling fill process used in groove is usually high-density plasma (HDP) chemical vapor deposition work
Skill.High density plasma CVD technique has excellent trench fill, and can be in relatively low temperature
The big gap of lower filling depth-to-width ratio, and it is preferable using the film quality of high density plasma CVD process deposits,
Impurity content is low, advantageously ensures that the working range and stability of device.However, heavy using high-density plasma chemical gas phase
The side wall that product technique is formed by fleet plough groove isolation structure is easy to appear lattice defect, leaks electricity so as to cause device.Application
People it has been investigated that, the reason of generating above-mentioned leaky, is as follows: high density plasma CVD technique generally according to
Secondary includes heating period and depositional phase, in the heating period of high density plasma CVD technique, process gas
In oxygen can and STI inside semiconductor substrate oxidation reaction occurs, can be inside semiconductor with the stress of oxidation reaction
Lattice defect is induced, and plasma can further stimulate lattice defect to spread, in addition, anti-during being subsequently formed protective layer
Answer the oxygen in gas that can react by the semiconductor material of loose STI side wall and lattice defect position, stress can be into
The expansion of one step causes lattice defect to wider extension, and this crystal defect is eventually exhibited as the serious electric leakage in electrical property.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of manufacturing method of semiconductor devices, comprising: offer is partly led
Body substrate；Groove is formed in the semiconductor substrate；Using high density plasma CVD technique in the ditch
Isolated material is filled in slot, to form fleet plough groove isolation structure, wherein the high density plasma CVD technique
Successively include heating period and depositional phase, does not include oxygen in process gas used in the heating period.
Process gas used in the heating period is inert gas.The inert gas is argon gas.
The step of filling isolated material in the trench using high density plasma CVD technique it
Before, further includes: form the laying for covering the channel bottom and side wall.The laying is oxide skin(coating).Using highly dense
Before the step of degree plasma activated chemical vapour deposition technique fills isolated material in the trench, further includes: execute annealing
Technique, to eliminate generated stress in the laying growth course.
Patterned hard mask layer is formed in the semiconductor substrate.Illustratively, filling isolation in the trench
The step of material includes: to be formed using high density plasma CVD technique and covered the hard mask layer and filled
The isolated material of the full groove；Chemical mechanical milling tech is executed, the isolated material is removed and is located on the hard mask layer
The part of side.
It further include the removal patterned hard mask layer after the step of executing the chemical mechanical milling tech
Step.After the step of removing the patterned hard mask layer, further includes: form the protection for covering the semiconductor substrate
Layer；Trap ion implanting is carried out to the semiconductor substrate；And the removal protective layer.
The manufacturing method of semiconductor devices provided by the invention, wherein high density plasma CVD technique adds
Process gas used in the hot stage do not include oxygen, avoid the semiconductor substrate of oxygen and trenched side-wall occur oxidation reaction and
Lattice defect is induced, so as to avoid the generation of element leakage phenomenon.
[exemplary embodiment]
It is carried out below with reference to manufacturing method of Fig. 1 and Fig. 2A-Fig. 2 F to the semiconductor devices of one embodiment of the invention detailed
Explanation.
Firstly, executing step 101 provides semiconductor substrate 200 as shown in Figure 2 A.The semiconductor substrate 200 can be
At least one of material being previously mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V
Compound semiconductor further includes multilayered structure that these semiconductors are constituted etc. or is silicon-on-insulator (SOI), insulator upper layer
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator are laminated on folded silicon (SSOI), insulator
(GeOI) etc..As an example, in the present embodiment, the constituent material of semiconductor substrate 200 selects monocrystalline silicon.
It is sequentially formed with buffer layer 201 and hard mask layer 202 from the bottom to top in the semiconductor substrate 200.The buffering
The material of layer 201 includes silica, and buffer layer 201 is that the hard mask layer 202 being subsequently formed provides buffering.Specifically, covering firmly
Film layer 202 directly forms to meeting on substrate and cause dislocation in substrate surface since stress is larger, and is formed in semiconductor substrate
Buffer layer 201 between 200 and hard exposure mask 202 can be to avoid the generation of dislocation.In addition, buffer layer 201 can also be gone subsequent
Semiconductor substrate 200 is protected during except hard mask layer 202.Illustratively, buffer layer 201 can be obtained by high-temperature oxidation
It arrives, thickness can be 100-200 angstroms, such as 110 angstroms.
Hard mask layer 202 can be used as the mask layer during etch semiconductor substrates 200, and as subsequent chemistry machine
Polish stop layer in tool grinding technics.Hard mask layer 202 can be heavy by chemical vapor deposition (CVD) method, physical vapor
The product formation such as (PVD) method or atomic layer deposition (ALD) method.As an example, hard mask layer 202 can be through ammonia and dichloro
Silane 750 DEG C or so at a temperature of, using low-pressure chemical vapor deposition formed silicon nitride layer, thickness is about 1200 angstroms.
Then, it executes step 102 and forms groove in the semiconductor substrate 200 as shown in Figure 2 B.Specifically, it uses
Lithography and etching technique forms the groove for accommodating fleet plough groove isolation structure, the etching in the semiconductor substrate 200
KOH, TMAH etc. can also be selected each with anisotropic dry etchings such as using plasma etching, reactive ion etchings
The wet etching method of anisotropy.The depth of groove can be true according to the actual needs size of required fleet plough groove isolation structure
It is fixed.Illustratively, the photoresist layer for defining channel patterns can be formed on hard mask layer 202, using the photoresist layer as exposure mask
Dry etching is carried out, to transfer a pattern to hard mask layer 202, and is to cover with photoresist layer and patterned hard mask layer 202
Film performs etching buffer layer 201 and semiconductor substrate 200, to form groove.After forming groove, using cineration technics or change
It learns reagent removal technique and removes photoetching offset plate figure.
Then, as shown in Figure 2 C, the laying 203 for covering the channel bottom and side wall is formed.Laying 203 is for keeping away
When exempting from directly to fill isolated material in the trench, the semiconductor substrate 200 that isolated material and trenched side-wall are exposed is adhered to
Property it is poor, be easy to appear cavity and the semiconductor material of spacer medium layer and trenched side-wall mismatches to form showing for larger stress
As, while the damage caused by trenched side-wall during etching is to form groove can be repaired.The formation of the laying
Method can be thermal oxidation method, such as dry-oxygen oxidation, steam oxidation, wet-oxygen oxidation etc. or other suitable methods.It is exemplary
Ground, the laying 203 are to form one layer of thin silicon oxide layer using ISSG (situ steam oxidation reaction) technique, and thickness is for example
It is 200-1000 angstroms.
Then, annealing process is executed, to eliminate generated stress in 203 growth course of laying.The annealing
The temperature and time of processing can be set according to actual needs, and in the present embodiment, the temperature of the annealing is 800 DEG C
~1350 DEG C, the time of the annealing is 5s~60s.
Then, execute step 103, using high density plasma CVD technique fill in the trench every
From material, to form fleet plough groove isolation structure, wherein the high density plasma CVD technique successively includes adding
Hot stage and depositional phase, process gas used in the heating period do not include oxygen.
It the use of high density plasma CVD process filling groove successively include two stages, i.e. heating period
And the depositional phase.Wherein, the heating period be by wafer from room temperature be heated to technological temperature, formal technique before temperature-rise period.
In the present invention, process gas used in the heating period does not include oxygen, due to not wrapping in the process gas of heating period
It is oxygenous, showing for lattice defect is induced due to oxidation reaction occurs for the semiconductor substrate without oxygen and trenched side-wall
As subsequent depositional phase and the process for forming protective layer further will not stimulate lattice defect to spread, to avoid device
Electric leakage failure.In the present embodiment, the process gas is inert gas, such as argon gas.
It after the heating period, carries out the depositional phase, the deposition, which is formed, to be covered the hard mask layer 203 and fill
The isolated material 204 of the full groove, as shown in Figure 2 D.The isolated material 204 can be silica, fluorine silica glass, not
One of the silicate glass (USG) of doping or tetraethyl orthosilicate are a variety of.As an example, the high-density plasma
The gas source of chemical vapor deposition can be SiH4And O2, wherein SiH4Flow can be 51sccm~61sccm, O2Flow can
Think 122sccm~142sccm, O2And SiH4Flow-rate ratio can be 1.8:1~2.7:1, time of deposition can for 40s~
80s, the pressure of deposition can be 2mTorr~10mTorr.Above-mentioned process conditions are not limiting, and those skilled in the art can
To select suitable process conditions according to the actual situation.
Then, as shown in Figure 2 E, the isolated material 204 for removing 202 top of hard mask layer, until exposing hard exposure mask
Layer 202.The technique for removing the isolated material 204 of 202 top of hard mask layer is CMP process, with hard mask layer 202
Terminal as CMP process.
Then, as shown in Figure 2 F, hard mask layer 202 and buffer layer 201 are removed.It can be used described in wet-etching technology removal
Hard mask layer 202 and buffer layer 201.As an example, then using diluted hydrofluoric acid using phosphoric acid removal hard mask layer 202 first
Buffer layer 201 is removed, thus the semiconductor substrate 200 of exposure below.
Then, the protective layer for covering the semiconductor substrate 200 is formed.It is described protective layer used to be injected in as subsequent ion
To form the protective layer of well region.In one embodiment, the formation process of the protective layer is well known to those skilled in the art
All kinds of thermal oxidation technologies, the thermal oxidation technology is, for example, boiler tube thermal oxidation method or steam method of formation in situ (ISSG).
Then, subsequent technique is completed with conventional steps.For example, executing trap ion implanting to form well region, and removal is protected
Sheath；The gate structure including gate dielectric and gate electrode layer is formed on the active area；Source and drain ion implanting is executed in grid
Pole structure two sides form source-drain area；Last part technology is executed to form interconnection layer etc..
So far, the processing step that method according to an exemplary embodiment of the present invention is implemented is completed.It is understood that this
Embodiment method, semi-conductor device manufacturing method not only includes above-mentioned steps, before above-mentioned steps, among or may also include it later
The step of he needs is included in the range of this implementation manufacturing method.
The manufacturing method of semiconductor devices provided by the invention, wherein high density plasma CVD technique adds
Process gas used in the hot stage do not include oxygen, avoid the semiconductor substrate of oxygen and trenched side-wall occur oxidation reaction and
Lattice defect is induced, so as to avoid the generation of element leakage phenomenon.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the manufacturing method includes:
Semiconductor substrate is provided；
Groove is formed in the semiconductor substrate；
Fill isolated material in the trench using high density plasma CVD technique, with formed shallow trench every
From structure, wherein the high density plasma CVD technique successively includes heating period and depositional phase, described
Oxygen is not included in process gas used in heating period.
2. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that used in the heating period
Process gas is inert gas.
3. the manufacturing method of semiconductor devices according to claim 2, which is characterized in that the inert gas is argon gas.
4. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that using high-density plasma
Chemical vapor deposition process was filled in the trench before the step of isolated material, further includes: is formed and is covered the trench bottom
The laying in portion and side wall.
5. the manufacturing method of semiconductor devices according to claim 4, which is characterized in that the laying is oxide
Layer.
6. the manufacturing method of semiconductor devices according to claim 4, which is characterized in that using high-density plasma
Chemical vapor deposition process was filled in the trench before the step of isolated material, further includes: annealing process is executed, to eliminate
Generated stress in the laying growth course.
7. the manufacturing method of semiconductor devices according to claim 1, which is characterized in that formed in the semiconductor substrate
There is patterned hard mask layer.
8. the manufacturing method of semiconductor devices according to claim 7, which is characterized in that filling isolation in the trench
The step of material includes:
Using high density plasma CVD technique, is formed and cover the hard mask layer and fill the full groove
Isolated material；
Chemical mechanical milling tech is executed, the part that the isolated material is located above the hard mask layer is removed.
9. the manufacturing method of semiconductor devices according to claim 8, which is characterized in that ground executing the chemical machinery
After the step of grinding process, further include the steps that the removal patterned hard mask layer.
10. the manufacturing method of semiconductor devices according to claim 9, which is characterized in that described patterned removing
After the step of hard mask layer, further includes:
Form the protective layer for covering the semiconductor substrate；
Trap ion implanting is carried out to the semiconductor substrate；And
Remove the protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810312387.2A CN110364475A (en) | 2018-04-09 | 2018-04-09 | A kind of manufacturing method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810312387.2A CN110364475A (en) | 2018-04-09 | 2018-04-09 | A kind of manufacturing method of semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110364475A true CN110364475A (en) | 2019-10-22 |
Family
ID=68212019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810312387.2A Pending CN110364475A (en) | 2018-04-09 | 2018-04-09 | A kind of manufacturing method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110364475A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314006A (en) * | 2023-05-26 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350662B1 (en) * | 1999-07-19 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method to reduce defects in shallow trench isolations by post liner anneal |
| US20050142797A1 (en) * | 2003-12-24 | 2005-06-30 | Ahn Heui G. | Isolation methods in semiconductor devices |
| CN1649122A (en) * | 2004-01-29 | 2005-08-03 | 台湾积体电路制造股份有限公司 | Method for forming shallow trench isolation (STI) and its structure |
| CN101075574A (en) * | 2007-06-12 | 2007-11-21 | 上海宏力半导体制造有限公司 | Method for producing shallow groove isolating structure of high-voltage assembly |
| CN101207063A (en) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation |
| CN101226895A (en) * | 2007-12-21 | 2008-07-23 | 上海宏力半导体制造有限公司 | Method for manufacturing shallow groove isolation structure |
| CN102122628A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure and manufacturing method thereof |
| CN103730404A (en) * | 2013-12-31 | 2014-04-16 | 上海集成电路研发中心有限公司 | Method for manufacturing shallow groove isolation |
| CN104835775A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure preparation method |
-
2018
- 2018-04-09 CN CN201810312387.2A patent/CN110364475A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6350662B1 (en) * | 1999-07-19 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method to reduce defects in shallow trench isolations by post liner anneal |
| US20050142797A1 (en) * | 2003-12-24 | 2005-06-30 | Ahn Heui G. | Isolation methods in semiconductor devices |
| CN1649122A (en) * | 2004-01-29 | 2005-08-03 | 台湾积体电路制造股份有限公司 | Method for forming shallow trench isolation (STI) and its structure |
| CN1324673C (en) * | 2004-01-29 | 2007-07-04 | 台湾积体电路制造股份有限公司 | Method for forming shallow trench isolation (STI) and its structure |
| CN101207063A (en) * | 2006-12-18 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation |
| CN101075574A (en) * | 2007-06-12 | 2007-11-21 | 上海宏力半导体制造有限公司 | Method for producing shallow groove isolating structure of high-voltage assembly |
| CN101226895A (en) * | 2007-12-21 | 2008-07-23 | 上海宏力半导体制造有限公司 | Method for manufacturing shallow groove isolation structure |
| CN102122628A (en) * | 2010-01-08 | 2011-07-13 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure and manufacturing method thereof |
| CN103730404A (en) * | 2013-12-31 | 2014-04-16 | 上海集成电路研发中心有限公司 | Method for manufacturing shallow groove isolation |
| CN104835775A (en) * | 2014-02-08 | 2015-08-12 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure preparation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314006A (en) * | 2023-05-26 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
| CN116314006B (en) * | 2023-05-26 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100334708C (en) | Semiconductor device mfg. method | |
| US7544548B2 (en) | Trench liner for DSO integration | |
| JP4345875B2 (en) | Contact plug forming method of semiconductor element | |
| CN101950730B (en) | STI structure and method of forming bottom void in same | |
| CN107958871B (en) | Semiconductor device and method for manufacturing the same | |
| CN105655284B (en) | The forming method of groove isolation construction | |
| CN106887408A (en) | A kind of manufacture method of semiconductor devices | |
| CN102214657A (en) | Semiconductor device, isolation structure of semiconductor device and method for manufacturing isolation structure of semiconductor device | |
| CN104835774A (en) | Semiconductor device preparation method | |
| CN101770974A (en) | Method for fabricating shallow-trench isolation structure | |
| CN104576501B (en) | A kind of semiconductor devices and its manufacture method | |
| CN103928386B (en) | A kind of manufacture method of fleet plough groove isolation structure | |
| US8877600B2 (en) | Method for manufacturing a hybrid SOI/bulk semiconductor wafer | |
| CN110364475A (en) | A kind of manufacturing method of semiconductor devices | |
| US6436791B1 (en) | Method of manufacturing a very deep STI (shallow trench isolation) | |
| CN102376621A (en) | Manufacturing method of shallow trench isolation structure | |
| CN107464741A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN110364476A (en) | A kind of manufacturing method of semiconductor devices | |
| CN102956535A (en) | Semiconductor device and manufacturing method thereof | |
| CN107958933B (en) | Semiconductor device and method for manufacturing the same | |
| US8269307B2 (en) | Shallow trench isolation structure and method for forming the same | |
| CN101930940B (en) | Semiconductor shallow trench isolation method | |
| CN110120364A (en) | The preparation method of fleet plough groove isolation structure | |
| CN104637881A (en) | Method for forming shallow trench isolation structure | |
| CN104517884B (en) | A kind of method for making semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20191022 |