CN105830045A - 仅用接收机时钟来进行的CCIe接收机逻辑寄存器写入 - Google Patents

仅用接收机时钟来进行的CCIe接收机逻辑寄存器写入 Download PDF

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Publication number
CN105830045A
CN105830045A CN201480068720.XA CN201480068720A CN105830045A CN 105830045 A CN105830045 A CN 105830045A CN 201480068720 A CN201480068720 A CN 201480068720A CN 105830045 A CN105830045 A CN 105830045A
Authority
CN
China
Prior art keywords
data bits
symbols
receiver device
clock
transition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480068720.XA
Other languages
English (en)
Chinese (zh)
Inventor
S·森戈库
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105830045A publication Critical patent/CN105830045A/zh
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
CN201480068720.XA 2013-12-18 2014-12-17 仅用接收机时钟来进行的CCIe接收机逻辑寄存器写入 Pending CN105830045A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361917895P 2013-12-18 2013-12-18
US61/917,895 2013-12-18
US14/572,680 2014-12-16
US14/572,680 US10031547B2 (en) 2013-12-18 2014-12-16 CCIe receiver logic register write only with receiver clock
PCT/US2014/070935 WO2015095382A1 (en) 2013-12-18 2014-12-17 CCIe RECEIVER LOGIC REGISTER WRITE ONLY WITH RECEIVER CLOCK

Publications (1)

Publication Number Publication Date
CN105830045A true CN105830045A (zh) 2016-08-03

Family

ID=53368356

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480068720.XA Pending CN105830045A (zh) 2013-12-18 2014-12-17 仅用接收机时钟来进行的CCIe接收机逻辑寄存器写入

Country Status (7)

Country Link
US (1) US10031547B2 (enExample)
EP (1) EP3084619A1 (enExample)
JP (1) JP2017501493A (enExample)
KR (1) KR20160100363A (enExample)
CN (1) CN105830045A (enExample)
BR (1) BR112016014347A2 (enExample)
WO (1) WO2015095382A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111934707B (zh) 2019-04-25 2024-07-09 恩智浦有限公司 数据发射代码和接口
US12278636B2 (en) * 2022-11-28 2025-04-15 Parade Technologies, Ltd. Receiver circuit with automatic DC offset cancellation in display port applications
US12306693B2 (en) * 2023-05-12 2025-05-20 Mediatek Inc. Method and device for saving power

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2440768A1 (de) * 1974-08-26 1976-03-11 Philips Patentverwaltung Verfahren und vorrichtung zur datenkompression fuer die faksimile-uebertragung graphischer information
GB2120054A (en) * 1982-04-23 1983-11-23 Gen Electric Co Plc Digital data signalling systems
US5640605A (en) * 1994-08-26 1997-06-17 3Com Corporation Method and apparatus for synchronized transmission of data between a network adaptor and multiple transmission channels using a shared clocking frequency and multilevel data encoding
CN1902613A (zh) * 2003-12-31 2007-01-24 英特尔公司 为串行点到点链路通过非数据符号处理进行通道到通道的偏斜校正
US20090092212A1 (en) * 2007-10-08 2009-04-09 Tli Inc. Clock embedded differential data receiving system for ternary lines differential signaling

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5850422A (en) 1995-07-21 1998-12-15 Symbios, Inc. Apparatus and method for recovering a clock signal which is embedded in an incoming data stream
JP2002351825A (ja) * 2001-05-29 2002-12-06 Rohm Co Ltd 通信システム
US7007120B2 (en) 2003-04-25 2006-02-28 Hewlett-Packard Development Company, L.P. Information transfer protocol having sync fields of different lengths
US7289528B2 (en) 2003-08-29 2007-10-30 Motorola, Inc. Component interconnect with self-clocking data
US7444558B2 (en) 2003-12-31 2008-10-28 Intel Corporation Programmable measurement mode for a serial point to point link
US7386661B2 (en) 2004-10-13 2008-06-10 Marvell International Ltd. Power save module for storage controllers
US7916820B2 (en) * 2006-12-11 2011-03-29 International Business Machines Corporation Systems and arrangements for clock and data recovery in communications
JP2010250048A (ja) * 2009-04-15 2010-11-04 Panasonic Corp 送信装置、受信装置、データ伝送システム、及び画像表示装置
US9118457B2 (en) * 2013-03-15 2015-08-25 Qualcomm Incorporated Multi-wire single-ended push-pull link with data symbol transition based clocking
US20150100711A1 (en) * 2013-10-07 2015-04-09 Qualcomm Incorporated Low power camera control interface bus and devices
US9426082B2 (en) * 2014-01-03 2016-08-23 Qualcomm Incorporated Low-voltage differential signaling or 2-wire differential link with symbol transition clocking
US20150220472A1 (en) * 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2440768A1 (de) * 1974-08-26 1976-03-11 Philips Patentverwaltung Verfahren und vorrichtung zur datenkompression fuer die faksimile-uebertragung graphischer information
GB2120054A (en) * 1982-04-23 1983-11-23 Gen Electric Co Plc Digital data signalling systems
US5640605A (en) * 1994-08-26 1997-06-17 3Com Corporation Method and apparatus for synchronized transmission of data between a network adaptor and multiple transmission channels using a shared clocking frequency and multilevel data encoding
CN1902613A (zh) * 2003-12-31 2007-01-24 英特尔公司 为串行点到点链路通过非数据符号处理进行通道到通道的偏斜校正
US20090092212A1 (en) * 2007-10-08 2009-04-09 Tli Inc. Clock embedded differential data receiving system for ternary lines differential signaling

Also Published As

Publication number Publication date
JP2017501493A (ja) 2017-01-12
US10031547B2 (en) 2018-07-24
KR20160100363A (ko) 2016-08-23
BR112016014347A2 (pt) 2017-08-08
EP3084619A1 (en) 2016-10-26
US20150168991A1 (en) 2015-06-18
WO2015095382A1 (en) 2015-06-25

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