CN105810669A - Vertical metal insulator and metal capacitor - Google Patents

Vertical metal insulator and metal capacitor Download PDF

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Publication number
CN105810669A
CN105810669A CN201610037440.3A CN201610037440A CN105810669A CN 105810669 A CN105810669 A CN 105810669A CN 201610037440 A CN201610037440 A CN 201610037440A CN 105810669 A CN105810669 A CN 105810669A
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China
Prior art keywords
vertical conductive
conductive structure
layer
pipe core
moulding
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Granted
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CN201610037440.3A
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Chinese (zh)
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CN105810669B (en
Inventor
廖文翔
周淳朴
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/600,777 external-priority patent/US9343237B2/en
Priority claimed from US14/996,070 external-priority patent/US9941195B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105810669A publication Critical patent/CN105810669A/en
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Publication of CN105810669B publication Critical patent/CN105810669B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor device and a formation method for the same. The semiconductor comprises a member pipe core, a modeling layer surrounding the member pipe core, a plurality of vertical conductive structures formed in the modeling layer, a plurality of first vertical conductive structures formed in the modeling layer, and interconnection structures of a plurality of second vertical conductive structures; the first vertical conductive structures and the second vertical conductive structures are arranged in a staggering manner; and the insulation structure is formed between the first vertical conductive structures and the second vertical conductive structures. The invention also discloses a metal capacitor perpendicular to the metal insulator.

Description

Vertical metal insulator metal capacitor
The cross reference of related application
The application is the 14/600 in submission on January 20th, 2015, the continuation application of No. 777 U. S. applications, this is 14/600 years old, No. 777 U. S. applications are the 14/337 in submission on July 22nd, 2014, the continuation application of No. 530 U. S. applications and require on June 29th, 2010 submit to the 12/825th, the priority of No. 605 U. S. applications, this is 12/825 years old, No. 605 U.S. Application claims on October 10th, 2009 submit to the 61/259th, the priority of No. 787 U.S. Provisional Applications, their full content is hereby expressly incorporated by reference.
Technical field
This invention relates generally to technical field of semiconductors, more particularly, to semiconductor device and forming method thereof.
Background technology
Capacitor is widely used in integrated circuit.The electric capacity of capacitor is directly proportional to the dielectric constant (k) of capacitor area and insulating barrier, and the thickness of the electric capacity of capacitor and insulating barrier is inversely proportional to.Therefore, in order to increase electric capacity, it is preferable that area increased and k value and reduce the thickness of insulating barrier.
It is associated with area increased and has a problem in that, it is necessary to bigger chip area.Traditional metal-insulator-metal type (MIM) capacitor in integrated circuit has the pectinate texture of various level.Horizontal structure electric capacity is relevant with the thickness of metal interlevel.But, the thickness of metal interlevel is difficult to control.This causes the very big change for the MIM capacitor in the product of desired value.Accordingly, it would be desirable to for the new method and structure of MIM capacitor.
Summary of the invention
In order to solve defect existing in prior art, according to an aspect of the present invention, it is provided that a kind of semiconductor device, including: component pipe core；Moulding layer, around described component pipe core；Multiple first vertical conductive structure, are formed in described moulding layer；And multiple second vertical conductive structure, formed in described moulding layer；Wherein, described first vertical conductive structure and described second vertical conductive structure are interlaced, and insulation system is formed between described first vertical conductive structure and described second vertical conductive structure.
According to a further aspect in the invention, it is provided that a kind of method, including: on substrate, form the first conductive plane；Described first conductive plane is formed multiple first vertical conductive structure and the plurality of first vertical conductive structure is electrically coupled to described first conductive plane；Forming multiple second vertical conductive structure over the substrate, wherein, described first vertical conductive structure and described second vertical conductive structure are interlaced, and insulation system is formed between described first vertical conductive structure and described second vertical conductive structure；Component pipe core is attached over the substrate；Being arranged in the moulding layer application moulding compound above described substrate with around described component pipe core；And on described moulding layer, form the second conductive plane, wherein, described second conductive plane is electrically coupled to described second vertical conductive structure.
According to another aspect of the invention, provide a method that, including: on package structure, form capacitor arrangement, wherein, described capacitor arrangement includes multiple first vertical conductive structure, multiple second vertical conductive structure and the insulation system between described first vertical conductive structure and described second vertical conductive structure；Component pipe core is attached on substrate；And being arranged in the moulding layer application moulding compound above described substrate with around described component pipe core and described capacitor arrangement.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, various aspects of the invention can be best understood from according to the following detailed description.It is emphasized that according to the standard practices in industry, various parts are not drawn to scale.It practice, in order to clearly discuss, the size of various parts can be arbitrarily increased or reduce.
Fig. 1 shows the schematic diagram of the semiconductor structure with vertical capacitor according to some embodiments of the present invention；
Fig. 2 shows the schematic diagram of integrated multi output (InFO) packaging part of the semiconductor structure included in Fig. 1 according to some embodiments of the present invention；
Fig. 3 shows the flow chart of the method for manufacturing the semiconductor structure in Fig. 2 according to some embodiments of the present invention；
Fig. 4 to Figure 19 is the sectional view according to the packaging part in Fig. 2 of the different phase being in manufacturing process of some embodiments of the present invention.
Figure 20 is the schematic diagram of integrated multi output (InFO) packaging part illustrating the semiconductor structure included in Fig. 1 according to some embodiments of the present invention；
Figure 21 shows the flow chart of the method for manufacturing the semiconductor structure in Figure 20 according to some embodiments of the present invention；
Figure 22 to Figure 26 is the sectional view according to the packaging part in Figure 20 of the different phase being in manufacturing process of some embodiments of the present invention；
Figure 27 shows the schematic diagram of integrated multi output (InFO) packaging part of the semiconductor structure included in Fig. 1 according to some embodiments of the present invention；And
Figure 28 shows the schematic diagram of integrated multi output (InFO) packaging part of the semiconductor structure included in Fig. 1 according to some embodiments of the present invention.
Detailed description of the invention
Disclosure below provides many different embodiments or examples, for realizing the different characteristic of provided theme.The particular instance of assembly explained below and layout is to simplify the present invention.Certainly, these are only examples and are not intended to limit the present invention.Such as, in the following description, above second component or on form first component and can include the embodiment that first component is formed as with second component directly contacting, it is also possible to include the embodiment that formation optional feature between first component and second component makes first component and second component be not directly contacted with.It addition, the present invention can in multiple examples repeat reference numerals and/or character.This repetition is for purposes of simplicity and clarity, and itself does not indicate the relation between each discussed embodiment and/or configuration.
The term used in this specification is generally of its its ordinary meaning in the art and in the specific environment using each term.The example used in this specification includes the example of any term discussed in this article, and this example is merely illustrative of and is definitely not the restriction present invention's or any exemplary term scope and meaning.Equally, the invention is not restricted to each embodiment provided in this specification.
Although term " first ", " second " etc. can being used to describe each element herein, but these elements should not being limited by these terms.These terms are for differentiating an element and another element.Such as, when without departing substantially from the scope of embodiment, it is possible to the first element is called the second element, and it is likewise possible to the second element is called the first element.As used herein, term "and/or" includes any one and all of combination of one or more listed associated item.
In addition, for the ease of describing, can use such as herein " in ... lower section ", " ... below ", " bottom ", " ... above ", the spatial relationship term such as " top " to be to describe the relation of an element as depicted or parts and another element or parts.Except the orientation shown in figure, spatial relationship term is intended to the different orientation including the device in use or operating process.Device can otherwise position (90-degree rotation or in other orientation), and spatial relation description symbol used herein can similarly correspondingly be explained.
In this article, term " coupling " can also be referred to as " electric coupling ", and term " connection " can be referred to as " electrical connection "." coupling " and " connection " can be used for indicating two or more element to cooperate or interact.
Fig. 1 is the schematic diagram illustrating the semiconductor structure 100 including vertical capacitor 100 according to some embodiments of the present invention.
As Fig. 1 is exemplarily illustrated, semiconductor structure 100 includes electrode 120 and 140.Electrode 120 includes conductive plane 122 and vertical conductive structure 124.Electrode 140 includes conductive plane 142 and vertical conductive structure 144.Vertical conductive structure 124 and vertical conductive structure 144 are interlaced, and dielectric material 160 is filled between electrode 120 and electrode 140.
Such as, conductive plane 122 and conductive plane 142 include conductive material, including copper, silver, gold etc..In certain embodiments, conductive plane 122 and conductive plane 142 include other suitable conductive materials than metal.
The schematic diagram of integrated multi output (InFO) packaging part 200 including the semiconductor structure 100 shown in Fig. 1 according to some embodiments of the present invention is showed with reference to Fig. 2, Fig. 2.About the embodiment of Fig. 1, for ease of understanding, the like in Fig. 2 is labeled with identical reference number.
In order to illustrate, packaging part 200 includes polymeric substrate layers 203, InFO dorsal part redistributing layer (RDL) 204, crystal seed layer 205, conductive material 206, conduction molding through hole (TMV) 207, component pipe core 208, moulding layer 209, conductive layer 210, polymeric layer 211,213 and 215, redistributing layer (RDL) 212 and 214, Underbump metallization (UBM) 216 and joint outer part 217.
As in figure 2 it is shown, in certain embodiments, the semiconductor structure 100 shown in Fig. 1 is formed in integrated multi output (InFO) packaging part 200.Owing to manufacturing semiconductor structure 100 with the miscellaneous part of packaging part 200 simultaneously, so manufacturing cost is relatively low.
In order to illustrate, semiconductor structure 100 includes: vertical conductive structure 124, is formed in moulding layer 209 and is electrically coupled to conductive plane 122；With vertical conductive structure 144, formation is in moulding layer 209 and is electrically coupled to conductive plane 142.Conductive plane 142 is arranged on above moulding layer 209.Vertical conductive structure 124 and 144 is formed by the conductive material 206 above crystal seed layer 205, and this conductive material is filled in molding through hole (TMV), and this molding through hole extends through moulding compound (MC).Conductive plane 122 is formed in InFO dorsal part RDL204.Conductive plane 142 is formed in RDL212, and by RDL214 by component pipe core 208 and conductive plane 142 electric coupling.
In certain embodiments, vertical conductive structure 124 and vertical conductive structure 144 have square shape, rectangular shape, round-shaped, elliptical shape, any other suitable shape or their combination in any in cross section.Vertical conductive structure 124 is evenly distributed on conductive plane 122, and vertical conductive structure 144 is evenly distributed on conductive plane 142 times.In certain embodiments, vertical conductive structure 124 is distributed as square grid pattern on conductive plane 122, and vertical conductive structure 144 is distributed as square grid pattern 142 times at conductive plane.
In certain embodiments, moulding compound MC is applied in moulding layer 209 with around the vertical conductive structure 124 on component pipe core 208 and polymeric substrate layers 203 and vertical conductive structure 144.Alternatively, in certain embodiments, the moulding compound MC in integrated multi output (InFO) packaging part 200 is filled between vertical conductive structure 124 and vertical conductive structure 144 using as dielectric material 160 as shown in Figure 1.In certain embodiments, moulding compound MC includes high k polymer or Silicon stone (silica).
In certain embodiments, the Overmolded layer 209 of polymeric layer 211.RDL212 overlying polymer layer 211.Polymeric layer 213 covers RDL212.RDL214 overlying polymer layer 213.Polymeric layer 215 covers RDL214.Underbump metallization (UBM) 216 is formed above RDL214.Joint outer part 217 is arranged on UBM216 and is configured to input/output (I/O) pad (such as, including soldered ball) to be electrically connected to component pipe core 208 by RDL214.In certain embodiments, joint outer part 217 is BGA (BGA) ball, controlled collapse chip connection (C4) projection etc..In certain embodiments, connector 217 is for being electrically connected to other package assemblings by packaging part 200, for instance another component pipe core, intermediary layer, package substrate, printed circuit board (PCB), mainboard etc..
Fig. 3 shows the flow chart that the formation according to some embodiments of the present invention includes the method 300 of integrated multi output (InFO) packaging part 200 shown in Fig. 2.In order to be more fully understood that the present invention, carry out discussion method 300 about the semiconductor structure 100 shown in Fig. 1 to Fig. 2, but the invention is not restricted to this.
In order to illustrate, come together to describe the manufacturing process of integrated multi output (InFO) packaging part 200 shown in Fig. 2 by method 300 with Fig. 4 to Figure 19.Fig. 4 to Figure 19 is the sectional view of integrated multi output (InFO) packaging part 200 of the different phase being in manufacturing process according to some embodiments of the present invention.After the different phase of Fig. 4 to Figure 19, packaging part 200 has the sectional view in Fig. 2.Although describing Fig. 4 to Figure 19 together with method 300, it should be appreciated that, structure disclosed in Fig. 4 to Figure 19 is not restricted to method 300.For ease of understanding, the similar element in Fig. 4 to Figure 19 is labeled with identical reference number.
Although herein disclosed method being shown and described as a series of step or event, but it is to be understood that these shown steps or the order of event should not be construed as limited significance.Such as, some steps can occur with different order and/or occur with other steps except illustrated herein and/or described step or event or event simultaneously.Further, it is not required that all steps illustrated are all for implementing one or more aspects described herein or embodiment.Additionally, can in the step of one or more separation and/or the stage performs one or more steps as herein described.
With reference to the method 300 in Fig. 3, in operation s 310, as shown in Figure 4, it is provided that carrier 201, adhesive layer 202 and polymeric substrate layers 203.
In certain embodiments, carrier 201 includes glass, pottery or other suitable materials to provide structure to support during the formation of all parts in device package.In certain embodiments, for instance, adhesive layer 202 is arranged on above carrier 201 and includes glue-line, photothermal deformation (LTHC) coating, ultraviolet (UV) film etc..By adhesive layer 202, polymeric substrate layers 203 is coated on carrier 201.In certain embodiments, after the encapsulation process, carrier 201 and adhesive layer 202 are removed from InFO packaging part.In certain embodiments, polymeric substrate layers 203 is made up of following material: polybenzoxazoles (PBO), aginomoto built up film (ABF, AjinomotoBuildupFilm), polyimides, benzocyclobutene (BCB), welding resistance (SR) film, tube core coherent film (DAF) etc., but the invention is not restricted to this.
With reference to the method 300 in Fig. 3, in operation S320, as it is shown in figure 5, subsequently form InFO dorsal part redistributing layer (RDL) 204.In certain embodiments, dorsal part RDL204 includes forming the conductive component in one or more polymeric layers, it may for example comprise wire and/or through hole.In certain embodiments, polymeric layer can use any suitable method of such as spin coating technique, sputtering etc. to be formed by any suitable material (including PI, PBO, BCB, epoxy resin, silicones, acrylate, nano-filled phenol resin, siloxanes, fluoropolymer, polynorbornene etc.).
In certain embodiments, conductive component is formed in polymeric layer.The formation of this conductive component includes: such as use the combination pattern fluidized polymer layer of photoetching and etch process；And in the polymeric layer of patterning, form conductive component, for instance, deposition crystal seed layer (that is, TiCu), then plated conductive metal level (that is, Cu) and use mask layer limit the shape of conductive component.In order to illustrate, design some conductive components to form the conductive plane 122 of semiconductor structure 100, and design some other conductive component to form functional circuit and the input/output component of the tube core for attachment subsequently.
It follows that in operation s 330, as shown in Figure 6, the photoresist 601 of patterning is formed above InFO dorsal part RDL204 and carrier 201.In certain embodiments, for instance, photoresist 601 is blanket layer at dorsal part RDL204 disposed thereon.It follows that use photomask (not shown) to carry out a part for exposure photo-etching glue 601.Then, according to using negativity or positive corrosion-resisting agent, remove the exposure of photoresist 601 or unexposed part.The photoresist 601 of obtained patterning includes the opening 602 being arranged on the neighboring area place of carrier 201.In certain embodiments, opening 602 also exposes the conductive component in dorsal part RDL204.
It follows that in operation S340, as it is shown in fig. 7, crystal seed layer 205 is deposited on above the photoresist 601 of patterning.
It follows that in operation S350, as shown in Figure 8, for instance, opening 602 is filled with conductive material 206, for instance include copper, titanium, nickel, tantalum, palladium, silver-colored in or golden etc. to form conductive through hole.In certain embodiments, during shikishima plating process, opening 602 is plated with conductive material 206, it may for example comprise electrochemistry plating, electroless plating etc..In certain embodiments, as it is shown in figure 9, filling opening 602 crossed by conductive material 206, and perform chemically mechanical polishing (CMP) technique and be positioned at the redundance above photoresist 601 with what remove conductive material 206.
It follows that in operation S360, as shown in Figure 10, remove photoresist 601.In certain embodiments, wet stripping technology is used for removing photoresist 601.In certain embodiments, wet stripping technology comprises dimethyl sulfoxide (DMSO) and tetramethyl ammonium hydroxide (TMAH) to remove Other substrate materials.
Therefore, vertical conductive structure 124 and vertical conductive structure 144 are respectively formed at above InFO dorsal part RDL204 and polymeric substrate layers 203.In order to illustrate, in certain embodiments, conduction molding through hole 207 is formed above dorsal part RDL204.In certain embodiments, conduction molding through hole 207 has square shape, rectangular shape, round-shaped, elliptical shape, any other suitable shape or their combination in any in cross section.Alternatively, in certain embodiments, conduction molding through hole 207 replaces with conductive pole or conductive lead wire, it may for example comprise copper, titanium, nickel, tantalum, palladium, silver, gold wire.In certain embodiments, conduction molding through hole 207 is spaced apart from each other, and spaced apart with vertical conductive structure 124 and vertical conductive structure 144 by opening 1001.In order to illustrate, at least one opening 1001 between conduction molding through hole 207 and semiconductor structure 100 is large enough to arrange one or more semiconductor element wherein.
It follows that in operation S370, as shown in figure 11, packaging part 200 is installed and be attached to one or more component pipe cores 208.In order to illustrate, as it can be seen, device package 200 includes carrier 201 and has the dorsal part RDL204 of conductive component.In certain embodiments, for instance, also include other interconnection structures, for instance, these other interconnection structures include the conduction molding through hole 207 of the conductive component being electrically coupled in dorsal part RDL204.In certain embodiments, it is possible to use component pipe core 208 is affixed to dorsal part RDL204 by adhesive layer.
It follows that in operation S380, as shown in figure 12, after component pipe core 208 being mounted to dorsal part RDL204 in opening 1001, moulding compound MC is formed in the moulding layer 209 in packaging part 200.Distribution moulding compound MC is to fill the gap between gap and vertical conductive structure 124 and the vertical conductive structure 144 between component pipe core 208 and conduction molding through hole 207.In certain embodiments, moulding compound MC is filled in the gap between vertical conductive structure 124 and vertical conductive structure 144 to form insulation system.
In certain embodiments, moulding compound MC includes the material with of a relatively high dielectric constant, it may for example comprise high K polymer or Silicon stone.In certain embodiments, compression molded, transfer molding and liquid sealant molding are the appropriate method for forming moulding compound MC, but the invention is not restricted to this.For example, it is possible to distribute moulding compound MC in liquid form.Subsequently, curing process is performed to solidify moulding compound MC.In certain embodiments, conduction molding through hole 207, component pipe core 208 and vertical conductive structure 124 and 144 are overflowed in the filling of moulding compound MC so that the end face of moulding compound MC covering device tube core 208 and conduction molding through hole 207.
It follows that in operation S390, perform grinding technics.It follows that in operation S399, perform chemically mechanical polishing (CMP) technique.In operation S390 and S399, as shown in figure 13, remove the redundance of moulding compound MC, and grinding back surface moulding compound MC is to reduce its integral thickness, therefore, expose conduction molding through hole 207 and vertical conductive structure 124 and 144.
Because obtained structure includes the conduction molding through hole 207 extending through moulding compound MC, so conduction molding through hole 207 and vertical conductive structure 124 and 144 are also known as molding through hole (TMV), internal run-through hole (TIV) etc..In order to illustrate, conduction molding through hole 207 provides and the electrical connection of the dorsal part RDL204 in packaging part 200.In certain embodiments, the reduction process for exposing conduction molding through hole 207 is additionally operable to expose the conductive pole 2081 of component pipe core 208.
It follows that in operation S400, as shown in figure 14, conductive layer 210 is formed on moulding layer and moulding compound MC.Such as, in certain embodiments, the conductive material forming conductive layer 210 includes copper, silver, gold etc..
It follows that in operation S410, as shown in figure 15, the photoresist 1501 of patterning is formed above conductive layer 210.Photomask (not shown) is used to carry out a part for exposure photo-etching glue 1501.Then, according to using negativity or positive corrosion-resisting agent, remove the exposure of photoresist 1501 or unexposed part.Remove a part for photoresist 1501 to form the opening being positioned at the exposure of vertical conductive structure 124 area above place at conductive layer 210, and the photoresist 1501 of the patterning at the obtained region place being arranged on conductive layer 210 covers vertical conductive structure 144.
It follows that in operation S420, as shown in figure 16, perform etch process to remove the expose portion of conductive layer 210.In certain embodiments, etch process includes plasma etching, but the invention is not restricted to this.
It follows that in operation S430, as shown in figure 16, remove photoresist 1501.In certain embodiments, plasma ashing or wet stripping technology are used for removing photoresist 1501.In certain embodiments, after plasma ash process, by sulphuric acid (H2SO4) wet impregnation in solution cleans packaging part 200 and remove remaining Other substrate materials.
Therefore, conductive plane 142 is formed in conductive layer 210 and is electrically coupled to vertical conductive structure 144.When completing operation S430, the semiconductor structure 100 including electrode 120 and electrode 140 is formed in packaging part 200.As shown in figure 16, electrode 120 includes conductive plane 122 and vertical conductive structure 124, and electrode 140 includes conductive plane 142 and vertical conductive structure 144.Vertical conductive structure 124 and vertical conductive structure 144 are interlaced, and moulding compound MC is filled between electrode 120 and electrode 140 as dielectric material 160.
It follows that in operation S440, as shown in figure 17, the polymeric layer 211 with the patterning of opening is formed on moulding compound MC and conductive layer 210.In certain embodiments, polymeric layer 211 includes PI, PBO, BCB, epoxy resin, silicones, acrylate, nano-filled phenol resin, siloxanes, fluoropolymer, polynorbornene etc..In certain embodiments, polymeric layer 211 is selectively exposed to plasma etching agent, for instance, this plasma etching agent includes CF4、CHF3、C4F8, HF etc., and be configured to etching polymer layer 211 to form opening.
In certain embodiments, opening is filled with conductive material.In order to illustrate, crystal seed layer (not shown) is formed in the opening, and such as, uses electrochemistry plating, electroless plating etc. to carry out plated conductive material in the opening.Illustrating to example as shown, the obtained through hole in polymeric layer 211 is electrically coupled to conductive pole 2081, conductive layer 210 or conduction molding through hole 207.
In certain embodiments, the one or more additional polymeric layer with conductive component is formed above polymeric layer 211.In operation S450, as shown in figure 17, the RDL212 with conductive component is formed.Illustrate to example as shown, in certain embodiments, by the through hole in polymeric layer 211, conductive component is electrically coupled to conductive layer 210.
It follows that in operation S460, as shown in figure 18, the polymeric layer 213 with the patterning of opening is formed on the polymeric layer 211 and RDL212 of patterning.In certain embodiments, polymeric layer 213 includes PI, PBO, BCB, epoxy resin, silicones, acrylate, nano-filled phenol resin, siloxanes, fluoropolymer, polynorbornene etc..In certain embodiments, polymeric layer 213 is selectively exposed to plasma etching agent, for instance, this plasma etchant includes CF4、CHF3、C4F8, HF etc., and be configured to etching polymer layer 213 to form opening.
It follows that in operation S470, as shown in figure 18, form the RDL214 with at least one conductive component.Illustrate to example as shown, in certain embodiments, by the through hole in polymeric layer 213 conductive component is electrically coupled to the conductive component in RDL212.By conductive through hole conductive component is electrically coupled to component pipe core 208, and by conductive through hole and conductive layer 210, conductive component is electrically coupled to electrode 140.In certain embodiments, RDL212 and 214 are all substantially similar with dorsal part RDL204 in composition and formation process, therefore, in order to concisely, omit detailed description.In certain embodiments, as shown in figure 18, the polymeric layer 215 of patterning is formed on the polymeric layer 213 and RDL214 of patterning.
Next, in operation S480, as shown in figure 19, then joint outer part 217 is formed to be electrically connected to component pipe core 208 by RDL214, this joint outer part is configured to input/output (I/O) pad, for instance this i/o pads includes the soldered ball on Underbump metallization (UBM) 216.In certain embodiments, connector 217 is provided in BGA (BGA) ball on UBM216, controlled collapse chip connection (C4) projection etc., and wherein, UBM216 is formed above RDL214.In certain embodiments, connector 217 is for being electrically connected to other package assemblings by InFO packaging part 200, for instance other package assemblings include another component pipe core, intermediary layer, package substrate, printed circuit board (PCB), mainboard etc..
It follows that remove carrier 201 and adhesive layer 202 from InFO packaging part.Fig. 2 illustrates obtained structure.In certain embodiments, also polymeric substrate layers 203 is removed from InFO packaging part.In some alternative embodiments, do not remove polymeric substrate layers 203, and this polymeric substrate layers is stayed in obtained structure as bottom protective layer.
Illustrated above include exemplary operation, but it is not necessary that perform this operation with shown order.The spirit and scope of each embodiment according to the present invention, it is possible to suitably add, replace, reset and/or remove operation.
The schematic diagram of another integrated multi output (InFO) packaging part 200 of the semiconductor structure 100 including Fig. 1 of some other embodiments according to the present invention is showed with reference to Figure 20, Figure 20.Engage the embodiment of Fig. 2, in order to make it easy to understand, utilize identical reference number to indicate the identical element in Figure 20.
Compared with the embodiment shown in Fig. 2, in the embodiment schematically shown in fig. 20, dielectric material 160 and moulding compound MC are different materials.Dielectric material 160 is filled between the vertical conductive structure 124 in semiconductor structure 100 and vertical conductive structure 144 to form insulation system.Such as, in certain embodiments, the dielectric constant values (or dielectric constant) of dielectric material 160 dielectric constant values more than moulding compound MC.In certain embodiments, moulding compound MC is applied in the moulding layer outside semiconductor structure 100 with around component pipe core 208, and moulding compound MC has low k-value, for instance, less than approximately 3.9, and it is even less than about 2.5 in other embodiments.In certain embodiments, moulding compound MC includes any suitable material, for instance, epoxy resin, molded bottom implant etc..
In certain embodiments, dielectric material 160 includes room temperature (such as, 25 DEG C) liquid phase height K polymer, for instance, polyimides (PI), polybenzoxazoles (PBO) etc..In some other embodiments, dielectric material 160 includes the dielectric constant room temperature more than or equal to about 4 or low temperature (such as, lower than 250 DEG C) liquid phase SiO2Or spin-coating glass (SOG).In some other embodiments, dielectric material 160 includes liquid phase SiNx or other high-k dielectrics.In some other embodiments, dielectric material 160 includes low temperature (such as, 180 DEG C) chemical vapor deposited SiO2(CVD-SiO2), SiNx or SiOxNy deposition, such as, deposition includes atmospheric pressure chemical vapor deposition CVD (APCVD), subatmospheric CVD (SACVD), plasma enhanced CVD (PECVD), metallorganic CVD (MOCVD) etc..In some other embodiments, dielectric material 160 includes low temperature (such as, 210 DEG C) high k dielectric deposition, it may for example comprise ZrO2-Al2O3-ZrO2(ZAZ)；Or other high k dielectrics deposition, it may for example comprise ZrO2、Al2O3、HfOx、HfSiOx、ZrTiOx、TiO2, TaOx etc..In some other embodiments, dielectric material 160 includes SrO (ALD-SrO) electrode of mixing ald and chemical vapor deposited RuO2(CVD-RuO2) dielectric layer.Such as, in some other embodiments, dielectric material 160 includes SrRuO3-SrTiO3-SrRuO3(SRO-STO-SRO) structure.
Figure 21 is the flow chart illustrating and illustrating the method 2100 forming integrated multi output (InFO) packaging part 200 according to some embodiments of the present invention.In order to be more fully understood that the present invention, in conjunction with semiconductor structure 100 discussion method 2100 shown in Fig. 1, and Figure 20 is not limited to this.
In order to illustrate, the manufacturing process of integrated multi output (InFO) packaging part 200 shown in Figure 20 is described by method 2100 by Figure 22 to Figure 26.Figure 22 to Figure 26 is the sectional view of integrated multi output (InFO) packaging part 200 of the different phase in manufacturing process according to some embodiments of the present invention.After the different stage of Fig. 4 to Figure 19 and Figure 22 to Figure 26, packaging part 200 has the sectional view in Figure 20.Although describing Figure 22 to Figure 26 together with method 2100, it should be appreciated that the structure disclosed in Figure 22 to Figure 26 is not limited to method 2100.In conjunction with Fig. 4 to Figure 19, in order to make it easy to understand, utilize identical reference number to indicate the identical element in Figure 22 to Figure 26.
Compared with the method 300 shown in Fig. 3, in the method 2100 shown in Figure 21, moulding compound MC includes the material with relatively low dielectric constant, it may for example comprise epoxy resin, molded bottom implant etc..
After grinding technics in implementing operation S390, as shown in figure 13, operation S391 is implemented.In operation S391, as shown in figure 22, it is formed over the photoresist 2201 of patterning at moulding compound MC.Use the part of photomask (not shown) exposure photo-etching glue 2201.According to using negativity or positive photoresist, then remove the exposure of photoresist 2201 or unexposed part.Remove the opening that the part of photoresist 2201 exposes with the region place between vertical conductive structure 124 and vertical conductive structure 144 forming moulding compound MC, and the photoresist 2201 of obtained patterning is arranged on the region place around component pipe core 208 of moulding compound MC.
It follows that as shown in figure 23, etch process is implemented to remove the expose portion between vertical conductive structure 124 and vertical conductive structure 144 of moulding compound MC.In certain embodiments, application uses HF and AMAR (Cu+NH3Mixture) wet etching process.In some other embodiments, application uses the wet etching of HF and LDPP (comprising TMAH).
It follows that in operation S395, as shown in figure 24, remove photoresist 2201.In certain embodiments, use wet stripping technology to remove photoresist 2201.In certain embodiments, during wet stripping technology, dimethyl sulfoxide (DMSO) and tetramethyl ammonium hydroxide (TMAH) are used for removing Other substrate materials.Such as, use dimethyl sulfoxide (DMSO) to remove photoresist 2201 to dissolve photoresist 2201 and to make photoresist 2201 expand, and tetramethyl ammonium hydroxide (TMAH) is used for cutting crosslinked polymer.
It follows that in operation S397, as shown in figure 25, form dielectric material 160 between vertical conductive structure 124 and vertical conductive structure 144 and on moulding layer 209.In certain embodiments, the dielectric constant of dielectric material 160 dielectric constant higher than moulding compound MC.
It follows that as shown in figure 26, chemically mechanical polishing (CMP) technique in operation S399 is implemented to remove the redundance of dielectric material 160 and to expose the conductive component of such as conductive material 206, conductive through hole 207 and conductive pole 2081.Therefore, the dielectric material 160 being different from moulding compound MC is filled between vertical conductive structure 124 and vertical conductive structure 144.
In certain embodiments, method 2100 includes the operation S310 to S390 implemented before operation S391 and the operation S400 to S480 implemented after operation S399.Operation S310 to S390 and operation S400 to S480 in method 2100 are similar to the operation in method 300, and have been described fully these operations in paragraph above and Fig. 4 to Figure 20.Therefore, to put it more simply, eliminate the description of detail.
The exemplary operation that includes described above, but operation need not be implemented in the order shown.The spirit and scope of each embodiment according to the present invention, it is possible to suitably add, replace, reset and/or remove operation.
With reference to Figure 27.Figure 27 is the schematic diagram of another integrated multi output (InFO) packaging part 200 of the semiconductor structure 100 including Fig. 1 illustrating each embodiment according to the present invention.Engage the embodiment of Fig. 2, in order to make it easy to understand, utilize identical reference number to indicate the identical element in Figure 27.
Compared with the embodiment shown in Fig. 2, in the embodiment schematically shown in fig. 20, component pipe core 208 includes two conductive poles 2081 and 2081, and conduction molding through hole 207 is arranged in the opposite side place of component pipe core 208.In order to illustrate, in certain embodiments, conduction molding through hole 207 is electrically connected to joint outer part 217a with ground connection by RDL212 and 214, and is electrically connected to vertical conductive structure 124 by dorsal part redistributing layer 204.Therefore, the bottom electrode ground connection of mim structure.Conductive pole 2081 is electrically connected to the positive voltage side of finger MIM by RDL212 and 214.Additionally, vertical conductive structure 144 is electrically connected to each other by RDL212.Therefore, the upper electrode of mim structure is connected to component pipe core 208 by RDL214 and conductive pole 2801.Conductive pole 2082 is electrically connected to joint outer part 217b with the input signal by joint outer part 217b receiving device tube core 208 by RDL212 and 214.Be similar to the embodiment shown in Fig. 2, high k moulding compound MC be filled in moulding layer 209 and be filled between the vertical conductive structure 124 in semiconductor structure 100 and vertical conductive structure 144 with formed finger type MIM capacitor structure for suppress by conductive pole 2081 and RDL214,212 and 210 signal noises transmitted from component pipe core 208.In certain embodiments, vertical conductive structure 124 and 144 has square shape, rectangular shape and any suitable shape or their any combination in the sectional views.
The manufacturing process of integrated multi output (InFO) packaging part 200 shown in Figure 27 is similar to the manufacturing process of integrated multi output (InFO) packaging part 200 shown in Fig. 2, in above paragraph, it is more fully described and therefore to the purpose simplified omits its detailed description.
With reference to the schematic diagram that Figure 28, Figure 28 are another integrated multi output (InFO) packaging parts 200 illustrating the semiconductor structure 100 included in Fig. 1 according to an alternative embodiment of the invention.With reference to the embodiment of Figure 20, in order to make it easy to understand, utilize identical reference number to indicate the identical element in Figure 28.
Compared with the embodiment shown in Figure 27, in the embodiment schematically shown in Figure 28, dielectric material 160 and moulding compound MC are different materials.Dielectric material 160 is filled between the vertical conductive structure 124 in semiconductor structure 100 and vertical conductive structure 144 to form insulation system.Such as, in certain embodiments, the dielectric constant values (or dielectric constant) of dielectric material 160 dielectric constant values more than moulding compound MC.In certain embodiments, moulding compound MC is applied in the moulding layer outside semiconductor structure 100 with around component pipe core 208, and moulding compound MC has low k-value, for instance, less than approximately 3.9, and it is even less than about 2.5 in other embodiments.In certain embodiments, moulding compound MC includes any suitable material, for instance, epoxy resin, molded bottom implant etc..Similarly, the manufacturing process of integrated multi output (InFO) packaging part 200 shown in Figure 28 is similar to the manufacturing process of integrated multi output (InFO) packaging part 200 shown in Figure 20, and in paragraph above, it has been more fully described and therefore to the purpose simplified omits its detailed description.
In certain embodiments, disclosing a kind of semiconductor device, semiconductor device includes component pipe core, around the moulding layer of component pipe core, multiple first vertical conductive structure formed in moulding layer and multiple second vertical interconnection structures of being formed in moulding layer.First vertical conductive structure and the second vertical conductive structure interlaced (interlaced), and insulation system formation is between the first vertical conductive structure and the second vertical conductive structure.
Preferably, in the semiconductor device, in described moulding layer, moulding compound is applied with around described component pipe core and form described insulation system.
Preferably, in the semiconductor device, described moulding compound includes polymer or Silicon stone.
Preferably, in the semiconductor device, described moulding layer is applied moulding compound with around described component pipe core, and in described moulding layer, apply dielectric material to form described insulation system.
Preferably, in the semiconductor device, the dielectric constant of described dielectric material is higher than the dielectric constant of described moulding compound.
Preferably, in the semiconductor device, described dielectric material includes polyimides or polybenzoxazoles.
Preferably, in the semiconductor device, described dielectric material includes silicon nitride or silicon dioxide.
Preferably, in the semiconductor device, described dielectric material includes ZrO2、Al2O3、HfOx、HfSiOx、ZrTiOx、TiO2With at least one in TaOx.
Preferably, in the semiconductor device, described dielectric material includes SrRuO3-SrTiO3-SrRuO3Structure or ZrO2-Al2O3-ZrO2Structure.
Preferably, in the semiconductor device, described first vertical conductive structure is distributed as comb mesh pattern, and described second vertical conductive structure is distributed as comb mesh pattern.
Preferably, this semiconductor device also includes: the first polymeric layer, is positioned at above described moulding layer；First redistributing layer, is positioned at above described first polymeric layer；The second polymer layer, is positioned at above described first redistributing layer；And second redistributing layer, it is positioned at above described the second polymer layer；Wherein, the second conductive plane is formed in described first redistributing layer, and described component pipe core and described second conductive plane are by described second redistributing layer electric coupling.
Also disclosing that a kind of method, method includes forming the first conductive plane (plane) on substrate；First conductive plane is formed multiple first vertical conductive structure and multiple first vertical conductive structure is electrically connected to the first conductive plane；Forming multiple second vertical conductive structure on substrate, wherein, the first vertical conductive structure and the second vertical conductive structure are interlaced, and insulation system is formed between the first vertical conductive structure and the second vertical conductive structure；Component pipe core is attached on substrate；Being arranged in the moulding layer application moulding compound above substrate with around component pipe core；And in moulding layer, form the second conductive plane, wherein, the second conductive plane is electrically connected to the second vertical conductive structure.
Preferably, the method also includes: apply described moulding compound with around described component pipe core, described first vertical conductive structure and described second vertical conductive structure being arranged in the moulding layer above described substrate.
Preferably, the method also includes: apply dielectric material between described first vertical conductive structure and described second vertical conductive structure to form insulation system, and wherein, the dielectric constant of described dielectric material is higher than the dielectric constant of described moulding compound.
Preferably, the method also includes: form first polymeric layer with multiple opening on described moulding layer；And on described first polymeric layer, form the first redistributing layer to form the second conductive plane.
Preferably, the method also includes: form the second polymer layer with multiple opening on described first redistributing layer；The second redistributing layer is formed on described the second polymer layer；And on described second redistributing layer, form third polymer layer, wherein, described component pipe core and described second conductive plane are by described second redistributing layer electric coupling.
Also disclose that a kind of method, method includes formation capacitor arrangement on substrate, wherein, capacitor arrangement includes multiple first vertical conductive structure, multiple second vertical conductive structure and the insulation system between the first vertical conductive structure and the second vertical conductive structure；Component pipe core is attached on substrate；And being arranged in the moulding layer application moulding compound above substrate with around component pipe core and capacitor arrangement.
Preferably, in the method, described insulation system includes dielectric material, and the dielectric constant of described dielectric material is higher than the dielectric constant of described moulding compound.
Preferably, in the method, described capacitor arrangement also includes the first conductive plane being electrically coupled to described first vertical conductive structure, and it is electrically coupled to the second conductive plane of described second vertical conductive structure, and method also includes: face forms dorsal part redistributing layer to form described first conductive plane over the substrate；First polymeric layer with multiple opening is formed on described moulding layer；And on described first polymeric layer, form the first redistributing layer to form the second conductive plane.
Preferably, the method also includes: form the second polymer layer with multiple opening on described first redistributing layer；The second redistributing layer is formed on described the second polymer layer；And on described second redistributing layer, form third polymer layer, wherein, described component pipe core and described second conductive plane are by described second redistributing layer electrical connection.
Foregoing has outlined the feature of some embodiments so that those skilled in the art can be more fully understood that each aspect of the present invention.It should be appreciated by those skilled in the art that they can readily use to design based on the present invention or revise for implementing the purpose identical with in this introduced embodiment and/or realizing other techniques and the structure of identical advantage.Those skilled in the art are it should also be appreciated that this equivalent constructions is without departing from the spirit and scope of the present invention, and when without departing substantially from the spirit and scope of the present invention, at this, they can make multiple change, replacement and change.

Claims (10)

1. a semiconductor device, including:
Component pipe core；
Moulding layer, around described component pipe core；
Multiple first vertical conductive structure, are formed in described moulding layer；And
Multiple second vertical conductive structure, are formed in described moulding layer；
Wherein, described first vertical conductive structure and described second vertical conductive structure are interlaced, and insulation system is formed between described first vertical conductive structure and described second vertical conductive structure.
2. semiconductor device according to claim 1, wherein, applies moulding compound with around described component pipe core and form described insulation system in described moulding layer.
3. semiconductor device according to claim 2, wherein, described moulding compound includes polymer or Silicon stone.
4. semiconductor device according to claim 1, wherein, applies moulding compound in described moulding layer with around described component pipe core, and applies dielectric material in described moulding layer to form described insulation system.
5. semiconductor device according to claim 4, wherein, the dielectric constant of described dielectric material is higher than the dielectric constant of described moulding compound.
6. semiconductor device according to claim 4, wherein, described dielectric material includes polyimides or polybenzoxazoles.
7. semiconductor device according to claim 4, wherein, described dielectric material includes silicon nitride or silicon dioxide.
8. semiconductor device according to claim 4, wherein, described dielectric material includes ZrO2、Al2O3、HfOx、HfSiOx、ZrTiOx、TiO2With at least one in TaOx.
9. a method, including:
Substrate is formed the first conductive plane；
Described first conductive plane is formed multiple first vertical conductive structure and the plurality of first vertical conductive structure is electrically coupled to described first conductive plane；
Forming multiple second vertical conductive structure over the substrate, wherein, described first vertical conductive structure and described second vertical conductive structure are interlaced, and insulation system is formed between described first vertical conductive structure and described second vertical conductive structure；
Component pipe core is attached over the substrate；
Being arranged in the moulding layer application moulding compound above described substrate with around described component pipe core；And
Forming the second conductive plane on described moulding layer, wherein, described second conductive plane is electrically coupled to described second vertical conductive structure.
10. a method, including:
Forming capacitor arrangement on package structure, wherein, described capacitor arrangement includes multiple first vertical conductive structure, multiple second vertical conductive structure and the insulation system between described first vertical conductive structure and described second vertical conductive structure；
Component pipe core is attached on substrate；And
Being arranged in the moulding layer application moulding compound above described substrate with around described component pipe core and described capacitor arrangement.
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DE102016015938B3 (en) 2023-07-20
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