KR20160089883A - Vertical metal insulator metal capacitor - Google Patents

Abstract

The specification discloses a semiconductor device and a method. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed in the molding layer, and a plurality of second vertical conductive structures formed in the molding layer. The first vertical conductive structures and the second vertical conductive structures intersect with each other. An insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures. So, a change in MIM capacitance can be reduced.

Description

{Vertical Metal Insulator Metal Capacitor}

Reference to Related Application

This application is a divisional application of U.S. Serial No. 12 / 825,605, filed June 29, 2010, which claims priority to U.S. Provisional Application No. 61 / 259,787, filed November 10, 2009, A continuation-in-part (cip) applicant of U.S. Serial No. 14 / 337,530, filed July 22, 2014, filed on January 20, 2015, which is a cip application of U.S. Serial No. 14 / 600,777, The whole is incorporated by reference.

The present invention relates to vertical metal insulator metal capacitors.

Capacitors are widely used in integrated circuits. The capacitance of the capacitor is proportional to the capacitor area and the dielectric constant (k) of the insulating layer, and is inversely proportional to the thickness of the insulating layer. Thus, in order to increase the capacitance, it is desirable to increase the area and k value and reduce the thickness of the insulating layer.

The problem associated with the increased area is that a larger chip area is required. Conventional metal-insulator-metal (MIM) capacitors in integrated circuits have various horizontal comb structures. The horizontal structure capacitance is correlated with the intermetallic layer thickness. However, the thickness of the interlayer metal layer is very difficult to control. This increases the variation of the MIM capacitance in the generation for the target value. Thus, new methods and structures are required for MIM capacitors.

In some embodiments, a semiconductor device is disclosed that includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed in the molding layer, And includes a plurality of second vertical electrically conductive structures. The first vertical conductive structure and the second vertical conductive structure are intertwined with each other, and an insulating structure is formed between the first vertical conductive structure and the second vertical conductive structure.

A method is also disclosed, the method comprising: forming a first conductive plane on a substrate; forming a plurality of first vertical conductive structures on the first conductive plane and electrically connected to the first conductive plane And forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structure and the second vertical conductive structure are entangled with each other, and the first vertical conductive structure and the second vertical conductive structure The method comprising: forming the plurality of second vertical electrically conductive structures wherein an insulating structure is formed between the structures; attaching a device die on the substrate; forming molding compound Forming a second conductive plane on the molding layer, wherein the second conductive plane And the plane is electrically connected to the second vertical conductive structure.

A method is also disclosed, the method comprising: forming a capacitor structure on a substrate, the capacitor structure comprising a plurality of first vertical conductive structures, a plurality of second vertical conductive structures, The method comprising: forming the capacitor structure, wherein the capacitor structure comprises an insulating structure between the first and second vertical conductive structures; attaching a device die on the substrate; forming a molding on the substrate to surround the device die and the capacitor structure; And applying a molding compound into the layer.

The aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practice in industry, various features are not drawn at scale. In fact, the dimensions of the various features may optionally be increased or decreased for clarity of discussion.
1 is a schematic diagram illustrating a semiconductor structure with vertical capacitors according to some embodiments of the present disclosure;
2 is a schematic diagram illustrating an integrated fan-out package (InFO) package including the semiconductor structure of FIG. 1 in accordance with some embodiments of the present disclosure;
Figure 3 is a flow chart illustrating a method of fabricating the semiconductor structure of Figure 2 in accordance with some embodiments of the present disclosure.
Figures 4 to 19 are cross-sectional views of the package of Figure 2 at different stages of the manufacturing process, in accordance with some embodiments of the present disclosure.
Figure 20 is a schematic diagram illustrating an InFO package including the semiconductor structure of Figure 1 in accordance with some embodiments of the present disclosure;
Figure 21 is a flow chart illustrating a method of fabricating the semiconductor structure of Figure 20 in accordance with some embodiments of the present disclosure.
Figures 22-25 are cross-sectional views of the package of Figure 20 at another stage of the manufacturing process, in accordance with some embodiments of the present disclosure.
Figure 27 is a schematic diagram illustrating an InFO package including the semiconductor structure of Figure 1 in accordance with some embodiments of the present disclosure;
Figure 28 is a schematic diagram illustrating an InFO package including the semiconductor structure of Figure 1 in accordance with some embodiments of the present disclosure;

This disclosure provides many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and devices are described below to simplify the present disclosure. Of course, these are examples only, and are not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and the first feature Embodiments may also include embodiments in which additional features may be formed between the first feature and the second feature such that the second feature and the second feature do not directly contact each other. In addition, the present disclosure may repeat the reference numerals and / or characters in various examples. These iterations are for simplicity and clarity and do not affect the relationship between the various embodiments and / or configurations discussed in and of themselves.

The terms used herein have their ordinary meaning in the art and the specific context in which each term is used. Use of the examples herein, including examples of any of the terms discussed herein, is for illustrative purposes only, and does not in any way limit the scope and meaning of the disclosure or any illustrated term. Likewise, the present disclosure is not limited to the various embodiments given in this specification.

Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, the first element may be termed as the second element, and similarly the second element may be termed as the first element. As used herein, the term " and / or " includes any and all combinations of one or more associated enumerated items.

It will also be appreciated that spatially relative terms such as "below", "under", "under", "above", "above", etc., ) Or feature (s) for the purposes of discussion herein. Spatially relative terms are intended to encompass different orientations of the device being used or operating, in addition to the orientations shown in the figures. The device may be oriented differently (rotated 90 degrees or other orientation), and the spatially relative descriptor used herein may be similarly interpreted accordingly.

In this embodiment, the term " coupled " may also be referred to as " electrically connected " and the term " conneted " The terms " connected " and " connected " may also be used to indicate that two or more elements cooperate or interact with one another.

1 is a schematic diagram illustrating a semiconductor structure 100 including a vertical capacitor 100 in accordance with some embodiments of the present disclosure.

As illustrated diagrammatically in FIG. 1, semiconductor structure 100 includes electrodes 120 and 140. The electrode 120 includes a conductive plane 122 and a vertical conductive structure 124. Electrode 140 includes a conductive plane 142 and a vertical conductive structure 144. The vertical conductive structure 124 and the vertical conductive structure 144 are entangled with each other and a dielectric material 160 is filled between the electrode 120 and the electrode 140.

The conductive plane 122 and the conductive plane 142 include a conductive material including, for example, copper, silver, gold, and the like. In some embodiments, the conductive plane 122 and the conductive plane 142 comprise a suitable conductive material other than metal.

See FIG. Figure 2 is a schematic diagram illustrating an integrated fan-out (InFO) package 200 including a semiconductor structure 100 as illustrated in Figure 1 in accordance with some embodiments of the present disclosure. For the embodiments of FIG. 1, similar elements in FIG. 2 are designated with the same reference numerals to facilitate understanding.

For example, the package 200 may include a polymer base layer 203, an InFo redistribution layer (RDL) 204, a seed layer 205, a conductive material 206, a conductive through molding via (TMV) 207, a device die 208, a molding layer 209, a conductive layer 210, polymer layers 211, 213 and 215, redistribution layers (RDL) 212 and 214, UBM Bump Metallurgy 216, and an external connector 217.

As illustrated in FIG. 2, in some embodiments, the semiconductor structure 100 shown in FIG. 1 is formed in an InFO (Integrated Fan-Out) package 200. Since the semiconductor structure 100 is fabricated simultaneously by other features of the package 200, the fabrication cost is relatively low.

The semiconductor structure 100 includes a vertical conductive structure 124 formed in the molding layer 209 and electrically connected to the conductive plane 122 and a conductive layer 124 formed in the molding layer 209 and electrically (Not shown). The conductive plane 142 is disposed over the molding layer 209. The vertically conductive structures 124 and 144 are formed by a conductive material 206 overlying the seed layer 205 and are formed through a through molding via TMV extending through a molding compound MC Is charged. The conductive plane 122 is formed in the RDL 204 if it is InFO. The conductive plane 142 is formed in the RDL 212 and the device 208 and the conductive plane 142 are electrically connected through the RDL 214.

In some embodiments, the vertical conductive structure 124 and the vertical conductive structure 144 may be formed into a square shape, a rectangular shape, a circular shape, an elliptical shape, any other suitable shape in cross section, I have. The vertical conductive structures 124 are uniformly distributed on the conductive planes 122 and the vertical conductive structures 144 are uniformly distributed below the conductive planes 142. In some embodiments, the vertical conductive structures 124 are distributed in a square grid pattern on the conductive plane 122 and the vertical conductive structures 144 are distributed in a square grid pattern below the conductive plane 142.

In some embodiments, the molding compound MC is applied to the molding layer 209 to surround the device die 208, the vertical conductive structure 124, and the vertical conductive structure 144 on the polymer base layer 203 . Alternately, in some embodiments, the molding compound MC in the InFO package 200 may include a vertical conductive structure 124 and a vertical conductive structure 144 as the dielectric material 160 shown in FIG. . In some embodiments, the molding compound (MC) comprises a high-k polymer or silica.

In some embodiments, the polymer layer 211 is over the molding layer 209. The RDL 212 is over the polymer layer 211. The polymer layer 213 is above the RDL 212. The RDL 214 is over the polymer layer 213. The polymer layer 215 is above the RDL 214. The UBM 216 is formed over the RDL 214. The external connector 217 is configured to be an input / output (I / O) pad that is disposed on the UBM 216 and includes a solder ball that is electrically connected to the device die 208, for example, do. In some embodiments, the external connector 217 is a ball grid array (BGA) ball, a controlled collapse chip connector (C4) bump, or the like. In some embodiments, connector 217 is used to electrically connect package 200 to other package components, including, for example, other device die, interposer, package substrate, printed circuit board, motherboard, .

FIG. 3 is a flow chart illustrating a method 300 of forming an InFO package 200 as illustrated in FIG. 2, in accordance with some embodiments of the present disclosure. For a better understanding of the present disclosure, the method 300 is discussed with respect to the semiconductor structure shown in Figures 1 and 2, but is not limited thereto.

For illustrative purposes, the fabrication process of the InFO package 200 illustrated in FIG. 2 is illustrated by method 300 in conjunction with FIGS. 4-19. 4 through 19 are cross-sectional views of an InFO package 200 at different stages of the manufacturing process, in accordance with some embodiments of the present disclosure. After the other stages in Figs. 4-19, the package 200 has a cross-sectional view in Fig. Although FIGS. 4 through 19 are described with method 300, it will be appreciated that the structures disclosed in FIGS. 4 through 19 are not limited to method 300. Similar elements in Figures 4 to 19 are designated with the same reference numerals for ease of understanding.

While the disclosed methods are illustrated and described herein as a series of acts or events, it should be appreciated that the illustrated sequence of events or events should not be construed in a limiting sense. For example, some operations may occur in a different order and / or concurrently with other operations or events, except for those illustrated and / or described herein. Furthermore, all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Also, one or more operations depicted herein may be performed in one or more separate operations and / or phases.

Referring to method 300 of FIG. 3, at operation S310, a carrier 201, an adhesive layer 202, and a polymer base layer 203 are provided, as illustrated in FIG.

In some embodiments, the carrier 201 comprises glass, ceramic, or other suitable material to provide structural support during formation of various features in the device package. In some embodiments, an adhesive layer 202 is disposed on the carrier 201, including, for example, a glue layer, a light-to-heat conversion (LTHC) coating, an ultraviolet (UV) The polymer base layer 203 is coated on the carrier 201 through the adhesive layer 202. In some embodiments, the carrier 201 and the adhesive layer 202 are removed from the InFO package after the packaging process. In some embodiments, the polymeric base layer 203 can be made of a material selected from the group consisting of PolyBenzOxazole (PBO), Ajinomoto Buildup Film (ABF), polyimide, BenzoCycloButene (BCB) A solder resist (SR) film, a die-attach film (DAF), or the like, but the disclosure is not limited thereto.

For the method 300 of FIG. 3, in operation S320, thereafter a Forward Redistribution Layer (RDL) 204 is formed, as illustrated in FIG. In some embodiments, the backside RDL 204 includes a conductive feature including, for example, conductive lines and / or vias formed in one or more polymer layers. In some embodiments, the polymer layer may be formed using any suitable method, including, for example, spin-on-coding techniques, sputtering, etc., to form PO, PBO, BCB, epoxy, silicone, acrylate, , Fluorinated polymers, polynorbornene, and the like.

In some embodiments, the conductive features are formed in the polymer layers. The formation of such a conductive feature can be accomplished, for example, by patterning the polymer layer using a combination of photolithography and etching processes, and using a mask layer to define the shape of the conductive feature, for example, a seed layer (i.e., TiCu) And then plating the conductive metal layer (i.e., Cu) to form the conductive features in the patterned polymer layer. For illustrative purposes, some of the conductive features are designed to form the conductive plane 122 of the semiconductor structure 100, and some other conductive features are designed to form functional circuitry and input / output features for the subsequently attached die .

Next, at operation S330, the patterned photoresist 601 is formed over the RDL 204 and the carrier 201 if InFO, as illustrated in FIG. In some embodiments, for example, photoresist 601 is deposited as a blanket layer over backside RDL 204. Next, a part of the photoresist 601 is exposed using a photomask (not shown). Thereafter, the exposed or unexposed portions of the photoresist 601 are removed, depending on whether a negative or positive resist is used. The resulting patterned photoresist 601 includes openings 602 disposed in the peripheral region of the carrier 201. [ In some embodiments, the opening 602 further exposes the conductive features in the backside RDL 204.

Next, in operation S340, the seed layer 205 is deposited on the patterned photoresist 601, as illustrated in FIG.

Next, at operation S350, the opening 602 is filled with a conductive material 206, such as copper, titanium, nickel, tantalum, palladium, silver or gold, etc., to form a conductive via ). In some embodiments, the openings 602 are plated with a conductive material 206 during a plating process including, for example, electro-chemical plating, electroless plating, and the like. In some embodiments, the conductive material 206 overcharges the openings 602 and a chemical mechanical polishing (CMP) process is performed to remove the conductive material 602 over the photoresist 601, as illustrated in FIG. 9, 0.0 > 206 < / RTI >

Next, at operation S360, the photoresist 601 is removed, as illustrated in Fig. In some embodiments, a wet strip process is used to remove the photoresist 601. In some embodiments, the wet strip solution includes dimethylsufoxide (DMSO) and tetramethyl ammonium hydroxide (TMAH) to remove the photoresist material.

Thus, when the vertical conductive structure 124 and the vertical conductive structure 144 are InFO respectively, they are formed on the RDL 204 and the polymer base layer 203. For illustrative purposes, in some embodiments, a conductive through molding via 207 is formed on the backside RDL 204. In some embodiments, the conductive through molding via 207 has a square shape, a rectangular shape, a circular shape, an elliptical shape, any other suitable shape in cross section, or any combination thereof. Alternatively, in some embodiments, the conductive through molding via 207 is replaced with a conductive stud or conductive wire comprising, for example, copper, titanium, nickel, tantalum, palladium, silver or gold wire. In some embodiments, the conductive through molding vias 207 are spaced from each other and from the vertical conductive structure 124 and the vertical conductive structure 144 by an opening 1001. For illustrative purposes, at least one opening 1001 between the conductive through molding via 207 and the semiconductor structure 100 is large enough to place one or more semiconductor die therein.

Next, at operation S370, one or more device dies 208 are mounted and attached to the package 200, as illustrated in Fig. For purposes of illustration, the device package 200 includes a carrier 201 and a back side RDL 204 having conductive features as shown. In some embodiments, other interconnect structures are also included, including conductive through molding vias 207 that are electrically connected to the conductive features in, for example, the backside RDL 204. In some embodiments, an adhesive layer is used to attach the device die 208 to the backside RDL 204.

Next, at operation S380, the molding compound MC is applied to the mold 200 of the package 200 after the device die 208 is mounted on the back side RDL 204 in the opening 1001, Layer 209 as shown in FIG. The molding compound MC is arranged to fill the gap between the device die 208 and the conductive through molding via 207 and the gap between the vertical conductive structure 124 and the vertical conductive structure 144. In some embodiments, the molding compound MC is filled in a gap between the vertical conductive structure 124 and the vertical conductive structure 144 to form an insulating structure.

In some embodiments, the molding compound (MC) comprises, for example, a material having a relatively high dielectric constant, including a high-K polymer or silica. In some embodiments, compression molding, transfer molding, and liquid seal molding are suitable methods of forming a molding compound (MC), but the disclosure is not limited thereto. For example, the molding compound (MC) is disposed in a liquid form. Thereafter, a curing process is performed to solidify the molding compound (MC). In some embodiments, the filling of the molding compound MC causes the molding compound to overflow the conductive through molding vias 207, the device die 208, and the vertical conductive structures 124 and 144, MC covers the top surface of device die 208 and conductive through molding via 207.

Next, in operation S390, the polishing process is performed. Next, in operation S399, a chemical mechanical polishing (CMP) process is performed. As illustrated in Figure 13, at the operations S390 and S399, an excessive portion of the molding compound (MC) is removed, and the molding compound (MC) is back polished to reduce its overall thickness, Vias 207 and vertical conductive structures 124 and 144 are exposed.

The resulting conductive structure includes conductive through molding vias 207 extending through the molding compound MC so that the conductive through molding vias 207 and the vertical conductive structures 124 and 144 also have through molding vias 207, through molding via (TMV), through inter via (TIV), and the like. For example, conductive through molding via 207 provides electrical connection to backside RDL 204 of package 200. In some embodiments, a thinning process used to expose the conductive through molding via 207 is also used to expose the conductive filler 2081 of the device die 208.

Next, in operation S400, as illustrated in Fig. 14, a conductive layer 210 is formed on the molding layer and the molding compound MC. For example, in some embodiments, the conductive material forming the conductive layer 210 includes copper, silver, gold, and the like.

Next, in operation S410, a patterned photoresist 1501 is formed on the conductive layer 210, as illustrated in Fig. Portions of the photoresist 1501 are exposed using a photomast (not shown). Thereafter, the exposed or unexposed portions of the photoresist 1501 are removed, depending on whether a negative or positive resist is used. A portion of the photoresist 1501 is removed to form an exposed opening in the region of the conductive layer 210 overlying the vertical conductive structure 124 and the resulting patterned photoresist 1501 is removed from the vertical conductive structure 144). ≪ / RTI >

Next, in operation S420, as illustrated in Fig. 16, an etching process is performed to remove the exposed portion of the conductive layer 210. [ In some embodiments, the etching process includes plasma etching, but the disclosure is not limited thereto.

Next, in operation S430, the photoresist 1501 is removed, as illustrated in Fig. In some embodiments, a plasma ashing or wet strip process is used to remove the photoresist 1501. In some embodiments, the plasma ashing process is followed by washing the package 200 and wet dipping into a sulfuric acid (H ₂ SO ₄ ) solution to remove residual photoresist material.

Accordingly, the conductive plane 142 is formed in the conductive layer 210 and electrically connected to the vertical conductive structure 114. The semiconductor structure 100 including the electrode 120 and the electrode 140 is formed in the package 200. [ The electrode 120 includes a conductive plane 122 and a vertical conductive structure 124 and the electrode 140 includes a conductive plane 142 and a vertical conductive structure 144, . The vertical conductive structure 124 and the vertical conductive structure 144 are entangled with each other and the molding compound MC is filled as the dielectric material 160 between the electrode 120 and the electrode 140.

Next, in operation S440, a patterned polymer layer 211 having an opening is formed on the molding compound MC and the conductive layer 210, as illustrated in Fig. In some embodiments, the polymer layer 211 may be made of a material selected from the group consisting of PI, PBO, BCB, epoxy, silicone, acrylate, nano-filled pheno resin, siloxane, fluorinated polymer, And the like. In some embodiments, the polymer layer 211 may be selectively etched into a plasma etch comprising, for example, CF ₄ , CHF ₃ , C ₄ F ₈ , HF, and the like configured to etch the polymer layer 211 to form an opening Exposed.

In some embodiments, the opening is filled with a conductive material. For illustrative purposes, a seed layer (not shown) is formed in the opening, and the conductive material is plated in the opening using, for example, an electrochemical plating process, an electroless plating process, or the like. The via hole in the resulting polymer layer 211 is electrically connected to the conductive filler 2081, the conductive layer 210, or the conductive through molding via 207, as illustrated by way of example.

In some embodiments, one or more additional polymeric layers having conductive features are formed over the polymeric layer (211). As illustrated in FIG. 17, in operation S450, an RDL 212 having a conductive feature is formed. As illustrated illustratively, in some embodiments, the conductive features are electrically connected to the conductive layer 210 via via-holes in the polymer layer 211.

18, in operation S460, a patterned polymer layer 213 having openings is formed over the patterned polymer layer 211 and the RDL 212. As shown in FIG. In some embodiments, the polymer layer 213 includes PI, PBO, BCB, epoxy, silicone, acrylate, nano-filled phenolic resin, siloxane, fluorinated polymer, polynorbornene and the like. In some embodiments, the polymer layer 213 may be selectively etched into a plasma etchant comprising, for example, CF ₄ , CHF ₃ , C ₄ F ₈ , HF, etc. configured to etch the polymer layer 211 to form an opening Exposed.

Next, as illustrated in FIG. 18, in operation S470, an RDL 214 having at least one conductive feature is formed. As illustrated illustratively, in some embodiments, the conductive features are electrically connected to the conductive features in the RDL 212 through via holes in the polymer layer 213. The conductive features are electrically connected to the device die 208 through conductive vias and conductive fillers 2081 and electrically coupled to the electrodes 140 through the conductive vias and conductive layer 210. In some embodiments, the RDLs 212 and 214 are substantially similar to the backside RDL 204 in both the composition and formation processes, so that detailed description thereof is omitted for simplicity. In some embodiments, as illustrated in FIG. 18, a patterned polymer layer 215 is formed over the patterned polymer layer 213 and the RDL 214.

19, an external connector 217 configured to be an input / output (I / O) pad including solder balls on an Under Bump Metallurgy (UBM) 216, for example, , And then electrically connected to the device die 208 via the RDL 214. In some embodiments, the connector 217 includes a ball grid array (BGA) ball, a controlled collapse chip connector (not shown) disposed on the UBM 216 formed on the RDL 214, chip connector (C4) bump. In some embodiments, connector 217 may be used to electrically connect InFO package 200 to other package components, including, for example, other device die, interposer, package substrate, printed circuit board, motherboard, Is used.

Next, the carrier 201 and the adhesive layer 202 are removed from the InF0 package. The resulting structure is shown in Fig. In some embodiments, the polymer base layer 203 is also removed from the InFO package. In some alternative embodiments, the polymer base layer 203 is not removed and is left in the resulting package as a bottom protective layer. Next, the carrier 201 and the adhesive layer 202 are removed from the InFO package. The resulting structure is shown in Fig. In some embodiments, the polymer base layer 203 is not removed and is left as a bottom protective layer in the resulting package.

The above example includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, reordered, and / or deleted depending on the spirit and scope of various embodiments of the present disclosure.

See FIG. 20 is a schematic diagram illustrating another InFO package 200 including the semiconductor structure 100 of FIG. 1 in accordance with some other embodiments of the present disclosure. For the embodiments of FIG. 2, similar elements in FIG. 20 are designated with the same reference numerals for ease of understanding.

In contrast to the embodiments shown in FIG. 2, in the embodiments illustrated in FIG. 20, the dielectric material 160 and the molding compound MC comprise different materials. The dielectric material 160 is filled between the vertical conductive structure 124 and the vertical conductive structure 144 of the semiconductor structure 100 to form an insulating structure. For example, in some embodiments, the dielectric constant (or permittivity) of the dielectric material 160 is greater than the dielectric constant (or permittivity) of the molding compound MC. In some embodiments, the molding compound MC is applied to a molding layer outside the semiconductor structure 100 to surround the device die 208 and the molding compound MC is, in other embodiments, Less than 3.9, and even less than about 2.5. In some embodiments, the molding compound (MC) comprises any suitable material including, for example, epoxy resin, molding underfill, and the like.

In some embodiments, the dielectric material 160 comprises a room temperature (e.g., 25 占 폚) liquid high-K polymer that includes polyimide (PI), polybenzoxazole (PBO) In some other embodiments, the dielectric material 118 comprises a liquid phase SiO ₂ or a Spin on Glass (SOG) at room or low temperature (e.g., less than 250%), . In some other embodiments, dielectric material 118 may be deposited using any suitable process, such as, for example, atmospheric pressure CVD (APCVD), sub-atmospheric CVD (SACVD), plasma enhanced CVD (PECVD) , metal organic CVD include;; (CVD-SiO ₂ chemical vapor deposited SiO _2), SiNx, or SiOxNy deposition (metal organic CVD MOCVD) or the like, a low temperature of (e.g., 180 ℃) chemical vapor deposited SiO ₂ comprising a. In some other embodiments, dielectric material 118 is, for example, ZrO ₂ -Al ₂ O ₃ -ZrO low temperature containing ₂ (ZAZ) (e.g., 210 ℃) high -K dielectric deposition, or for example, ZrO _2, K ₂ O ₃ , H ₂ O ₃ , HfO x, HfSiO x, ZrTiO x, TiO ₂ , TaO x, and the like. Part according to other embodiments, dielectric material 118 is a hybrid atomic layer deposition of SrO (atomic layer deposited SrO; ALD-SrO) electrode and a chemical vapor deposited _{RuO 2 (chemical vapor deposited RuO 2} ; CVD-RuO 2) And a dielectric layer. For example, the part according to other embodiments, the dielectric material 118 comprises a _{SrRuO 3 -SrTiO 3 -SrRuO 3 (SRO} -STO-SRO) structure.

FIG. 21 is a flow chart illustrating a method 2100 of forming an InFO package 200 as illustrated in FIG. 20, in accordance with some embodiments of the present disclosure. For a better understanding of the present disclosure, the method 2100 is discussed with respect to the semiconductor structure 100 shown in Figures 1 and 20, but is not limited thereto.

For illustrative purposes, the manufacturing process of the InFO package 200 illustrated in FIG. 20 is illustrated by method 2100 for FIGS. 22-26. 22-26 are cross-sectional views of an InFO package 200 at different stages of the manufacturing process, in accordance with some embodiments of the present disclosure. After the different stages in Figs. 4-19 and 22-26, the package 200 has the cross-section of Fig. Although FIGS. 22-26 are described together using method 2100, it should be appreciated that the structures disclosed in FIGS. 22-26 are not limited to method 2100. For the embodiments of Figs. 4-19, similar elements of Figs. 22-26 are designated with the same reference numerals for ease of understanding.

In contrast to the method 300 illustrated in FIG. 3, in the method 2100 illustrated in FIG. 21, the molding compound MC includes a material having a relatively low dielectric constant, including, for example, epoxy resin, molding underfill, do.

As illustrated in FIG. 13, after the polishing process at operation S390 is performed, operation S391 is performed. In operation S391, as illustrated in Fig. 22, a patterned photoresist 2201 is formed on the molding compound MC. A part of the photoresist 2201 is exposed using a photomask (not shown). Thereafter, the exposed or unexposed portions of the photoresist 2201 are removed depending on whether a negative or positive resist is used. The portion of the photoresist 2201 is removed to form an exposed opening in the region of the molding compound MC between the vertical conductive structure 124 and the vertical conductive structure 144 and placed in the region of the molding compound MC As a result, the patterned photoresist 2201 encapsulates the device die 208.

23, an etching process is performed to remove the exposed portion of the molding compound MC between the vertical conductive structure 124 and the vertical conductive structure 144, at operation S393. In some embodiments, wet etching with HF and AMAR (Cu + NH ₃ compound) is applied. In some other embodiments, wet etching with LDPP and HF containing TMAH is applied.

Next, as illustrated in Fig. 24, in operation S395, the photoresist 2201 is removed. In some embodiments, a wet strip process is used to remove the photoresist 2201. In some embodiments, during the wet strip process, dimethylsulfoxide (DMSO) and tetramethyl ammonium hydroxide (TMAH) are used to remove the photoresist material. For example, the photoresist 2201 is removed using dimethylsulfoxide (DMSO) to dissolve the photoresist 2201 and swell the photoresist 2201, and tetramethylammonium hydroxide (TMAH) It is used to cut cross-linkage.

Next, dielectric material 160 is formed over molding layer 209 and between vertical conductive structure 124 and vertical conductive structure 144 in operation S397, as illustrated in Fig. In some embodiments, the dielectric constant of the dielectric material 160 is greater than the dielectric constant of the molding compound MC.

26, the chemical mechanical polishing (CMP) process at operation S399 removes the excess portion of the dielectric material 160 and exposes the conductive material 206, the conductive vias 207, and the conductive Is performed to expose the conductive features, such as the filler 2081. Accordingly, a dielectric material 160 different from the molding compound MC is filled between the vertical conductive structure 124 and the vertical conductive structure 144.

In some embodiments, the method 2100 includes operations S310 through S390 prior to operation S391 and operations S400 through S480 performed after operation S399. Operations (S310-S390 and S400-S480) in method 2100 are similar to operations in method 300 and therefore are fully described in the paragraphs above and Figures 4-20. Therefore, a detailed description thereof is omitted for the sake of simplicity.

The above example includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, substituted, reordered, and / or properly deleted depending on the spirit and scope of various embodiments of the present disclosure.

See FIG. Figure 27 is a schematic diagram illustrating another InFO package 200 including the semiconductor structure 100 of Figure 1 in accordance with various embodiments of the present disclosure. For the embodiments of FIG. 2, similar elements in FIG. 27 are designated with the same reference numerals for ease of understanding.

In contrast to the embodiments shown in FIG. 2, in the embodiments illustrated in FIG. 20, the device die 208 includes two conductive fillers 2081 and 2082, and the conductive through- (207) is disposed on the other side of the device die (208). For illustrative purposes, in embodiments, conductive through molding via 207 is electrically connected to external connector 217a through RDLs 212 and 214 to be connected to ground, and a backside redistribution layer 204 (Not shown). Accordingly, the lower electrode of the MIM structure is connected to the ground. The conductive filler 2081 is electrically connected to the positive voltage side of the finger MIM through the RDLs 212 and 214. [ In addition, the vertical conductive structures 144 are electrically connected to each other via the RDL 212. Accordingly, the top electrode of the MIM structure is connected to the device die 208 via the RDL 214 and the conductive filler 2081. The conductive filler 2082 is electrically connected to the external connector 217b through the RDLs 212 and 214 to receive an input signal to the device die 208 through the external connector 217b. Similar to the embodiment shown in Figure 2, the high-k molding compound MC is used to suppress signal noise sent from the die 208 via the conductive filler 2081 and the RDLs 214, 212, Is filled into the molding layer 209 and filled between the vertical conductive structure 124 and the vertical conductive structure 144 of the semiconductor structure 100 to form a finger type MIM capacitor structure. In some embodiments, the vertical conductive structures 124 and 144 have a square shape, a rectangular shape, any other suitable shape in cross section, or any combination thereof.

The manufacturing process of the InFO package 200 illustrated in FIG. 27 is similar to the manufacturing process of the InFO package 200 illustrated in FIG. 2, which is fully described in the above-mentioned paragraphs, and thus is omitted for the sake of simplicity.

See FIG. 28 is a schematic diagram illustrating another InFO package 200 including the semiconductor structure 100 of FIG. 1 in accordance with alternative embodiments of the present disclosure. For the embodiments of FIG. 20, similar elements in FIG. 28 are designated with the same reference numerals for ease of understanding.

In contrast to the embodiments shown in FIG. 27, in the embodiments illustrated in FIG. 28, the dielectric material 160 and the molding compound MC have different materials. The dielectric material 160 is filled between the vertical conductive structure 124 and the vertical conductive structure 144 in the semiconductor structure 100 to form an insulating structure. For example, in some embodiments, the dielectric constant (or permittivity) value of the dielectric material 160 is greater than the dielectric constant (or permittivity) of the molding compound MC. In some embodiments, the molding compound MC is applied to a molding layer outside the semiconductor structure 100 to surround the device die 208 and the molding compound MC is used in other embodiments, for example, less than about 3.9 And even a low-k value of less than about 2.5. In some embodiments, the molding compound (MC) comprises any suitable material including, for example, epoxy resin, molding underfill, and the like. Similarly, the manufacturing process of the InFO package 200 illustrated in FIG. 28 is similar to the manufacturing process of the InFO package 200 illustrated in FIG. 20, which is fully described in the above paragraphs, do.

The foregoing description outlines features of several embodiments in order to enable those skilled in the art to better understand aspects of the disclosure. Those skilled in the art will recognize that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or to achieve the same advantages as the embodiments disclosed herein . Those skilled in the art will further appreciate that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions, and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the disclosure.

Claims (20)

A semiconductor device comprising:
Device die,
A molding layer surrounding the device die,
A plurality of first vertical conductive structures formed in the molding layer,
And a plurality of second vertical electrically conductive structures formed in the molding layer,
Wherein the first vertical conductive structure and the second vertical conductive structure are entangled with each other and an insulating structure is formed between the first vertical conductive structure and the second vertical conductive structure. 2. The semiconductor device of claim 1, wherein a molding compound is applied to the molding layer to surround the device die and to form the insulation structure. 3. The semiconductor device of claim 2, wherein the molding compound comprises a polymer or silica. 2. The semiconductor device of claim 1, wherein a molding compound is applied to the molding layer to surround the device die, and a dielectric material is applied to the molding layer to form the insulation structure. 5. The semiconductor device of claim 4, wherein the dielectric material has a dielectric constant that is higher than a dielectric constant of the molding compound. 5. The semiconductor device of claim 4, wherein the dielectric material comprises polyimide or polybenzooxazole. 5. The semiconductor device of claim 4, wherein the dielectric material comprises silicon nitride or silicon dioxide. The method of claim 4, wherein the semiconductor device to the dielectric material comprises at least one of _{ZrO 2, Al 2 O 3,} HfOx, HfSiOx, ZrTiOx, TiO 2, and TaOx. The method of claim 4, wherein the dielectric material is, SrRuO ₃ -SrTiO ₃ -SrRuO ₃ structure or a semiconductor device comprises a ZrO ₂ -Al ₂ O ₃ -ZrO ₂ structure. The semiconductor device of claim 1, wherein the first vertical conductive structures are distributed in a lattice pattern, and the second vertical conductive structures are distributed in a lattice pattern. The method according to claim 1,
A first polymer layer overlying the molding layer,
A first redistribution layer overlying the first polymer layer,
A second polymer layer overlying the first redistribution layer,
Further comprising a second redistribution layer overlying the second polymer layer,
Wherein a second conductive plane is formed in the first redistribution layer and the device die and the second conductive plane are electrically connected through the second redistribution layer. In the method,
Forming a first conductive plane on the substrate;
Forming a plurality of first vertical electrically conductive structures electrically connected to the first conductive plane and to the first conductive plane;
Forming a plurality of second vertical electrically conductive structures on the substrate, wherein the first vertical electrically conductive structure and the second vertical electrically conductive structure are entangled with each other, and between the first vertical electrically conductive structure and the second vertical electrically conductive structure Forming a plurality of second vertical conductive structures, wherein an insulating structure is formed;
Attaching a device die on a substrate;
Applying a molding compound into the molding layer overlying the substrate to surround the device die,
And forming a second conductive plane on the molding layer,
Wherein the second conductive plane is electrically connected to the second vertical conductive structure. 13. The method of claim 12,
Further comprising applying the molding compound in the molding layer overlying the substrate to surround the device die, the first vertical conductive structure, and the second vertical conductive structure. 13. The method of claim 12,
Further comprising the step of applying a dielectric material between the first vertical conductive structure and the second vertical conductive structure,
Wherein the dielectric material has a higher dielectric constant than the dielectric constant of the molding compound. 13. The method of claim 12,
Forming a first polymer layer overlying the molding layer, the first polymer layer having a plurality of openings,
Further comprising forming a first redistribution layer overlying the first polymer layer to form the second conductive plane. 16. The method of claim 15,
Forming a second polymer layer overlying the first redistribution layer and having a plurality of openings,
Forming a second redistribution layer overlying the second polymer layer;
Further comprising forming a third polymer layer overlying the second redistribution layer,
Wherein the device die and the second conductive plane are electrically connected through the second redistribution layer. In the method,
Forming a capacitor structure on a package structure, the capacitor structure comprising a plurality of first vertical conductive structures, a plurality of second vertical conductive structures, and an insulating structure between the first vertical conductive structures and the second vertical conductive structures, Forming the capacitor structure, wherein the capacitor structure comprises:
Attaching a device die on the substrate;
And applying a molding compound into the molding layer lying over the substrate to surround the device die and the capacitor structure. 18. The method of claim 17, wherein the dielectric structure comprises a dielectric material having a dielectric constant that is higher than a dielectric constant of the molding compound. 18. The device of claim 17, wherein the capacitor structure further comprises: a first conductive plane electrically coupled to the first vertical conductive structure and a second conductive plane electrically coupled to the second vertical conductive structure,
The method comprises:
Forming a backside redistribution layer overlying the substrate to form the first conductive plane;
Forming a first polymer layer overlying the molding layer, the first polymer layer having a plurality of openings,
Further comprising forming a first redistribution layer overlying the first polymer layer to form a second conductive plane. 20. The method of claim 19,
Forming a second polymer layer overlying the first redistribution and having a plurality of openings,
Forming a second redistribution layer over the second polymer layer;
Further comprising forming a third polymer layer over the second redistribution layer,
Wherein the device die and the second conductive plane are electrically connected through the second redistribution layer.

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