TW201104770A - Semiconductor device and method of forming stress relief layer between die and interconnect structure - Google Patents

Abstract

A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for forming stress mitigating insulating layers between semiconductor dies and build-up interconnect structures. [Prior Art] Semiconductor components are commonly found in modern electronic products. The number and density of electrical components contained in different semiconductor components vary. A single-piece semiconductor component typically includes an electrical component 'eg, a light emitting diode emitting diode; LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field oxide transistor (metal oxide semiconductor) Field effect transistor ; M0SFET). Integral semiconductor components contain essentially hundreds to millions of electrical components. Examples of integrated semiconductor components include a microcontroller (micr〇c〇ntr〇Uer), a microprocessor, a charged-coupled device 'CCD, a solar cell (s〇iar ceu), and a digital micro Digital micro-mirror device (DMD). Semiconductor components perform a wide variety of functions, such as high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual representations of television displays. Semiconductor components are used in entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor components can also be found in military applications, aerospace, automotive, industrial controllers, and office equipment. Semiconductor components utilize the electrical properties of semiconductor materials. Semiconductor material 5 201104770, the material structure makes its electrical conductivity can be applied by electric field or via mismatch (d_g) ', force control. The doping incorporates impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor component. The semiconductor device comprises an active ((10)ive) and passive electrical:: an active structure comprising a bi-carrier and a field-effect transistor, controlling the electric force by changing the degree of doping and applying an electric field or a base current, = Current flow in the electrical body is boosted or suppressed. Passive structures, including resistors, capacitors, and inductors, establish a specific relationship between voltage and current for various electrical functions. The passive and active structures are electrically connected to one another to form a circuit that enables the semiconductor component to perform high speed calculations and other useful functions. The production of semiconductor components generally uses two complicated processes, that is, two front-end production and back-end production, each of which may contain hundreds of steps], and the production system includes semiconductor wafers (semiconductor) A plurality of dies are formed on the surface of the wafer. Each of the dies is substantially identical to each other and a circuit formed by electrically connecting the active and passive components. The back end production includes self-finishing wafer singulation of individual dies and encapsulating the dies to provide structural support and environmental isolation. The goal of semiconductor manufacturing is to produce smaller semiconductor components. Smaller components typically consume less power, are more efficient, and can be produced more efficiently. In addition, smaller semiconductor components have a smaller coverage area and are necessary for small products. The smaller grain size can be achieved by improving the front-end process to produce grains with smaller and higher density active and passive components. The back-end process can be fabricated with electrical interconnects and improvements in materials that can be used to produce semiconductor component packages with a small footprint. The electrical interconnection between the stacked semiconductor dies can be achieved via conductive through silicon vias (TSV) or through hole vias (THV) and intervening buildup interconnect layers. To form TS v or THV ', a through hole is cut through the semiconductor material or a peripheral region surrounding the semiconductor die. The perforations are then filled with an electrically conductive material, for example, by a copper deposition process. A potential mismatch between the coefficient of thermal expansion (CTE) of the semiconductor die and the fixed or dielectric buildup interconnect layer will result in a failure of the THV or TSV bond and the die from adjacent interconnect structures. The stress of layer separation. These component failures reduce yield and increase manufacturing costs. SUMMARY OF THE INVENTION There is a need for a vertical interconnect structure having a low failure rate for a stacked semiconductor device. In view of the above, in one embodiment, the present invention is a method of fabricating a semiconductor device, the step of which includes providing a temporary carrier, forming a first conductive layer on the temporary carrier, and forming a conductive pillar structure thereon. An active surface of one of the semiconductor dies is fixed to the temporary carrier on the first conductive layer and by an adhesive Uyer. The semiconductor die is vertically offset from the first conductive layer by the adhesive layer. The method further includes depositing an encapsulant on the semiconductor die and surrounding the conductive pillar structure, removing the temporary carrier and the adhesive layer, and forming a stress re-relief insulation layer (stress reHef msuUting layer) On the active surface of the semiconductor die and the surface of the encapsulant 201104770. The stress mitigation insulating layer has a first thickness on the semiconductor die and a first thickness on the encapsulant that is less than the first thickness. The method further includes forming a first interconnect structure on the stress mitigating insulating layer and forming a second interconnect structure on a second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected to each other through the conductive columnar structure. In another embodiment, the present invention is a method of fabricating a semiconductor device, the method comprising: providing a first carrier, forming a conductive pillar structure on the first carrier, securing a semiconductor component to the first carrier, Depositing an encapsulant on the semiconductor component and around the conductive pillar structure, removing the first carrier and forming a stress mitigating insulating layer on the first surface of the semiconductor component and the encapsulant. The stress mitigation insulating layer has a first thickness on the semiconductor component and a second thickness on the encapsulant that is less than the first thickness. The method further includes forming a first interconnect structure on the stress mitigation insulating layer and forming a second interconnect structure on a second surface of the encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected to each other through the conductive columnar structure. In another embodiment, the present invention is a method of fabricating a semiconductor device, the method comprising: providing a first carrier, forming a conductive pillar structure on the first carrier, securing a semiconductor component to the first carrier, Depositing an encapsulant on the semiconductor component and surrounding the conductive pillar structure, removing the first carrier, forming a stress mitigating insulating layer on the first surface of the semiconductor component and the encapsulant, and forming a first mutual The structure is on the insulating layer of the stress reduction plate. The first interconnect structure is electrically connected to the conductive pillar 8 201104770-like structure. In another embodiment, the present invention is a semiconductor component comprising a semiconductor component and a conductive pillar structure, the conductive columnar component assembly being surrounded by a material (4) on the W component. A stress mitigating insulating layer is formed on the -surface of the semiconductor component and the encapsulant. - a first interconnect structure is formed on the stress-reducing insulating layer. a second interconnect structure formed on the second surface of the encapsulant on the opposite side of the first interconnect structure. The first and second interconnect structures are electrically connected to each other through the conductive columnar structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention are described in the following with reference to the embodiments of the drawings. Although the description of the present invention presents the best mode for achieving its objectives, those skilled in the art should be able to understand the spirit and scope of the invention as defined by the scope of the patent. Equivalent structure or method, and equivalent structures or methods supported by the following disclosure and drawings. The production of semiconductor components generally utilizes two complex processes: front-end production and back-end production. Front end production involves forming a plurality of grains on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to one another to form a functional circuit. The active electrical components of the transistors and diodes have passive electrical components such as electric grids, inductors, resistors, and transformers that control the flow of current to establish the specific electrical relationships required to perform various circuit functions. 201104770 Passive and active components are formed on semiconductor wafers by a series of process steps such as s doping, deposition, photonthography, surging, jetching, and planarization (pUnarizati〇n) On the surface. The doping process incorporates impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion (113 011). The doping process modifies the conductivity of the semiconductor material in the active device, converts the semiconductor material into an insulator, a conductor, or dynamically changes the conductivity of the semiconductor material in response to an electric field or base current. The transistor contains regions of different types and doping levels depending on the desired configuration, enabling the transistor to boost or suppress the flow of current depending on the applied electric field or base current. Active and passive components are formed by a stack of materials with different electrical characteristics. The formation of such laminates can be accomplished by a variety of deposition techniques that are somewhat dependent on the type of material being deposited. For example, thin film deposition can include chemical vapor phase; redundancy (- a deposition, CVD), physical vapor deposition (physicai-Uon; PVD), electrolytic electro-mine kiss to piating, and electroless electric clock (electr0less) Plating) Process. Each of the layers is typically patterned to form an active component, a passive component, or an electrical connection between components. The laminate can be patterned using optical lithography, which involves depositing a photosensitive material such as a photoresist onto the laminate to be patterned. The pattern is transferred from light to a photoresist using a photomask. It uses a solvent to remove the light-resistant photoresist pattern portion to expose the underlying portion to be patterned. After the remaining photoresist is removed, a rounded stack is left. Alternatively, 10 201104770 The patterning of certain materials is by direct deposition of materials into regions or spaces formed by a prior deposition/etch process using techniques such as electroless and electrolytic plating. °°° $ ; redundancy - film material on the existing pattern can enlarge the underlying pattern and produce a non-uniform flat surface. It requires a uniform flat surface to create a small and structurally dense active and passive planarization process to remove material from the wafer surface and produce a -j -j flat surface. Planarization involves smoothing the surface of the wafer with a polishing pad. During the smoothing process, abrasive materials and corrosive chemicals are added to the surface of the wafer. The mechanical active combination of the abrasive material 0 actively corrodes any irregular surface irregularities to produce a uniform flat surface. The back end production involves cutting or singulating the finished wafer into individual granules, and then encapsulating the dies to provide structural support and environmental isolation. In the case of a singulated die, the wafer is scored and cut along a non-functional area on the wafer called a saw or saw wire. Wafer singulation utilizes a laser cutting tool or saw blade. After singulation, individual dies are fixed to a package substrate that includes pins or pads for interconnecting with other system components (contact pads are formed on the semiconductor dies and then Connected to the package (4), the electrical connection can be achieved by solder bumps (4) Μ hmp), & stud bumps, conductive adhesives (c〇nduetivepaste) or wire bonding (". Other molding materials are deposited on the package to provide physical support and electrical insulation. The completed package is inserted into the electrical system 'so that the function of the semiconductor (4) can be used by other system components. 201104770 Figure 1 .

The device 5 has a wafer carrier substrate or PCB' plurality of semiconductor packages mounted on its surface. Depending on the application, the electronic device 5 can have a rich, or a plurality of shaped semiconductor packages. Based on the example - 曰 曰 (5) ^ ^, the purpose, Figure 1 shows a different type of semiconductor package. The sub-device 50 can be a stand-alone system that performs four electrical functions using the semiconductor packages. Alternatively, the electronic device can be a secondary component in a larger system. For example, the electronic device 50 can be a graphics card, a network interface card, or other signal processing card that can be inserted into the computer t. The semiconductor package may comprise a microprocessor, a memory, an integrated circuit, an ASIC, a logic, a separate component, or other semiconductor die circuit (application specific circuit, analog circuit, RF circuit, or electrical component. The PCB 52 provides a common substrate for structural support and electrical interconnection with a semiconductor package mounted on the PCB. The conductive signal traces 54 are evaporated (evap〇rati〇n), electrolytically plated 'electroless' Electroplating, screen printing, or other suitable metal deposition 1 is formed on one surface or laminate of PCB 52, and signal traces M provide electrical communication between the semiconductor package, the fixed components, and other external system components. The trace 54 also provides a power and ground connection to each semiconductor package. In some embodiments, a semiconductor component has two package levels. The first level package is used to mechanically and electrically assemble the semiconductor die. To - the technique of an intermediary carrier. The second level package comprises mechanically and electrically assembling the intermediate carrier to the PCB. In other embodiments, - The semiconductor component may only have 12 201104770 with a first level package in which the die is directly fixed to the PCB in a mechanical and electrical manner. For the purposes of illustration 'many of the first level package types, including the wire bond package 56 and the overlay Flip chips 58 are all displayed on the PCB 52. In addition, a plurality of types of second level packages, including a ball grid array (BGA) 60, a bump chip carrier (BCC) 62, dual in-line package (DIP) 64, land grid array 'LGA 66, multi-chip module (MCM) 68, four sides without lead The quad flat non-leaded package (QFN) 70 and the quad nat package 72 are shown to be fixed on the PCB 52. Depending on the system requirements, any combination of semiconductor packages is configured as the first and the first Any combination of the two-level package form, as well as other electronic components, can be coupled to the pCB 52. In some embodiments, the electronic device 50 includes a single assembled semiconductor package, and:: his embodiment may A package with multiple interconnects. By combining one or more $conductors on a single-substrate, the manufacturer can add the finished component to the electronic device and system. Since the semiconductor package contains complex functions, the electronic device $- Γ, production can use lower-cost components and a mobile production line 1 The resulting device is less prone to failure and the production cost is less expensive, making the cost to consumers lower. "' page shows an exemplary semiconductor package. Figure 2a illustrates further details of DlP64:^, & F,, ^ fixed on the PCB. The semiconductor die 74 includes an active & field comprising a passive component, a conductive layer, and a 5-bit circuit formed in the die, and according to the die 13 The electrical design of 201104770 is electrically interconnected. For example, a 5H circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components formed in the active region of the semiconductor die 74. The interface is a one- or one-layer conductive material, such as Shao (A1), copper (Cu), tin ((four), town (Ni), gold (Au) or silver (Ag), which is electrically connected to the semiconductor crystal a circuit component within the granule. During the assembly of the DIP 64, the semiconductor die (4) is fixed to the glazing material by a g〇id-slilcon eutectic layer or an adhesive such as thermal epoxy. Intermediate carrier 78. The package body comprises an insulating package such as polymer or ceramic

material. Conductor lead 80 and wire bond 82 provide an electrical interconnection between semiconductor die 74 and pcB 52. Encapsulant 84 is deposited on the package for environmental protection by preventing moisture and particulates from entering the package contamination grain 74 or wire bond 82. Figure 2b illustrates further details of the bcc 62 affixed to the PCB 52. The semiconductor die 8.8 is fixed to the carrier 90 by an underfill or epoxy synthetic resin adhesive. Wire bonding 94 provides a first level package interconnect between pads 96 and 98. A molding compound or package is formed on the semiconductor die 8 8 and the wire bond 94 to provide support and electrical insulation of the component body. The pad 2 is formed on the surface of the PCB 52 by a suitable metal deposition such as electrolytic or electroless plating to prevent oxidation. The pads 102 are electrically connected to one or more conductive signal traces 54 in the PCB 52. The bumps 104 are formed between the pads 98 of the BCC 62 and the pads 1〇2 of the PCB 52. In Fig. 2c, the semiconductor die 58 is fixed to the interposer carrier 106 face down in a flip chip form first level seal 14 201104770. The active regions 108 & of the semiconductor die 58 include analog or digital circuits implemented as active components, passive components, conductive layers, and dielectric layers in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within the active region 108. The semiconductor crystal grain 58 is electrically and mechanically connected to the carrier 1〇6 via the bumps 110. Ba

The BGA 60 utilizes bumps 112 to electrically and mechanically connect to the PCB 52 in a second level package in the form of -BGA. The semiconductor die 58 is electrically connected to the conductive signal trace 54 in the PCB 52 through the bump 110, the signal line U4, and the bump m. A molding material or encapsulant 116 is deposited over the semiconductor crystal particles 58 and the carrier 1〇6 to provide support and electrical insulation of the element body. The flip-chip semiconductor component provides a very short electrical conduction path from the active components on the semiconductor die 58 to the conductive traces on the PCB 52 to reduce signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 can utilize a flip-chip first level package without electrical interposer 1 , ie, electrically and mechanically directly connected to the pcB. FIGS. 3a-3m illustrate the formation of a vertical interconnect structure. The process, the vertical interconnect structure has a conductive pillar structure and a stress mitigation layer between the semiconductor die and the build-up interconnect structure. In FIG. 3a, a sacrificial or temporary substrate or carrier 120 comprises a susceptor material such as ruthenium, polymer, polymeric composition, metal sheet, ceramic, glass, glass epoxy, beryllium oxide (berylHum oxide). , tape or other suitable low cost, strong material for structural support. A selective interface layer 122 can be formed on the carrier 12 as an etch stop layer. An electrically conductive layer 124 is formed on the carrier 120 by patterning pvD, CVD, a sputtering clock, an electrolytic clock, an electroless electrical recording, or other suitable metal deposition process. Conductive layer 124 can be a laminate of one or more layers of etch, copper, tin, gold, silver, stellite, polycrystalline, or other suitable electrically conductive material. The conductive layer i24 includes a wettable c〇ntact pad to facilitate the formation of a subsequent conductive columnar structure. In the embodiment, the wettable interface of the conductive layer i 24 is pre-charged on the carrier 120. In Fig. 3b, a plurality of electrically conductive columnar structures or rod-like structures 128 are formed on the wettable joint of the guide 124. In an embodiment, the conductive pillar structure 128 is formed by depositing one or more layers of photoresist on the interface layer 122 or the carrier 120. The photoresist portion on conductive layer 124 is exposed and removed via a button engraving process. The conductive material is deposited on the removed portion of the photoresist layer using a selective plating process. The photoresist layer is stripped leaving an individual conductive pillar structure 128. The conductive pillar structure 128 can be copper, aluminum, tungsten (W), gold, solder or other suitable electrically conductive material. The conductive columnar structure 128 has a height range of 2_12 〇 micrometers ("m). In another embodiment, the conductive pillar structures 128 may be formed as stud bumps or stacked bumps. A plurality of semiconductor dies or components 130 are secured to the interface layer 122 in a flip chip configuration via a protective adhesion layer 132. The pads 134 and the active surface 136 are located face down on the interface layer 122 and the carrier 120. The protective adhesive layer 132 can be one or more layers of ultraviolet (UV) curable and heat stable adhesive tape. The protective adhesive layer 132 establishes a vertical offset between the active surface 136 and the conductive layer 124. 201104770

The semiconductor die 130 includes an active surface i36 including an analog or digital circuit implemented as an active device, a passive component, a conductive layer, and a dielectric layer formed within the die and based on electrical design and function of the die Electrically interconnected with each other. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in active surface 136 to implement a baseband analog circuit or digital circuit, such as a digita signal processor (DSP). ), ASIC, memory or other signal processing circuit. The semiconductor die 130 may also include an IPD (integrated passive device) such as an inductor, a capacitor, and a resistor for RF signal processing. In another embodiment, a separate semiconductor component can be attached to the interface layer 122 or the carrier 12. The conductive pillar structure 128 is disposed around the semiconductor die 130. Figure 3d shows an encapsulant or molding material 丨38 using paste printing, compressive muffing, transfer molding, liquid encapsulation (Hquid molding), Vacuum lamination (vacuum ianiinati〇n), or other suitable coating mechanism is deposited on the semiconductor die 13 and the conductive columnar structure 28. The encapsulant 138 may be a polymer composite material such as an epoxy resin having a fuier, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant us is non-conductive and environmentally protects the semiconductor components from external components and contamination. The protective adhesive layer 32 prevents the encapsulant 138 from flowing into the active surface 136. In FIG. 3e, the carrier 120, the interface layer 122, and the protective adhesive layer 132 17 201104770 are subjected to chemical wet etching, plasma dry etching, mechanical peel-off. , CMP, mechanical grinding, thermal bake, laser scanning or wet stripping are removed. After the carrier 120 is removed, the encapsulant 38 provides structural support to the semiconductor die 13 (with the removal of the carrier 120, the interface layer 122, and the protective adhesive layer 132, the conductive layer 124 and the semiconductor die 130) The pad 134 is exposed. In Figure 3f, the above structure is inverted and a stress relief insulating layer 140 is utilized by PVD, CVD, printing, spin coating, spray coating (spray c 〇 ating, sintedng, or thermal oxidation is formed on the encapsulant 138, the conductive layer 124, and the active surface 136. The stress mitigating insulating layer 上述4〇 may be one or more layers of cerium oxide ( Si02), tantalum nitride (Si3N4), niobium oxynitride (Si〇N), niobium oxide (Ta2〇5), aluminum oxide (A1303), or other laminates having materials having similar insulating and structural properties. Due to the vertical offset of the protective adhesive layer 132, the insulating layer 14 is thicker on the active region 136 than on the encapsulant 138 and the conductive layer 146 to provide additional stress relief for the semiconductor die 130. In one embodiment The insulating layer 140 is on the active region 136 The thickness of the sub-layer is 5-1 〇〇 / / m, and the thickness of the insulating layer 14 〇 on the encapsulant i 3 8 is 2-5 〇 # m. - The partial insulating layer 140 is patterned The etching and etching processes are removed to expose the conductive layer 124 and the pads 134, as shown in FIG. 3g. In FIG. 3h, a bottom side build-up interconnect structure i42 is formed on the insulating layer 1 々ο is 201104770 The layer 144 is formed on the insulating layer 14G, the conductive layer 124, and the pad 134 by patterning with PVD, CVD, sputtering, 弋-key electroless electrowinning, or other suitable metal deposition process.疋—or a multilayer of layers consisting of conductive, copper, tin, gold, silver, or other electrically conductive materials of the field. Part of the conductive I(4) is electrically connected to the conductive columnar structure 128, the conductive layer 124, and the pads. The other portions of conductive layer 144 may be electrically or electrically insulated from one another, depending on the design and function of the semiconductor component. For example, portion 145 of conductive layer 144 is charged with a redistribution layer hya; RDL) or chute ( rUnner) to extend the conductivity of the conductive columnar structure 128 and the conductive layer 124. In the figure, an insulating or passivation layer i46 is formed over the insulating layer 140 and the conductive layer 144 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. Layer 146 can be one or more layers of SiO 2 , Si 3 N 4 , SiON, Ta 205, Al 2 〇 3, or other materials having similar insulating and structural properties. A portion of passivation layer 146 is removed by an etch process to expose conductive layer 丨44. An electrically conductive layer 148 is formed over passivation layer 146 and conductive layer 144 by patterning, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 148 can be one or more layers of aluminum, copper, tin, nickel, gold, silver or other suitable electrically conductive material. The conductive layer 148 is electrically connected to the conductive layer 144. The conductive layer 148 is an under bump metallization (UBM) that is in electrical contact with the conductive layer 144 and the conductive pillar structure 128. UBM 148 can be a multiple metal stack with an adhesive layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed on the conductive layer 144 and may be composed of titanium (Ti), titanium nitride (TiN), titanium tungsten (Tiw), aluminum or chromium (Cr). The barrier layer is formed on the adhesive layer and may be composed of nickel, nickel vanadium (NiV), platinum (Pt), palladium (Pd), titanium tungsten or chromium copper (CrCu). The barrier layer prevents copper from diffusing into the active regions of the die. The seed layer (μμ layer) may be copper, nickel, nickel vanadium, gold or aluminum. The seed layer is formed over the barrier layer and acts as an intermediate conductive layer between the conductive layer 144 and subsequent solder bumps or other interconnect structures. UBM 148 provides a low resistance connection to conductive layer 144, as well as a seed layer for solder diffusion barrier and solder wettability. In Figure 3j, encapsulant 138 is subjected to grinding or plasma etching to planarize its surface for the formation of a top build-up interconnect structure. This polishing action exposes one surface of the conductive columnar structure 128. A selective process carrier 15, such as a backgrinding tape, can be secured to the purification layer 146 and the conductive layer 148 through the adhesive layer 152 to increase structural support during the lapping action. In Figure 3k, the structure is inverted and a top build-up interconnect structure 154 is formed over encapsulant 138 and conductive pillar structure 128. An insulating or passivation layer 156 is formed over encapsulant 138 and conductive pillar structure 128 by pvd, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. The purification layer 156 may be one or more layers of SiO 2 , Si 3 N 4 , SiON, Ta 2 〇 5, A 12 〇 3 or other materials having similar insulating and structural properties. A portion of the passivation layer 156 is removed by an etching process. The conductive columnar structure 128 is exposed. An electrically conductive layer 158 is formed over the purification layer 156 and the conductive pillar structure 128 by patterning in conjunction with PVD, CVD, sputtering, 20201104770, '^ electroless electrical recording, or other suitable metal deposition process. Conductive layer 158 can be one or more layers of lamination, copper, tin, gold, silver, or other suitable electrically conductive material f. A portion of the conductive layer 158 is electrically connected to the conductive pillar structure 128. Other portions of conductive layer 158 may be electrically or electrically insulated from one another, depending on the design and function of the semiconductor component. For example, portion 159 of conductive layer 158 acts as an RDL or chute to extend the conductivity of conductive pillar structure 128. In Fig. 31, an insulating or passivation layer 160 is formed over the passivation layer and conductive layer 158 by PVD, CVD, P-brush spin coating, spray coating, sintering or thermal oxidation. The passivation layer "Ο" may be one or more layers of Si 2 , S 3 N 4 , SiO 2 , Ta 2 〇 5, Al 2 〇 3 or other materials having similar insulating and "structural properties". A portion of the passivation layer 1 60 is removed by an etching process to expose the conductive layer 158. The electrically conductive layer 162 is formed over the passivation layer 160 and the conductive layer 158 by patterning pvd, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 162 can be - or a plurality of layers of aluminum, copper, tin, nickel, gold, silver or other suitable electrically conductive material. Conductive layer 162 is a UBM that is in electrical contact with conductive layer 158 and conductive dendritic structure 128. UBM 162 can be a multiple metal stack with an adhesive layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed over the conductive layer 158 and may be composed of titanium, titanium nitride, titanium tungsten, aluminum, or chromium. The barrier layer is formed over the adhesive layer and may be composed of nickel, nickel vanadium, platinum, palladium, titanium tungsten or chromium copper. The barrier layer prevents the copper from expanding into the active region of the die. The f-seed layer may be copper, nickel, nickel vanadium, gold or the like. The seed layer is formed on the barrier layer and acts as a conductive

Layer 158 and subsequent solder bumps or other interconnected conductive layers. UBM 162 provides a low resistance connection to conductive layer 158, as well as a seed layer for solder diffusion barrier and solder wettability. In the figure, the carrier 150 and the adhesive layer 152 are removed by chemical wet etching, electric dry etching, mechanical stripping, CMp, mechanical grinding, hot chess, laser scanning or wet stripping. The bottom side build-up layer (4) includes a conductive layer 144, a passivation layer 146, and a UBM 148i portion build-up interconnect structure 154 including a passivation layer 156, a conductive layer 158, a purification layer 16A, and (10) μ 162 ° - conductive bump material utilization. Evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes are deposited on top of UBM 148. The bump material may be aluminum 'tin, nickel, gold, silver 'palladium (pb)' 铋, copper, solder, and combinations of the foregoing, plus a selective (iv) agent. For example, S, the bump material can be eutectic tin/palladium, high lead solder or lead free solder. The bump material is bonded to the crucible 148 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed (10) lQw by heating the material above its melting point to form spherical solder balls or bumps 164. In some applications, the bumps 1 64 are reflowed a second time to enhance the electrical contact bumps with the UBM 148 and may also be bonded to the UBM 148. Bump 164 represents an interconnect structure type that can be formed on UBM 148. The interconnect structure can also use wiring, conductive paste, stud bumps, micro bumps, or other electrical connections. 22 201104770 The semiconductor die 130 is singulated into individual semiconductor components 168 by saw blades or laser cutting tools. After singulation, individual semiconductor components 168 can be stacked as shown in FIG. The conductive pillar structure 128 provides a vertical z-direction interconnect between the top side build up interconnect layer 154 and the bottom side build up interconnect layer 142. The conductive layer 158 is electrically connected to the conductive layer 124 and the pads 134 of each of the semiconductor elements 168 via the conductive pillar structures 128. The thick protective insulating layer disposed on the active surface 136 reduces the stress generated by the CTE mismatch between the semiconductor die 130 and the bottom side buildup interconnect structure 42. The stress buffer provided by the insulating layer 140 reduces the junction failure rate of the conductive pillar structure 138 and the lamination separation between the semiconductor die 13A and the build-up interconnect structure 142. Figure 5 shows a variation of the diagram process flow. Encapsulant 13 8 and conductive pillar structure 128 are subjected to grinding or plasma etching to planarize the surface of the encapsulant to facilitate formation of topside build-up interconnect layer 154. This polishing action exposes the backside surface of the semiconductor die 13G which is coplanar with the exposed surface of the conductive pillars 128. The remainder of this process is illustrated in Figures 3k-3m. Figure 6 illustrates an embodiment of a vertical interconnect structure having no plurality of IpDs formed in the topside interconnect structure. Similar to the process illustrated in Figures 3a-3m, semiconductor component 17 (M吏 uses a sacrificial or temporary substrate or carrier with a selective interface layer)

Body, its system is used as a locust to soften | temperature «Β. ί L,, stop layer. An electrically conductive layer 丨72 is formed on the carrier by patterning with PVD, CVD, etch, 贱 plating, electrolytic plating, electroless plating, or other suitable metal deposition process. 1 1 A stack of materials such as tin, nickel, gold, silver, tungsten, polycrystalline germanium or other suitable electrical conductors. The conductive layer 172 comprises a wet cell joint to facilitate the formation of a subsequent conductive columnar structure. A plurality of conductive pillar structures or rod structures 178 are formed on the wettable pads of the conductive layer 172. In one embodiment, the conductive columnar structure 78 is formed by depositing one or more layers of photoresist on the carrier and the interface layer. The photoresist portion on conductive layer 172 is exposed and removed via an etch developing process. The conductive material is deposited on the removed portion of the photoresist layer using a selective electroplating process. The photoresist layer is stripped leaving a separate conductive pillar structure 178. The electrically conductive columnar structure 178 can be copper, aluminum, tungsten, gold, solder or other suitable electrically conductive material. The electrically conductive columnar structure 178 has a height range of 2_12 〇 M . In another embodiment, the conductive pillar structure 78 may be formed as a stud bump or a stacked bump. A plurality of semiconductor dies or components 18 〇 are fixed to the interface layer in a flip chip configuration via a protective adhesion layer, and the pads 184 and the active surface 186 are oriented downwardly on the interface layer and the carrier. The protective adhesive layer can be one or more layers of curable and heat stable adhesive tape. The protective adhesive layer creates a vertical offset between the active surface 186 and the conductive layer 172. The semiconductor die 18 〇 includes an active surface 186 including an analog or digital circuit implemented as an active device, a passive component, a conductive layer, and a dielectric layer, and is formed within the die according to electrical design and function of the die Electrically interconnected with each other. For example, the continuation circuit can include one or more transistors, diodes, and other circuit components formed in the active surface 186 to implement a base frequency analog circuit or digital circuit, such as a DSP, ASIC, memory, or other signal processing circuit. . Semiconductor die 180 may also include an IPD, such as inductors, capacitors, and resistors for RF signal processing. In another embodiment, a separate semiconductor component can be bonded to the interface layer or carrier. Encapsulant or molding material outer bucket 18 transfer molding, liquid sealing (4) (four) sealing 'mechanism deposition on semiconductor 曰 vacuum lamination or other suitable coating 1QQ conductor day granule 180 and conductive column structure 178. The enchantment agent 188 may be a material of the armor of the person, such as an epoxy synthetic tree sapphire with a filler, a ruthenium-filled ruthenium, a oxyacrylate of a filler, or an appropriate filling. The polymer of the backing 1. The encapsulant is electrically conductive and can protect the environment from external influences and contamination. The tantalum carrier and the protective adhesive layer are removed by chemical wet button etching, electroless dry etching, mechanical stripping, CMP, mechanical grinding, thermal baking, laser sweeping or wet stripping. After the carrier is removed, the package 188 provides: structural support to the semiconductor die 180. The pad i 84 of the conductive layer 172 and the semiconductor die i 8 is removed as the carrier and the interface layer are removed. The structure is inverted and an insulating layer 19 is formed over the encapsulant 188, the conductive layer 172 and the active surface 186. Due to the vertical offset of the protective adhesive layer, the insulating layer 190 is in the active region! 86 on the encapsulant i 88 and conductive layer! u is thicker. A portion of the insulating layer 19 is removed by a patterning and etching process to expose the conductive layer 172 and the pads 184». A bottom side build-up interconnect structure 192 is formed over the insulating layer 19A. The bottom side buildup interconnect structure 192 includes a conductive layer 194, an insulating or passivation layer ι96, and a UBM 198. The encapsulant 188 is subjected to grinding or plasma etching for surface planarization to facilitate the formation of a top build-up interconnect structure. The polishing action exposes the top surface of the conductive pillar structure 178 and 'selectively, the backside of the semiconductor die 18 2011 25 201104770 side surface as illustrated in FIG. - A selective process carrier can be applied to the purification layer 196 and the conductive layer 198 to increase structural support during the polishing action. The structure is inverted and a top build-up interconnect structure 2 is formed over the encapsulant 188 and the conductive pillar structure 178. The build-up interconnect structure 2〇〇 contains one or more IPDs. An insulating or passivation layer 2〇2 is formed over encapsulant 188 and conductive pillar structure 178 by spin coating, pvD, C VD printing sintering or thermal oxidation. The passivation layer 202 may be one or more layers of Si〇2, Si3N4,

A laminate of SiON, Ta2〇5, Abo:) or other material having suitable insulating properties. A portion of the passivation layer 202 is removed to expose the conductive pillar structure 178 °. An electrically conductive layer 204 is formed by patterning a PVD, CVD, sputtering 'electrolytic plating' electroless plating process, or other suitable metal deposition process. Above the insulating layer 202 to form individual portions or blocks. Individual portions of conductive layer 204 may be electrically or electrically insulated from one another, depending on the connection of individual semiconductor dies. Conductive layer 204 can be a laminate of one or more layers of aluminum, copper, tin, nickel, gold, silver, or other suitable electrically conductive material. A portion of the conductive layer 204 is electrically connected to the conductive pillar structure 1 78. Other portions of conductive layer 204 may be electrically or electrically insulated from one another, depending on the design and function of the semiconductor component. A resistive layer 206a-206b is separately patterned and deposited on the conductive layer 2〇4 and the insulating layer 2〇2 by PVD or CVD. Resistance layer 2〇6 is a tantalum silicide; TaxSiy or other metal telluride, nitride button (TaN), nickel chromium (NiCr), nitrided (TiN) or sunset stone mixed with impurities Xi's resistivity is between 5 and loo 〇hm/sq. A rim 26 201104770 The edge layer 208 is formed over the resistive layer 206a by PVD, CVD, printing, sintering or thermal oxidation. The insulating layer 208 may be one or more layers of Si3N4, SiO2, SiON, Ta205, ZnO, ZrO2, Al2〇3, polyimide, BCB, PBO or other suitable dielectric materials. The resistive layer 206 and the insulating layer 208 may be formed in the same mask and simultaneously engraved. Alternatively, the resistive layer 206 and the insulating layer 208 can be patterned and etched with different masks. An insulating or passivation layer 210 is formed over the passivation layer 202, the conductive layer 204, the resistive layer 206, and the insulating layer 208 by spin coating, pvd, CVD, printing, sintering, or thermal oxidation. The passivation layer 210 may be one or more layers of Si 2 , Si 3% ' SiON, TaW 5 , AhO 3 or other materials having suitable insulating properties. A portion of the passivation layer 21 is removed to expose the conductive layer 204, the resistive layer 206, and the insulating layer 208. An electrically conductive layer 212 is patterned and deposited on the purification layer 21, the conductive layer, and the resistive layer by PVD, CVD, sputtering, electrolytic plating, & electroplating, or other suitable metal deposition process. Above the insulating layer _, in %, a part or section of j and further interconnectivity. Individual portions of conductive layer 212 may be electrically or electrically insulated from one another, depending on the connectivity of the individual semiconductor dies. The conductive layer 2^2 may be - or a plurality of layers of laminates of indium, copper, tin, nickel, gold, silver or other suitable electrically conductive material. Insult

An insulating or passivation layer 214 is formed on the conductive layer 212 and the blunt U layer by spin coating, PVD, CVD, print sintering or thermal oxidation - which may be - or multilayered by Si3N4, T2, U2, A = 27 201104770 or A laminate of other materials having suitable insulating properties. A portion of the purification layer 214 is removed to expose the conductive layer 212. Electrogenerated twin conductive layer 216 is patterned and deposited over passivation layer 214 and conductive layer 212 using pVD, c, bond, electrolytic plating, electroless clock process, or other suitable metal deposition process. Conductive layer 216 can be one or more layers of aluminum, copper, tin, nickel, gold, silver or other suitable electrically conductive material. The conductive layer 216 is a UBM that is in electrical contact with the conductive layers 212 and 2〇4 and the conductive pillar structure 178. The structures described in the build-up interconnect structure 2 constitute one or more passive circuit components or IPDs. In one embodiment, the conductive layer 2〇4, the resistive layer 206a, the insulating layer 208, and the conductive layer 212 are a metal-insulator-metal (MIM) capacitor. The resistive layer 206b is in the passive circuit. A resistance member. Individual sections of conductive layer 2 1 2 may be wound or wound into a coil on a plane to create or exhibit the properties of an inductor. The above IPD architecture provides such as a resonator (res〇nat〇r), a high-pass filter, an i〇w-pass filter, and a band-pass filter. Electrical characteristics required for high frequency applications such as symmetric Hi-Q resonant transformers, matching networks, and tuning capacitors. These IPDs can act as front-end wireless RF components that can be placed between an antenna and a transceiver. The inductor can be a hi-Q bal (balun; balun) 'transformer or coil, operating at up to 100 GHz (Gigahertz; 1 billion megahertz). In some applications, 28 201104770 夕 楞 楞 is formed on the same substrate, making it possible to operate in multiple bands. For example, two or more Bessie are used in a mobile phone or other global system (GSM) communication to be responsible for the four bands, each dedicated to the operation of one of the four band devices. A typical RF system requires multiple lpDs and other high frequency circuits in one or more semiconductor packages to perform the required electrical functions. The IPD such as δHai may be formed in one or both of the top side buildup bonding structure and the bottom side buildup interconnect structure. The selective carrier and adhesion layers on passivation layer 196 and UBM 198 are removed by chemical wet etching, plasma dry etching, mechanical stripping, CMp, mechanical grinding, heat supply, laser scanning or wet stripping. A conductive bump material is deposited on the UBM 198 by evaporation, electrolytic plating, electroless plating, solder ball implantation, or a screen printing process. The bump material can be aluminum, tin, nickel, gold, silver, palladium, rhodium, copper, solder, and combinations of the foregoing, plus a selective flux. For example, the bump material can be eutectic tin/palladium, lead solder or lead-free solder. The bump material is bonded to the UBM 198 using a suitable adhesive or bonding gas path. In one embodiment, the bump material is heated to above its melting point to form a spherical tin ball or bump 218. In one or two applications, the bumps 2 18 are reflowed a second time to enhance electrical contact with the ubm 198. The bumps can also be crimped to the UBM 198. Bumps 218 represent an interconnect structure that can be formed on UBM 198. The interconnect structure can also utilize wiring, conductive paste, stud bumps, microbumps, or other electrical connections. The conductive pillar structure 178 provides a vertical z-direction interconnect between the top build-up interconnect layer 2 and the bottom germanium interconnect layer 192. The conductive layers 2〇4 and 2丨2 are electrically connected to the conductive layer 172 and the pads 184 of the semiconductor die 18〇 via the 29 201104770 conductive pillar structure 178. The thick protective insulating layer 190 disposed on the active surface 186 is reduced by the semiconductor die 180 and the bottom side build-up interconnect structure 192. Then the four stresses are generated. Insulation | The stress buffer provided by i 9G reduces the junction failure rate of the conductive pillar structure 178 and the lamination separation between the semiconductor die 18 〇 and the build-up interconnect structure 192. Although one or more embodiments of the invention are described in detail above, it is to be understood that the embodiments may be modified and modified without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates a PCB with a different type of package secured to its surface. Figure 2a-2c shows further details of a representative semiconductor attached to the upper 31pCB; Figure 3a-3m illustrates the use of The process of forming a vertical interconnect structure between the conductive pillar structure and the stress mitigation layer between the die and the build-up interconnect structure. Figure 4 illustrates the electrical interconnection with the conductive pillar structure. 5 illustrates a back side surface of a half grain coplanar with one surface of the conductive columnar structure; and an element FIG. 6 illustrates a semiconductor having an IPD formed in a top side interconnect structure. [Main Component Symbol Description 50 Electronic Device 30 201104770 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 88 90 92 94 96 98

PCB trace wire bond package flip chip ball grid array bump wafer carrier double row package substrate grid array multi-chip module four-sided leadless flat package four-sided flat package semiconductor die pad interposer carrier conductor wire bonding encapsulant Semiconductor die carrier underfill or epoxy synthetic resin adhesive material wire bond pad gasket molding material or encapsulant 31 100 201104770 102 pad 104 bump 106 carrier 108 active region 110 solder bump or solder ball 112 solder bump Or solder ball 114 signal line 116 molding material or encapsulant 120 carrier 122 interface layer 124 conductive layer 128 conductive pillar structure 130 semiconductor die or component 132 protective adhesive layer 134 pad 136 active surface 138 encapsulant or molding material 140 insulating layer 142 bottom side build-up interconnect structure 144 conductive layer 145 portion of conductive layer 146 insulating or passivation layer 148 conductive layer 150 carrier 32 201104770 152 adhesive layer 154 top side build-up interconnect structure 156 insulating or passivation layer 158 conductive layer 159 part of the conductive layer 160 insulation or passivation layer 162 conductive 164 bump 168 semiconductor component 170 semiconductor component 172 conductive layer 178 conductive pillar structure 180 semiconductor die or component 184 pad 186 active surface 188 encapsulant or molding material 190 insulating layer 192 bottom side build-up interconnect structure 194 conductive layer 196 Insulation or passivation layer 198 UBM 200 Top side buildup interconnect structure 202 Insulation or passivation layer 204 Conductive layer 33 201104770 206a, b Resistive layer 208 Insulation layer 210 Insulation or passivation layer 212 Conductive layer 214 Insulation or passivation layer 216 Conductive layer 34

Claims (1)

201104770 VII. Patent application scope: 1. A method for manufacturing a semiconductor component, comprising: providing a temporary carrier; forming a first conductive layer on the temporary carrier; forming a conductive columnar structure on the first conductive layer ; : + conductor day - the active surface is fixed to the: carrier by an adhesive layer, the semiconductor die is vertically offset from the first -ZM-, a. Encapsulating agent on the semiconductor die and around the conductive germanium structure; removing the temporary carrier and the adhesive layer; forming a stress mitigating insulating layer on the active surface of the semiconductor die and On the surface of the master, the stress relief insulating layer has a first ig rip degree on the semiconductor die and a second thickness on the encapsulant that is smaller than the first thickness; Connecting the structure to the stress mitigation insulating layer; and forming a second interconnect structure on the first surface of the encapsulant opposite the first interconnect structure, the first and second interconnect structures passing through the conductive pillar shape Configuration is electrically connected to each other. The method of claim 1, wherein the second interconnection structure comprises - a light human 4; a wood & S-type passive component is electrically connected to the conductive columnar structure. *8 3. The method of claim 1, wherein the method further comprises removing - X encapsulant to form a flat surface for the first interconnect structure. The method of claim 3, wherein the back side surface of one of the semiconductor grains on the opposite side of the active surface of the semiconductor die is coplanar with a surface of the conductive pillar structure. 5. The method of claim 1, further comprising: stacking the plurality of semiconductor components; and electrically connecting the plurality of semiconductor components via the conductive pillar structure. 6. A method of fabricating a semiconductor device, comprising: providing a first carrier; forming a conductive pillar structure on the first carrier; securing a semiconductor component to the first carrier; depositing an encapsulant on the semiconductor component And surrounding the conductive pillar structure; removing the first carrier; forming a stress mitigating insulating layer on the first surface of the semiconductor component and the encapsulant, the stress mitigating insulating layer has a first portion on the semiconductor component a thickness 'and a second thickness on the encapsulant that is less than the first thickness; forming a first interconnect structure on the stress mitigation insulating layer; and forming a second interconnect structure on the first interconnect On one of the second surfaces of the encapsulant opposite the structure, the first and second interconnect structures are electrically connected to each other through the conductive pillar structure. 7. The method of claim 6, wherein the second interconnect structure comprises an integrated passive component electrically connected to the conductive braid structure 0 36 201104770 8. As described in claim 6 The method further includes removing a 4 knives of encapsulant to form a flat surface for the first interconnect structure. 9. The method of claim 6, further comprising securing a second carrier to the first interconnect structure prior to forming the first interconnect structure. 10. The method of claim 6, further comprising: stacking the plurality of semiconductor components; and electrically connecting the plurality of semiconductor components via the conductive pillar structure. The method of claim 6, wherein the forming the first interconnect structure comprises: forming a first conductive layer on the stress mitigation insulating layer, the first conductive layer being electrically connected to the conductive column Forming a first insulating layer on the stress mitigation insulating layer and the first conductive layer; and forming a second conductive layer on the first conductive layer, the second conductive layer being electrically connected to the conductive ridge structure. 12. A method of fabricating a semiconductor device, comprising: providing a first carrier; forming a conductive pillar structure to fix the first semiconductor component to the first carrier; depositing an encapsulant on the semiconductor component; The conductive germanium structure circumferentially removes the first carrier; forming a stress mitigating insulating layer on the first surface of the semiconductor component and the encapsulant 37 201104770; and forming a first interconnect structure on the stress mitigating insulating layer The first interconnect structure is electrically connected to the conductive pillar structure. 1. The method of claim 12, further comprising forming a first interconnect structure on the second surface of one of the encapsulants on the opposite side of the first interconnect structure, the first and second interconnects The structures are electrically connected to each other through the conductive columnar structure. 14. The method of claim 13 wherein the second interconnect structure comprises an integrated passive component electrically coupled to the conductive pillar structure. 15. The method of claim 12, wherein the semiconductor component is vertically offset from the first conductive layer. The method of claim 2, wherein the stress mitigation insulating layer has a first thickness on the semiconductor component and has a second less than the first thickness on the encapsulant thickness. 17. The method of claim 12, further comprising removing a portion of the encapsulant to form a planar surface for the first interconnect structure. 18. The method of claim 12, further comprising securing a carrier to the first structure prior to forming the distal-interconnect structure. The method of claim 12, further comprising: stacking a plurality of the semiconductor elements; and electrically connecting the plurality of semiconductor elements by the conductive columnar structure. The method of claim 12, wherein the forming the 38 201104770 first interconnect structure comprises: forming a first conductive layer on the stress mitigation insulating layer, the first conductive layer being electrically connected to a conductive columnar structure; forming a first insulating layer on the stress mitigating insulating layer and the first conductive layer; and forming a second conductive layer on the first conductive layer, the second conductive layer is electrically connected to The conductive columnar structure. A semiconductor device comprising: a semiconductor component; a conductive pillar structure formed around the semiconductor component; an encapsulant 'deposited on the semiconductor component and around the conductive pillar structure, a stress mitigating insulating layer, Formed on the first surface of the semiconductor component and the encapsulant; a first interconnect structure formed on the stress mitigation insulating layer; and a first interconnect structure formed on the opposite side of the first interconnect structure On one of the second surfaces of the encapsulant, the first and second interconnect structures are electrically connected to each other through the conductive pillar structure. 22. The semiconductor device of claim 21, wherein the stress mitigation insulating layer has a first thickness on the semiconductor component and a second thickness on the encapsulant that is less than the first thickness. 23. The semiconductor component of claim 21, wherein the second interconnected junction comprises an integrated passive component electrically coupled to the electrically conductive pillar structure. 39 201104770 24. The semiconductor device of claim 21, further comprising a plurality of the semiconductor elements electrically connected to each other via the conductive columnar structure. 25. The semiconductor device of claim n, wherein the first interconnect structure comprises: a first conductive layer formed on the stress mitigation insulating layer, the first conductive layer being electrically connected to the conductive a columnar structure; a first insulating layer formed on the stress mitigating insulating layer and the electric layer; and a second conductive layer formed on the first conductive layer, the second conductive layer electrically connected to the Conductive columnar structure. Eight, schema: (such as the next page)