CN105810662B - 半导体封装结构及形成方法 - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
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- 239000010703 silicon Substances 0.000 claims abstract description 25
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Abstract
本发明公开了一种半导体封装结构及形成方法。该半导体封装结构包括:基板、硅通孔内连线结构、第一和第二保护环掺杂区域;其中该基板具有前侧和后侧,而该硅通孔内连线结构形成于该基板中,而该第一和第二保护环掺杂区域也形成于该基板中并且相邻于该硅通孔内连线结构,同时耦接至地。本发明实施例,基板或者硅通孔内连线结构产生的噪音可以经由第一和第二保护环掺杂区域而耦接至地,从而有效地降低噪音。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种具有TSV(through silicon via,硅通孔)内连线结构的半导体封装结构及形成方法。
背景技术
对于电子工程领域而言,TSV为一种完全穿过硅晶圆或硅芯片的垂直电子连线。相较于例如POP(package-on-package,叠层封装)等其他半导体结构,TSV是由高性能的制造技术所制成。使用TSV来创建3D(三维)半导体封装和3D集成电路。相较于其他半导体封装,TSV之通孔(via)的密度实质上大于其他半导体封装,并且具有较短的连接长度。
传统TSV的绝缘衬垫(liner)作为硅晶圆和TSV通孔插塞之间的电容。在高速应用(例如:射频应用)中,传统TSV的电阻抗因为绝缘衬垫而降低。当高速电路(例如:数字电路)传递信号时,这些信号会从高速电路耦合至其他节点,例如模拟电路中之多个TSV。因此,产生噪音耦合(noise coupling)并干扰其他敏感电路(例如模拟电路),影响需要高时钟频率(clock rate)和模拟精确度(analog precision)的半导体封装之整体性能表现。
因此,亟需一种用于具有TSV内连线的半导体封装的新颖噪音耦合抑制结构。
发明内容
有鉴于此,本发明实施例提供了一种半导体封装结构及形成方法,可有效地抑制噪音耦合。
本发明提供了一种半导体封装结构,包括:基板,具有前侧和后侧;硅通孔内连线结构,形成于该基板中;以及第一保护环掺杂区域和第二保护环掺杂区域,形成于该基板中,其中该第一和第二保护环掺杂区域相邻该硅通孔内连线结构,并且均耦接至地。
其中,该第一和第二保护环掺杂区域具有不同的导电类型。
其中,该半导体封装结构还包括:第三保护环掺杂区域,形成于该基板中,并且相邻于该第二保护环掺杂区域。
其中,该半导体封装结构还包括:第四保护环掺杂区域,形成于该基板中,并且相邻于该第三保护环掺杂区域。
其中,该第一保护环掺杂区域为n型保护环掺杂区域,该第二保护环掺杂区域为p型保护环掺杂区域。
其中,该n型保护环掺杂区域包括位于n井区域中的n型重掺杂区域;以及/或,该p型保护环掺杂区域包括位于p井区域中的p型重掺杂区域。
其中,该硅通孔内连线结构包括:导电材料;绝缘层,围绕该导电材料;
导电凸块,形成于该基板的该后侧上,其中该导电凸块直接形成于该导电材料上;以及多晶硅图案,形成于该基板的该前侧上,其中该多晶硅图案直接形成于该导电材料上。
其中,该半导体封装结构还包括:井区域,形成于该基板中,并且该井区域与该第二保护环掺杂区域之间的区域为未掺杂区域。
本发明实施例还提供了一种半导体封装结构的形成方法,包括:提供具有前侧和后侧的基板;于该基板中形成第一保护环掺杂区域和第二保护环掺杂区域,并将该第一和第二保护环掺杂区域耦接至地;形成从该基板的后侧穿过该基板的沟槽;形成衬垫于该基板的该后侧、该沟槽的底表面和侧壁的绝缘层;移除位于该基板的该后侧上的绝缘层,以形成通孔;以及于该通孔中形成导电材料,从而由该绝缘层和该导电材料形成硅通孔内连线结构。
其中,该方法还包括:于该基板的该后侧及该导电材料上形成导电凸块;于该基板的该前侧上形成多晶硅图案。
其中,该第一和第二保护环掺杂区域具有不同的导电类型。
其中,该方法还包括:于该基板中形成井区域,该井区域与该第二保护环掺杂区域之间的区域为未掺杂区域。
其中,该方法还包括:形成相邻该第二保护环掺杂区域的第三保护环掺杂区域;以及形成相邻该第三保护环掺杂区域的第四保护环掺杂区域,其中该第三保护环掺杂区域的导电类型不同于该第四保护环掺杂区域的导电类型。
其中,该于基板中形成第一保护环掺杂区域和第二保护环掺杂区域,包括:于该基板中形成n型保护环掺杂区域;以及于该基板中形成p型保护环掺杂区域;其中,该n型保护环掺杂区域包括位于n井区域中的n型重掺杂区域;该p型保护环掺杂区域包括位于p井区域中的p型重掺杂区域。
本发明实施例的有益效果是:
上述半导体封装结构及形成方法,在基板中,具有至少两个耦接至地的保护环掺杂区域,因此来自于基板或TSV结构的噪音可通过该至少两个保护环掺杂区域而耦合至地,从而有效地降低噪音。
附图说明
图1为根据本发明一些实施例的半导体封装结构的横截面示意图;
图2A~2D为根据本发明一些实施例的用于显示形成半导体封装结构之各工艺的横截面示意图;
图3为根据本发明一些实施例的半导体封装结构的横截面示意图;
图4为根据本发明一些实施例的半导体封装结构的横截面示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
以下内容中提供了许多不同的实施例或范例,以描述本发明的半导体封装结构及形成方法的不同特征。以下中,通过描述构件和排列方式的特定范例来简化描述。当然,这些特定的范例仅作为示例而并非用以限定本发明。举例来说,下文中,当叙述第一特征形成于第二特征之上或上方,其可能包含上述第一特征与上述第二特征是直接接触的实施例,亦可能包含了有额外的特征形成于上述第一特征与上述第二特征之间,而使上述第一特征与第二特征可能未直接接触的实施例。此外,本发明可能在不同的范例中重复附图标记。这样的重复是为了简化与清晰的目的,并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
此外,可在此使用空间相关词语,例如:“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词,这是为了便于描述附图中一个组件或特征与另一个(些)组件或特征之间的关系。除了在附图中示出的方位外,这些空间相关用词意欲包含使用中或操作中的装置的不同方位。装置可能被转向不同方位(旋转90度或其他方位),则在此使用的空间相关词也可依此相同解释。
下文描述一些实施例的变化。通过各种视角和所示的实施例中,类似的附图标记用来标记类似的组件。可理解的是,可在上述方法之前、期间、及之后提供额外的操作,且在上述方法的其他实施例中,可置换或删除其中的一些操作。
图1为根据本发明一些实施例的半导体封装结构100的横截面示意图,该半导体封装结构100为噪音耦合抑制结构。半导体封装结构100包括基板200。基板200具有前侧201和相对于前侧201的后侧203。在一些实施例中,基板200可由硅或其他半导体材料组成。可选地,基板200可包括其他元素半导体材料,例如锗。在一些实施例中,基板200是由化合物半导体组成,例如碳化硅、砷化镓、砷化铟、或磷化铟。在一些实施例中,基板200是由合金半导体组成,例如硅锗、硅锗碳化物(silicon germanium carbide)、镓砷磷化物(galliumarsenide phosphide)、或镓铟磷化物(gallium indium phosphide)。在一些实施例中,基板200包括外延层(epitaxial layer)。举例来说,基板200具有覆盖在块状半导体上的外延层。
集成电路组件220(例如晶体管)形成于基板200的前侧201上。隔离结构205形成于基板200中,以将集成电路组件220与其他组件(未显示)隔离。
TSV内连线结构230穿过基板而形成,且从基板200的前侧201延伸至基板200的后侧203。TSV结构230包括绝缘层232和导电材料234。在一些其他的实施例中,扩散阻障层(未显示)形成于绝缘层232和导电材料234之间。
绝缘层232是由绝缘材料组成,例如氧化物或氮化物。可利用PECVD(plasmaenhanced chemical vapor deposition,等离子体增强化学汽相沉积)工艺或其他可应用的工艺形成绝缘层232。在一些实施例中,导电材料234可以是由铜、铜合金、铝、铝合金、或前述之组合所组成。在一些实施例中,利用电镀(plating)形成导电材料234。
导电凸块236形成于导电材料234上及基板200的后侧203上。导电凸块236是由导电材料组成,例如铜、铜合金、铝、铝合金、或前述之组合。
多晶硅图案(poly silicon pattern)238形成于导电材料234上及基板200的前侧201上。使用多晶硅图案238作为蚀刻停止层。
内连线结构252形成于基板200上。在一些实施例中,内连线结构252包括接触插塞和导电特征。导电特征内埋于IMD(inter-metal dielectric,金属间介电)层250中。在一些实施例中,IMD层250是由氧化硅组成。在一些实施例中,IMD层250包括由介电材料组成之多层介电层。所示的内连线结构252仅为了说明的目的。内连线结构252可包括其他的构造且可包括一种或多种导电衬垫及通孔层(via layers)。
至少两个保护环掺杂区域242和244与TSV结构230相邻,例如保护环掺杂区域242围绕并接触硅通孔内连线结构230,保护环掺杂区域244围绕并接触保护环掺杂区域244。如图1所示,第一保护环掺杂区域242形成于基板200中且相邻TSV结构230。第二保护环掺杂区域244相邻于第一保护环掺杂区域242。第一和第二保护环掺杂区域242和244耦接至接地端(GND)。因此,来自基板200或TSV结构230的噪音耦合(noise coupling)传递至第一和第二保护环掺杂区域242和244,并接着传递至接地端(GND)。虽然图1仅显示一个TSV结构230,但是可形成多于一个的TSV以穿过基板200。
图2A~2D为根据本发明一些实施例的显示形成半导体封装结构各工艺的横截面示意图。图2A为半导体封装结构100的区域300的放大的横截面示意图。
如图2A所示,提供基板200。基板200的材料已描述如上,故在此省略。第一保护环掺杂区域242形成于基板200中。第二保护环掺杂区域244相邻于第一保护环掺杂区域242而形成。应注意的是,保护环掺杂区域242和244邻接(adjoined to)彼此。
第一保护环掺杂区域242的导电类型不同于第二保护环掺杂区域244的导电类型。在一些实施例中,第一保护环掺杂区域242为n-型保护环掺杂区域,且第二保护环掺杂区域244为p-型保护环掺杂区域。n-型保护环掺杂区域包括位于n-井区域中的n-型重(n+)掺杂区域。p-型保护环掺杂区域包括位于p-井区域中的p-型重(p+)掺杂区域。
设置n-型保护环掺杂区域242用以传递高频率的噪音,例如介于约几MHz至约数GHz范围内的噪音。设置p-型保护环掺杂区域244用以传递低频率的噪音,例如介于约几MHz至约数GHz的范围内的噪音。由于n-型保护环掺杂区域242和p-型保护环掺杂区域244同时形成于基板200中,因此可传递高频率或低频率的噪音至接地端(GND)。因此,可有效地降低噪音。
多个井区域245相邻于第二保护环掺杂区域244形成。在一些实施例中,当基板200为p-型基板时,井区域245为p-型井区域。位于第二保护环掺杂区域244和井区域245之间的未掺杂区域称为原生区域(native region)。使用没有任何掺杂的原生区域来增加电阻(resistivity)。噪音可因较高的电阻而减少。
形成第一保护环掺杂区域242和第二保护环掺杂区域244之后,IMD层250形成于基板200的前侧201上。之后,多晶硅图案238形成于IMD层250中及基板200的前侧201上。多晶硅图案238用作后续蚀刻工艺中的蚀刻停止层。
之后,从基板200的后侧203对基板200实施光刻(photolithography)工艺和蚀刻工艺直到露出多晶硅图案238为止。从而形成穿过基板200的沟槽240a。
根据本发明一些实施例,形成沟槽240a之后,如图2B所示,顺应性形成绝缘层232,其衬垫于基板200的后侧203及沟槽240a的底表面和侧壁。绝缘层232是由绝缘材料组成,例如氧化物或氮化物。
根据本发明一些实施例,形成绝缘层232之后,如第2C图所示,对基板200的后侧203实施回蚀刻工艺(etching back process)以移除形成于基板200的后侧203上及沟槽240底表面上的绝缘层232。因此,露出多晶硅图案238并形成通孔(through via)240b。在一些实施例中,回蚀刻工艺可以为湿蚀刻工艺或干蚀刻工艺。
根据本发明一些实施例,形成通孔240b之后,如图2D所示,将导电材料234填入通孔240b中及基板200的后侧203上。在一些实施例中,导电材料234是由铜(Cu)、铜合金、铝(Al)、铝合金、或前述之组合所组成。在一些实施例中,利用电镀形成导电材料234。
之后,实施研磨工艺以移除通孔240b之外多余的导电材料234。在一些实施例中,研磨工艺为CMP(Chemical Mechanical Polishing,化学机械研磨)工艺。因此,形成包含绝缘层232和导电材料234的TSV结构230。
在研磨工艺之后,导电凸块236形成于导电材料234上。在一些实施例中,导电凸块236为焊锡凸块。在一些实施例中,导电材料234是由具有低电阻率的导电材料组成,例如焊锡或焊锡合金。包含在焊锡合金中的元素例如包括Sn、Pb、Ag、Cu、Ni、Bi、或前述之组合。
如图2D所示,导电材料234具有两个端点,分别形成于基板200的前侧201和后侧203上。导电材料234的其中一个端点连接至多晶硅图案238,且导电材料234的另一个端点连接至导电凸块236。
应注意的是,第一和第二保护环掺杂区域242和244耦接至接地端(GND)。因此,来自基板200或TSV结构230的噪音耦合(noise coupling)被传递至第一和第二保护环掺杂区域242和244,并接着被传递至接地端(GND)。举例来说,来自TSV结构230的噪音耦合透过基板200和保护环掺杂区域242和244被传递至接地端(GND),如图2D中箭头290所标记。
在一些实施例中,第一和第二保护环掺杂区域242和244具有深度D1,其范围介于约几百奈米(nm)至约数微米(μm)。在一些实施例中,保护环掺杂区域的深度D1和硅通孔(TSV)内连线结构230的高度H1之比例(D1/H1)范围介于30至100之间。如果比例(D1/H1)太低,较少的噪音被第二保护环掺杂区域244吸收。
图3为根据本发明一些实施例的半导体封装结构的横截面示意图。图3类似于图2D,图2D和图3之间的差异在于,在图3中,第三保护环掺杂区域246相邻于第二保护环掺杂区域244形成。换句话说,第三保护环掺杂区域246形成于井区域245和第二保护环掺杂区域244之间。
图4为根据本发明一些实施例的半导体封装结构的横截面示意图。图4类似于图2D,图2D和图4之间的差异在于,在图4中,第四保护环掺杂区域248相邻于第三保护环掺杂区域246形成。保护环掺杂区域的数量不限于二个、三个、或四个,且可根据实际应用进行调整。
本发明提供用以形成半导体封装组件的实施例。硅通孔(TSV)内连线结构形成于基板中。至少两个保护环掺杂区域形成于基板中并相邻TSV结构。保护环掺杂区域耦接至接地端。两个相邻的保护环掺杂区域具有不同的导电类型。n-型保护环掺杂区域邻接至p-型保护环掺杂区域。来自于基板或TSV结构的高频率噪音或低频率噪音可透过保护环掺杂区域而被传递至接地端(GND)。此外,在不需要额外的工艺步骤的情况下,可将TSV技术应用至半导体封装结构。
在一些实施例中,提供一种半导体封装结构。半导体封装结构包括基板,且此基板具有前侧和后侧。半导体封装结构包括形成于基板中的硅通孔(TSV)内连线结构,以及形成于基板中的第一保护环掺杂区域和第二保护环掺杂区域,且第一保护环掺杂区域和第二保护环掺杂区域相邻硅通孔(TSV)内连线结构。
在一些实施例中,提供一种半导体封装结构的形成方法。此方法包括提供基板,且此基板具有前侧和后侧。此方法也包括形成第一保护环掺杂区域和一第二保护环掺杂区域于基板中。此方法也包括形成沟槽,从基板的后侧穿过基板,并顺应性形成绝缘层,衬垫于基板的后侧、沟槽的底表面和侧壁。此方法更包括移除位于基板的后侧上的部分绝缘层以形成通孔;以及形成导电材料于通孔中,其中硅通孔(TSV)内连线结构由绝缘层和导电材料形成。
虽然本发明已以数个较佳实施例说明如上,然其并非用以限定本发明,本领域技术人员在不脱离本发明之精神和范围内,当可作任意的改动和润饰,因此本发明之保护范围当视对应的权利要求书所限定的为准。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (14)
1.一种半导体封装结构,其特征在于,包括:
基板,具有前侧和后侧;
硅通孔内连线结构,形成于该基板中;以及
第一保护环掺杂区域和第二保护环掺杂区域,形成于该基板中,其中该第一和第二保护环掺杂区域相邻该硅通孔内连线结构并且均耦接至地;
其中,该第一和第二保护环掺杂区域具有不同的导电类型。
2.如权利要求1所述的半导体封装结构,其特征在于,还包括:第三保护环掺杂区域,形成于该基板中,并且相邻于该第二保护环掺杂区域。
3.如权利要求2所述的半导体封装结构,其特征在于,还包括:第四保护环掺杂区域,形成于该基板中,并且相邻于该第三保护环掺杂区域。
4.如权利要求1所述的半导体封装结构,其特征在于,该第一保护环掺杂区域为n型保护环掺杂区域,该第二保护环掺杂区域为p型保护环掺杂区域。
5.如权利要求4所述的半导体封装结构,其特征在于,该n型保护环掺杂区域包括位于n井区域中的n型重掺杂区域;以及/或,该p型保护环掺杂区域包括位于p井区域中的p型重掺杂区域。
6.如权利要求1所述的半导体封装结构,其特征在于,该硅通孔内连线结构包括:
导电材料;
绝缘层,围绕该导电材料;
导电凸块,形成于该基板的该后侧上,其中该导电凸块直接形成于该导电材料上;以及
多晶硅图案,形成于该基板的该前侧上,其中该多晶硅图案直接形成于该导电材料上。
7.如权利要求1所述的半导体封装结构,其特征在于,还包括:
井区域,形成于该基板中,并且该井区域与该第二保护环掺杂区域之间的区域为未掺杂区域。
8.一种半导体封装结构的形成方法,其特征在于,包括:
提供具有前侧和后侧的基板;
于该基板中形成第一保护环掺杂区域和第二保护环掺杂区域,并将该第一和第二保护环掺杂区域耦接至地,其中该第一和第二保护环掺杂区域具有不同的导电类型;
形成从该基板的后侧穿过该基板的沟槽;
形成衬垫于该基板的该后侧、该沟槽的底表面和侧壁的绝缘层;
移除位于该基板的该后侧上的绝缘层,以形成通孔;以及
于该通孔中形成导电材料,从而由该绝缘层和该导电材料形成硅通孔内连线结构。
9.如权利要求8所述的半导体封装结构的形成方法,其特征在于,还包括:
于该基板的该后侧及该导电材料上形成导电凸块;
于该基板的该前侧上形成多晶硅图案。
10.如权利要求8所述的半导体封装结构的形成方法,其特征在于,还包括:
于该基板中形成井区域,该井区域与该第二保护环掺杂区域之间的区域为未掺杂区域。
11.如权利要求8所述的半导体封装结构的形成方法,其特征在于,还包括:
形成相邻该第二保护环掺杂区域的第三保护环掺杂区域;以及
形成相邻该第三保护环掺杂区域的第四保护环掺杂区域,其中该第三保护环掺杂区域的导电类型不同于该第四保护环掺杂区域的导电类型。
12.如权利要求8所述的半导体封装结构的形成方法,其特征在于,该于基板中形成第一保护环掺杂区域和第二保护环掺杂区域,包括:
于该基板中形成n型保护环掺杂区域;以及
于该基板中形成p型保护环掺杂区域;
其中,该n型保护环掺杂区域包括位于n井区域中的n型重掺杂区域;该p型保护环掺杂区域包括位于p井区域中的p型重掺杂区域。
13.一种半导体封装结构,其特征在于,包括:
基板,具有前侧和后侧;
硅通孔内连线结构,形成于该基板中;以及
第一保护环掺杂区域和第二保护环掺杂区域,形成于该基板中,其中该第一和第二保护环掺杂区域相邻该硅通孔内连线结构并且均耦接至地;
其中,还包括:第三保护环掺杂区域,形成于该基板中,并且相邻于该第二保护环掺杂区域。
14.如权利要求13所述的半导体封装结构,其特征在于,还包括:第四保护环掺杂区域,形成于该基板中,并且相邻于该第三保护环掺杂区域。
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