CN105810576B - The method and semiconductor chip of cutting crystal wafer - Google Patents
The method and semiconductor chip of cutting crystal wafer Download PDFInfo
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- CN105810576B CN105810576B CN201510937887.1A CN201510937887A CN105810576B CN 105810576 B CN105810576 B CN 105810576B CN 201510937887 A CN201510937887 A CN 201510937887A CN 105810576 B CN105810576 B CN 105810576B
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000005520 cutting process Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000013078 crystal Substances 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000001020 plasma etching Methods 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 32
- 238000000926 separation method Methods 0.000 claims description 20
- 238000000608 laser ablation Methods 0.000 claims description 14
- 230000007547 defect Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000012545 processing Methods 0.000 description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 230000004048 modification Effects 0.000 description 8
- 238000012986 modification Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 229910001092 metal group alloy Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002679 ablation Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000013467 fragmentation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 238000013532 laser treatment Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 241000931526 Acer campestre Species 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Abstract
Various embodiments are related to the method and semiconductor chip of cutting crystal wafer.A kind of method of cutting crystal wafer may include：Multiple active areas are formed in wafer, each active area includes at least one electronic component, and active area is extended in wafer from the first surface of wafer by certain altitude and separated by separated region, and separated region does not have metal；At least one groove is formed in wafer and carrying out plasma etching from the first surface of wafer at least one separated region.At least one groove further extends in wafer than multiple active areas.Method may further include handle the remainder of wafer in separated region with by wafer separate at individual chip.
Description
Technical field
Various embodiments relate generally to a kind of cutting crystal wafer method and a kind of semiconductor chip.
Background technique
The wafer for especially including small chip (such as the chip formed using 65nm technology (or even more small)) can be with
Including the layer with small dielectric constant, that is, so-called low k layer.Low k layer may be quite frangible, for example, than silica or
Other usually used dielectrics are more fragile.This may cause problem when sawing wafer is to be cut to individual chip.
Individual chip can suffer from so-called fragmentation (in the small chip of the material for the edge fracture of chip newly formed).Fragmentation can
Energy can be very serious so that having to abandon chip.
In order to avoid the function of chip is influenced by fragmentation, can be cut between the functional area of chip can be expanded
The interval cut.However, this may be decreased the chip-count of each wafer and therefore increases manufacturing cost.
It is alternatively possible to which frangible layer is separated using laser, such as by laser ablation (also referred to as laser slotting).So
And ablated material (may rest on chip) and/or (such as active area to chip is introduced into wafer by laser
In) both heats may cause the damage to chip, this chip must not be not dropped.This means that the output of production technology
It may decline, therefore increase manufacturing cost.
Summary of the invention
A kind of method of cutting crystal wafer may include：Multiple active areas are formed in wafer, each active area includes at least
One electronic component, active area are extended to from the first surface of wafer in wafer and by separated region point by certain altitude
From separated region does not have metal；In at least one separated region, and the first surface plasma etching from wafer
At least one groove is formed in wafer.At least one groove further extends in wafer than multiple active areas.Method is into one
Step include the remainder of wafer of the processing in separated region with by wafer separate at individual chip.
Detailed description of the invention
In the accompanying drawings, through different views, identical appended drawing reference generally refers to identical part.Attached drawing is not necessarily
It is proportional, emphasis but be placed in and explain in the principle of the present invention.In the following description, various embodiments of the present invention are joined
The following drawings description is examined, wherein：
Figure 1A to Fig. 1 F shows each stage of the method for cutting crystal wafer according to various embodiments；
Fig. 2A to Fig. 2 F shows each stage of the method for cutting crystal wafer according to various embodiments；
Fig. 3 shows the schematic cross section of semiconductor chip according to various embodiments；And
Fig. 4 shows the schematic process flow diagram of the method for cutting crystal wafer according to various embodiments.
Specific embodiment
Detailed description below refers to accompanying drawing, and attached drawing is shown in a manner of explaining can practice the present invention wherein
Detail and embodiment.
Word " exemplary " used herein means " as example, example or explanation ".It is described herein as " exemplary "
Any embodiment or design are not necessarily construed as preferably or more advantageous than other embodiments or design.
For be formed in side or surface " on " deposition material word " on " can be used to mean herein
The material of deposition for example can be directly contact directly formed on signified side or surface with signified side or surface.For
Be formed in side or surface " on " deposition material word " on " can be used to mean that the material of deposition can herein
Be formed on signified side or surface indirectly, wherein one or more additional layer arrangements are on signified side or surface and sink
Between long-pending material.
Various aspects of the disclosure is provided for device, and various aspects of the disclosure is provided for method.It answers
When the fundamental characteristics for understanding device is also suitable method and vice versa.Therefore, for sake of simplicity, the repeated description of this characteristic
It may be omitted.
Hereinafter, " active area " may refer to may include such as crystal in semiconductor crystal wafer or semiconductor chip
The region of at least one electronic component of pipe, diode etc..Such as it may include integrated circuit.
Hereinafter, " separated region " may refer between two adjacent active areas in wafer region (and/or
Refer to the region between active area and the edge of wafer).
It in various embodiments, can at individual chip in order to which wafer to be divided to (singulate) (also referred to as cutting)
Improve the cutting result for narrow separated region (in general, can execute in separated region by wafer to be incorporated to new technique
It is separated into individual chip), and to reduce manufacturing cost simultaneously.Narrower separated region can permit to be arranged more on wafer
More chips.
In addition, cutting may include etching technics, and the adjustable etching depth that can be executed makes by will be by
The heat that laser cutting parameter introduces guide the deeper region of such as chip into and far from active area, can be to avoid to may be to heat
The heat impact of the active area of sensitive chip.
It in various embodiments, can be with binding plasma etching technics and the second cutter in wafer cutting technique
Skill.Plasma etching can be executed in multiple separated regions, multiple separated region can be arranged in having for multiple chips
Between source region, the active area of multiple chips extends in wafer from the surface of wafer, so that passing through plasma etch process shape
At groove can further be extended in wafer from the surface of wafer than active area.Second cutting technique can be used for separating
Separation is formed in region in remaining material, therefore completes the separation to multiple chips.
Figure 1A to Fig. 1 F shows each stage of the method for cutting crystal wafer according to various embodiments.
As shown in figure 1A, in various embodiments, wafer 102 can have first surface on the first side of wafer
1021 and in second side of wafer have the second surface 1022 opposite with first surface 1021.Wafer 102 can be half
Semiconductor wafer, such as Silicon Wafer, germanium wafer, SiGe wafer, gallium nitride wafer etc..In other words, wafer may include semiconductor
Material, such as silicon, germanium, gallium nitride etc..Wafer can have thickness 102T.
In various embodiments, wafer 102 may include the material with low-k, and this material is also referred to as low
K material 104 or low K dielectrics 104.Low-k materials 104 can be formed on the first side of wafer 102.It can be at least partly
(such as shown in figure 1A, fully) forms the first surface 1021 of wafer 102.In various embodiments, low-k materials 104
It can be formed the part of one or more layers or one layer or the part of multilayer.For example, low-k materials 104 can be formed one
A structured layer or multiple structured layers.Low-k materials 104 may be quite frangible.
In various embodiments, the method for cutting crystal wafer 102 may include that multiple active areas 110 are formed in wafer 102.
Each active area 110 in multiple active areas 110 can extend to wafer from the first surface 2021 of wafer 102 with certain altitude
In 102.The height of each active area 110 of multiple active areas 110 can also be referred to as its thickness 110T.In various embodiments
In, thickness 110T can be less than the thickness 102T of wafer 102.For example, thickness 110T can be less than the thickness 102T's of wafer 102
About 95%, be, for example, less than about the 80% of thickness 102T, be, for example, less than thickness 102T about 50%, be, for example, less than thickness
About the 10% of 102T.
In various embodiments, a part of of the wafer 102 under the level of multiple active areas 110 can be referred to as crystalline substance
The substrate portions of circle 102.In various embodiments, the wafer 102 under the level of multiple active areas 110 can have thickness
102TS, the i.e. substrate portions of wafer 102 can have thickness 102TS.In other words, the thickness 102T of wafer 102 can be more
The sum of thickness 110T and the thickness 102TS of substrate portions of wafer 102 of a active area 110.
Hereinafter, it unless differently indicates, " each active area 110 " and/or " active area 110 " can indicate multiple have
110/ active area 110 of each active area in source region, and " multiple active areas 110 " can indicate multiple active areas 110.
In various embodiments, each active area 110 may include at least one different from the semiconductor material of wafer 102
Kind material.For example, each active area 110 may include such as such as copper, aluminium, copper-tin, the gold titanium for providing redistribution layer
Category or metal alloy, via hole and/or conductive contact.Each active area can be for example including at least one metalization layer, such as wraps
Include multiple metalization layers.Minimum metallization can be referred to as with the immediate metalization layer of second surface 1022 of wafer 102
Layer or referred to as bottom metallization layer.
In various embodiments, for example, each active area 110 may include for example for conductive structure to be electrically insulated from each other
Dielectric, such as silica, silicon nitride, with low-k (relative to for example pure body silica) material, example
Such as low-k materials 104, such as silica, porous silica, the organic polymer dielectric of Fluorin doped etc..
In various embodiments, during the formation of active area 110, multiple separated regions 112 can be formed.It is multiple active
Area 110 can be separated by the separated region 112 of multiple separated regions 112.In other words, it can be formed in wafer 102 multiple
Active area 110, so that all active areas 110 adjacent to each other in multiple active areas 110 are by point in multiple separated regions 112
It is separated from region 112.Furthermore, it is possible to multiple active areas 110 be formed in wafer 102, so that point in multiple separated regions 112
The active area 110 and wafer 102 adjacent with the edge of wafer 102 (such as circumferential edges) can be disposed in from region 112
Between edge.In other words, multiple separated regions 112 can be disposed between multiple active areas 110 and have around multiple
Source region 110.
In the various embodiments of the method for cutting crystal wafer, multiple active areas 110 can be formed in wafer 102, so that
Multiple separated regions 112 can not have metal, such as without metal layer (or metal alloy layer) or not a part of metal layer
(or a part of metal alloy layer).In other words, multiple separated regions 112 can not include metal or metal alloy.Change sentence
It talks about, the layout of wafer 102 can be made so as to multiple separated regions 112 and be formed no metal.In various embodiments,
No one of multiple separated regions 112 may include metal or metal alloy.
In various embodiments, multiple separated regions 112 can be further without low K dielectrics 104.
In various embodiments, multiple separated regions 112 can only include the semiconductor material of semiconductor crystal wafer.Various
In embodiment, multiple separated regions 112 may include semiconductor crystal wafer semiconductor material and routine it is (such as opposite with low k
) dielectric substance, such as silica and/or silicon nitride.
In various embodiments, the method for cutting crystal wafer may include being formed on the first surface 1021 of wafer 102
Exposure mask 106, such as the exposure mask 106 of structuring.Exposure mask 106 can be covering of such as generally using in plasma etch process
Film, such as photo etched mask.For example, exposure mask may include photoresist or substantially be made of photoresist.It can be such as
Using photoetching process by 106 structuring of exposure mask.In various embodiments, exposure mask 106 can be for example including silica and/or
The hard exposure mask of silicon nitride.
In various embodiments, (such as structuring) exposure mask 106 can be formed and make first surface 1021 in wafer 102
At least part of multiple separated regions 112 at place can not have exposure mask 106.In other words, exposure mask 106 may include at least one
A opening 108, such as groove, wherein at least one opening 108 can be arranged on multiple separated regions 112.
As shown in figure 1B, in various embodiments, the method for cutting crystal wafer may include formed in wafer 102 to
A few groove 114.Can from the first surface 1021 of wafer 102 by carried out at least one separated region 112 etc. from
Daughter etches to form at least one groove 114.Plasma etch process can be used in wafer 102 forming at least one ditch
Slot 114, plasma etch process are, for example, anisotropic etching technics, such as deep reaction ion etching, such as Bosch
(Bosch) etching technics.In various embodiments, since at least one separated region 112 can not have metal, it is possible to save
Slightly it is suitable for etching the etching technics of metal.In other words, the individual plasma suitable for the semiconductor material of etching wafer 102
Etching technics (such as anisotropic etching) can be used for being formed at least one groove 114.
In various embodiments, at least one groove 114 can have width 114W, width 114W from about 10 μm to
In about 70 μm of range, such as in the range from about 15 μm to about 30 μm.
In various embodiments, at least one groove 114 can be completely formed at least one separated region 112.
In other words, the side wall of at least one groove 114 can be not formed at multiple active areas 110 or in multiple active areas 110.
Therefore, the side wall of at least one groove 114 (can not mark, but referring to Fig. 3, wherein semiconductor core herein without metal
The upper surface 230SU of piece 230 can be with the side of at least one groove 114 formed in the cutting technique of semiconductor chip 230
Wall is corresponding).
In various embodiments, at least one groove 114 can further extend to wafer 102 than multiple active areas 110
In.For example, in vertical direction, at least one groove 114 can be disposed in the second surface 1022 of wafer 102 and multiple have
At level between the minimum metalization layer of source region 110.In other words, the depth 114D of groove 114 can have greater than multiple
The thickness 110T of source region 110.Again in other words, groove 114 extends in the substrate portions of wafer 102.Again in other words,
Difference DELTA DT=114D -110T can be greater than 0.
In various embodiments, which, which may be enough to be formed to have, is greater than multiple active areas
At least one groove 114 of the depth 114D of 110 thickness.
In various embodiments, the depth 114D of groove 114 can be less than the thickness 102T of wafer 102.In other words, exist
After the etching of groove 114, can remaining separated region 112 the bottom in groove 114 horizontal down part.This is in example
As indicated in Figure 1B by dashed rectangle.This part of separated region 112 can be referred to as remainder 112R or referred to as bottom
Portion part 112R.
In various embodiments, the depth 114D of groove 114 can be substantially greater than the thickness of multiple active areas 110
110T.The depth 114D of groove 114 can be larger about for example 1 μm, such as about 5 μm than thickness 110T.This may be, for example, this
Kind situation, if in the subsequent processing of the wafer 102 of the cutting for completing wafer 102, heat such as swashing in wafer 102
It is introduced in light processing in wafer 102.In various embodiments, can according to the amount for the heat being introduced into wafer 102 come
Difference DELTA DT is adjusted, the amount of heat is for example depending on laser output power, wavelength of laser etc..The heat being introduced into wafer 102
The amount of amount is higher, can choose be used to form groove 114 difference DELTA DT it is bigger.In an illustrative manner, when use infrared laser
When for further cutting technique, difference DELTA DT can be bigger than using blue laser.
In various embodiments, the depth 114D of the groove 114 of no ensuing laser processing can be substantially greater than multiple
The thickness 110T of active area 110.
In various embodiments, the depth 114D of groove 114 can be slightly greater than the thickness of multiple active areas 110
110T.The depth 114D of groove 114 can for example be less than greatly about 1 μm, for example less than about 500nm than thickness 110T.This can
It can be, for example, such case, if machine can be used in the subsequent processing of the wafer 102 of the cutting for completing wafer 102
Tool technique, such as sawing.Even if however, executing laser treatment is used for cutting crystal wafer 102, the depth 114D of groove 114 can also be with
The thickness 110T of slightly greater than multiple active areas 110.
In various embodiments, it by extending at least one groove 114 in the substrate area of wafer 102, can keep away
Exempt from for example as overheating to damage caused by one or more active areas 110 because multiple separated regions 112, formed at least
May be remaining after one groove 114 and it may need that (such as laser ablation or laser stealth are cut for example, by laser treatment
Cut) separation part can be sufficiently apart from multiple active areas 110, to cause temperature at multiple active areas 110 that cannot rise to damage
Wound is horizontal.In other words, at least one groove 114 can be formed enough to depth, have sufficiently large difference DELTA DT, to ensure
Temperature at multiple active areas 110 is maintained at level of damage or less.
In various embodiments, it by extending at least one groove 114 in the substrate area of wafer 102, can keep away
Exempt from for example and causing crackle to extend in one or more active areas 110 to caused by one or more active areas 110
Damage because multiple separated regions 112 after forming at least one groove 114 may residue and may need to pass through example
As sawing or as laser stealth cut a part rupture and isolated part can be sufficiently apart from multiple active areas 110
And/or can be sufficiently wide so that can for example start in the remainder of multiple separated regions 112 crackle (such as deliberately
Ground is as stealthy a part cut and/or unexpectedly) it can propagate to groove 114 and terminate there, rather than propagate
To in one or more of multiple active areas 110.
In various embodiments, after the etch, exposure mask 106 can be removed, such as photoresist can be removed.
In various embodiments, as shown in Fig. 1 C to Fig. 1 F, remainder 112R can be processed, such as is processed,
Wafer 102 is separated into individual chip (such as chip 230 shown in fig. 3).Wafer 102 is separated into independent chip
The cutting of wafer 102 can also be referred to as.
As shown in fig. 1 c, in various embodiments, the method for cutting crystal wafer, which may further include, is attached layer 116
To the first surface 1021 of wafer 102, such as the first surface 1021 by layer 116 fixed to wafer 102.Layer 116 can be such as
It is lapping tape.Wafer 102 can be installed to grind since the second surface 1022 of wafer 102.As layer 116, can be used
Common grinding layer, such as common lapping tape, such as soft, viscosity, UV or the releasable PET film of heat.
In various embodiments, the method for cutting crystal wafer may further include grinding crystal wafer 102.It can be from wafer 102
Second surface 1022 start grinding crystal wafer 102.After milling, as shown in Fig. 1 D, the thickness 102T of wafer 102 can be with
It is down to the thickness 102TR of reduction.The reduced thickness 102TR of wafer 102 can be greater than the depth of groove 114D.In other words,
Grinding can not exclusively remove remainder 112R.
In various embodiments, the method for cutting crystal wafer, which may further include, installs wafer 102 (for example, pacifying again
Dress) in incised layer 220, such as in cutting belt 220.Incised layer 220 can be attached to the first surface 1021 of wafer 102.Cause
This, the second surface 1022 of wafer 102 can be accessible to the processing of such as laser treatment.Alternatively, in some cases
Under, incised layer 220 can be attached to the second surface 1022 of wafer 102, these situations are e.g. possible can be from wafer 102
First side position manages remainder 112R, for example, if depth-to-width ratio (such as the depth 114D of groove 114 and the groove of groove 114
Width 114W ratio) be small enough so that and can process remainder 112R or these situations from the first side of wafer 102
E.g. despite the presence of incised layer 220, or remainder 112R, example can may be started to process from second side of wafer 102
As if incised layer 220 is substantial transparent to the light emitted by laser.
As incised layer 220, can be used for example cutting belt 220, common incised layer 220, for example common cutting belt,
It is for example suitable for the common cutting belt of laser (such as stealthy) cutting.Incised layer 220 for example may be configured to bear may be
It may, for example, be by a large amount of heat and/or incised layer 220 that are introduced in the cutting technique of laser in incised layer 220
Porous and/or provide strongly adherent for draining/bearing water, water can be cooling purpose during laser cutting parameter
It is provided and/or incised layer 220 can be for example transparent to optical maser wavelength.
In various embodiments, as shown in fig. ie, the remainder 102B of processing (such as processing) wafer 102 can be with
It is cut including laser stealth.Laser stealth cutting may include utilizing laser to irradiation remainder 112R to allow to be formed tool
There is the region 224 of modification structure (such as crystal structure of modification).Region 224 with modification structure can form defect area
Domain.In an illustrative manner, single-crystal semiconductor material can be changed to polycrystalline semiconductor material using the irradiation of laser.However,
The semiconductor material of wafer 102 can without or at least without be significantly utilized laser irradiation removal.With modification structure
Region 224 can be more more fragile without the part of laser processing than the possibility of wafer 102.In various embodiments, it can execute
Conventional laser stealth cutting technique.
In various embodiments, region 224 can have from 5 μm of width to about 30 μ ms are greater than, such as about
10μm。
In various embodiments, the width 114W of groove 114 can be greater than the width in region 224.Thereby it can be assured that such as
It is described below can be located at the bottom of groove 114 in one end of 228 (F referring to fig. 2) of caused fracture in region 224.
In various embodiments, the laser for laser stealth cutting can be infrared laser.The wavelength of laser can example
Such as it is greater than about 750nm.Laser may, for example, be the Nd with 1064nm wavelength:YAG laser, such as pulse Nd:YAG swashs
Light.In various embodiments, the laser with different wave length and/or with other different characteristics can be used for laser stealth and cut
It cuts.
Therefore, as shown in figure 1f, expanded by applying on the wafer 102 for including the region 224 with modification structure
Cross force is opened, wafer 102 can be broken at 224 with modification structure.In an illustrative manner, fracture 228 (is also referred to as split
228) line 228 or separation can be formed in the region 224 with modification structure, from the second surface 1022 of wafer 102 to ditch
Slot 114 extends.
In order to apply expansion cross force on wafer 102, wafer 102 can be attached to expansion layer 226, such as be fixed on expansion
It opens on layer 226, such as is fixed on spreading belt 226.As expansion layer 226, common expansion layer can be used, such as common
Spreading belt, such as distensible synthetic resin film.In various embodiments, incised layer 220 can be distensible, so that being not required to
Want special expansion layer 226.
By being stretched in opposite transverse direction (such as in two pairs of opposite transverse directions or in radial directions)
One or more edges of expansion layer 226 can apply expansion cross force on wafer 102.Wafer 102 may have modification
It is ruptured at one or more regions 224 of structure.Wafer 102 can form separation 228.Therefore, it can be formed multiple individual
Semiconductor chip 230.
In various embodiments, as shown in fig. 2f, expansion layer 226 can be applied to the second surface of wafer 102
1022.It is alternatively possible to which expansion layer 226 to be applied to the first surface 1021 of wafer 102.
In various embodiments, as described above, the method for cutting crystal wafer may include being attached to wafer 102 temporarily
Support construction 116,220,226.In various embodiments, temporary support structure 116,220,226 may include or substantially by
It is formed with lower layer：Grinding layer 116, incised layer 220 and/or expansion layer 226.In various embodiments, in the same of processing wafer 102
When, only one temporary support structure 116,220,226 can be attached to wafer 102.Wafer is attached to (example depending on being directed to
Such as it is fixed to) the possible technique executed of temporary support structure 116,220,226, temporary support structure 116,220,226 can be attached
It is connected to the first surface 1021 of wafer 102 or is attached to the second surface 1022 of wafer 102.
Fig. 2A to Fig. 2 F shows each stage of the method for cutting crystal wafer 102 according to various embodiments.
In various embodiments, the technique shown in Fig. 2A to Fig. 2 D can be respectively and shown in Figure 1A to Fig. 1 D
Technique is identical.
The technique shown in Fig. 2A to Fig. 2 F can be different from technique shown in Figure 1A to Fig. 1 F, essentially consist in, such as
Shown in Fig. 2 E, the remainder 112R of processing wafer 102 can not include laser stealth cutting.
In various embodiments, the remainder 112R for processing wafer 102 may include laser ablation.In other words, swash
Light can be used for partly removing semiconductor material from the separated region of wafer 102 112.
In various embodiments, for the laser of laser ablation can be described above to laser stealth cutting swash
Light is similar or identical.However, laser may be configured to partly remove semiconductor material.In various embodiments, with laser
Stealth cutting is compared, and one or more parameters of the laser and/or its operation can be modified, so that being introduced into wafer 102
Energy in the processing part of separated region 112 can be enough ablation semiconductor material.In an illustrative manner, it can be directed to and partly lead
Ablation adjustment laser energy, pulse duration, pulse frequency and/or sweep speed of body material etc..
In various embodiments, using laser ablation, separation 228 can be formed in wafer 102, such as in wafer 102
Separated region 112 in, such as in the remainder 112R of separated region 112.
In various embodiments, it can have by the separation 228 that laser ablation is formed from about 5 μm to about 20 μm
In the range of width, such as about 10 μm.
In various embodiments, the remainder 112R for processing wafer 102 may include sawing.Use sawing, separation 228
It can be formed in wafer 102, such as in the separated region of wafer 102 112, such as the remainder in separated region 112
In 112R.
In various embodiments, can for example using thin saw cutting blade execute sawing, such as with from about 10 μm to
The saw cutting blade of thickness in about 50 μ ms.Therefore, it can have by the separation 228 that sawing is formed from about 10 μm
To the thickness in about 50 μ ms.
In various embodiments, other techniques can be used for being formed in the remainder 112R of separated region 112
Separation 228.
In various embodiments, the width 114W of groove 114 can be greater than separation 228, and separation 228 can be processed with passing through
The separation between individual chip 230 that the remainder 112R of wafer 102 is formed is corresponding.
In various embodiments, separation 228 can be formed by laser ablation, sawing etc..Therefore, wafer 102 can be by
(cutting) is separated into individual chip 230.Opposite with as shown in Figure 1A to Fig. 1 F, the technique shown in Fig. 2 E it
Afterwards, i.e., after through the formation such as laser ablation, sawing separation 228, the individual chip 230 of separation can be had existed.
In various embodiments, as shown in fig. 2f, expansion layer 226 and expansion work are used as described in conjunction with Fig. 1 F
The optional expansion of skill can be used for increasing the width of separation 228.
Fig. 3 shows the schematic cross section of semiconductor chip 230 according to various embodiments.
In various embodiments, semiconductor chip 230 may include the first surface at least one active area 110
1021C, the second surface 1022C opposite with first surface 1021C and connection first surface 1021C and second surface 1022C
At least one side surface 230SU, 230SL.Semiconductor chip 230 can for example near cubic shape, and at least one
A side surface 230SU, 230SL can be connection first surface 1021C and second surface 1022C four side surface 230SU,
230SL。
In various embodiments, the first surface 1021C of semiconductor chip 230 can be above-described wafer 102
A part of first surface 1021, and the second surface 1022C of semiconductor chip 230 can be above-described wafer 102
Second surface 1022 a part.
In various embodiments, at least one side surface 230SU, 230SL of common edge are formed with first surface 1021C
First part 230SU can be formed by plasma etching.
The first part 230SU of at least one side surface 230SU, 230SL, also referred to as at least one side surface 230SU,
The top 230SU of 230SL can for example be formed a part of at least one above-described groove 114, such as side wall.
In various embodiments, for the formation by plasma etching, at least one side surface 230SU, 230SL's
The shape of first part 230SU can be characteristic.The first part 230SU of at least one side surface 230SU, 230SL can
With the wall shape for example with fluctuating, it can also be described as the wall shape or wave-like of pectination, which may originate from
The alternating of etching and passivation during the execution of the plasma etching of such as deep reaction ion etching.It can be for example as above
Description ground executes plasma etching.
As described above, the first part 230SU of at least one side surface 230SU, 230SL can have greater than active
The height 114D (can be identical as the depth of trenches described above 114) of the thickness 110T in area 110.
In various embodiments, at least one side surface 230SU, 230SL of common edge are formed with second surface 1022C
Second part 230SL can by laser processing and/or machine cuts be formed.
The second part 230SL of at least one side surface 230SU, 230SL, also referred to as at least one side surface 230SU,
The downside surface 230SL of 230SL can pass through the remainder for the wafer 102 in separated region 114 as described above
Being further processed for 114R is divided to be formed with the technique for executing wafer separate at individual chip 230.Second part 230SL can
For example by laser stealth cutting (i.e. laser irradiation is then mechanically decoupled), by laser ablation, by sawing or pass through it
His (such as mechanical) suitable separation method is formed.
In various embodiments, for by remainder 112R for the wafer 102 in separated region 112 into
The processing of one step is with the formation by wafer separate at the technique of individual chip 230, and the of at least one side surface 230SU, 230SL
The shape of two part 230SL can be characteristic.For example, the second part 230SL of at least one side surface 230SU, 230SL
Shape can be for by the formation that laser stealth is cut being characteristic, such as very smooth surface, or for sharp
Light ablation is characteristic, such as may show the very smooth surface of the instruction of some fusings, or formed by sawing
The coarse surface of characteristic appropriateness.
In various embodiments, as described above, at least one groove 114 may be formed entirely in separated region 112
It is interior.Therefore, at least one side surface 230SU, 230SL can not have metal.
Fig. 4 shows the schematic process flow diagram 600 of the method for cutting crystal wafer according to various embodiments.
In various embodiments, method may include that multiple active areas are formed in wafer, and each active area includes at least
One electronic component, active area are extended to from the first surface of wafer in wafer and by separated region point by certain altitude
From separated region does not have metal (in 610).
In various embodiments, method may further include at least one separated region by from the first of wafer
Surface carries out plasma etching and forms at least one groove in wafer, and wherein at least one groove is than multiple active areas
It further extends in wafer (in 620).
In various embodiments, method may further include the remainder for handling the wafer in separated region to incite somebody to action
Wafer separate is at individual chip (in 630).
In various embodiments, a kind of method of cutting crystal wafer is provided.Method may include：It is formed in wafer multiple
Active area, each active area include at least one electronic component, and active area is extended through certain altitude from the first surface of wafer
It is separated into wafer and by separated region, separated region does not have metal；By from wafer at least one separated region
First surface carries out plasma etching and forms at least one groove in wafer, and wherein at least one groove has than multiple
Source region further extends in wafer；And handle the remainder of wafer in separated region with by wafer separate at independent
Chip.
In various embodiments, process wafer remainder may include laser ablation or laser stealth cutting in extremely
Few one kind.Wavelength for laser ablation or the laser of laser stealth cutting can be greater than about 750nm.In various embodiments
In, the remainder for processing wafer may include sawing.In various embodiments, method may further include in processing wafer
Remainder before, by the first surface of wafer be fixed to temporary support structure.
In various embodiments, method may further include before the remainder of processing wafer, will be with the first table
The second surface of the opposite wafer in face is fixed to temporary support structure.In various embodiments, it can be held from the first side of wafer
The remainder of row processing wafer, wherein the first surface of wafer can be located on the first side of wafer.Can from wafer
Second side of the opposite wafer in first side executes the remainder of processing wafer.The width of groove can be greater than through processing wafer
Remainder formed independent chip between separation.
In various embodiments, a kind of semiconductor chip is provided.Semiconductor chip may include having at least one
The first surface of source region, the second surface opposite with first surface and at least one the side table for connecting first surface and second surface
Face.The first part for forming at least one side surface of common edge with first surface can be formed by plasma etching.
The second part for forming at least one side surface of common edge with second surface can be by laser processing and/or machine cuts
It is formed.At least one side surface can not have metal.
Although the present invention is particularly shown and described by reference to specific embodiment, those skilled in the art are answered
It, can be in form when understanding in the case where not departing from the scope and spirit of the present invention such as limited by the attached claims
Various changes are made to the present invention in details.Therefore the scope of the present invention by the attached claims indicate and it is intended that
Including enter claim meaning and equivalent in the range of all changes.
Claims (15)
1. a kind of method of cutting crystal wafer, the method includes：
Multiple active areas are formed in wafer, each active area includes at least one electronic component, and the active area passes through certain
Height is extended in the wafer from the first surface of the wafer and is separated by separated region, and the separated region is without gold
Belong to；
Described and carrying out plasma etching from the first surface of the wafer at least one separated region
At least one groove is formed in wafer, wherein at least one described groove further extends to the crystalline substance than the multiple active area
In circle；And
Handle the remainder of the wafer in the separated region with by the wafer separate at individual chip,
The remainder for handling the wafer includes at least one of laser ablation, laser stealth cutting and sawing.
2. according to the method described in claim 1, the laser wherein cut for the laser ablation or the laser stealth
Wavelength than about 750nm long.
3. handling the described surplus of the wafer according to the method described in claim 1, wherein executing from the first side of the wafer
Remaining part point, wherein the first surface of the wafer is located on first side of the wafer.
4. according to the method described in claim 1,
The remainder of the wafer is wherein handled below the multiple active area of the wafer at predefined distance
It executes.
5. according to the method described in claim 4,
Wherein the predefined distance is based on from at least one in laser ablation and laser stealth cutting to the wafer
Desired heat transfer.
6. according to the method described in claim 1,
The remainder for wherein handling the wafer includes modifying the structure of the remainder to form at least one and lack
Fall into region.
7. according to the method described in claim 6,
Wherein at least one described defect area is narrower than the width of at least one groove.
8. according to the method described in claim 6, further comprising：
Apply expansion cross force so that at least one described defect area is broken, by the wafer separate at the individual core
Piece.
9. according to the method described in claim 1,
The remainder for wherein handling the wafer, which is included in the remainder, to be formed the wafer separate into institute
State at least one disengagement zone of individual chip.
10. according to the method described in claim 9,
Wherein at least one described disengagement zone is narrower than the width of at least one groove.
11. according to the method described in claim 1,
Wherein the multiple active area is formed in the semiconductor material of the wafer.
12. according to the method for claim 11,
The separated region without metal includes the semiconductor material.
13. according to the method described in claim 1, further comprising：
Before the remainder for handling the wafer, by the first surface of the wafer or with the first surface
The second surface of the opposite wafer is fixed to temporary support structure.
14. according to the method described in claim 1,
The residue for handling the wafer is wherein executed from second side of the wafer opposite with the first side of the wafer
Part,
Wherein the first surface of the wafer is located at first side of the wafer.
15. according to the method described in claim 1,
Wherein the width of the groove is greater than between the individual chip formed by the remainder for handling the wafer
Separation.
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| DE102015100783A1 (en) * | 2015-01-20 | 2016-07-21 | Infineon Technologies Ag | Method for dicing a wafer and semiconductor chip |
| CN107685196B (en) * | 2017-07-14 | 2018-09-14 | 中国科学院微电子研究所 | A kind of method and device of laser processing wafer |
| CN109599357B (en) * | 2018-11-26 | 2020-12-18 | 合肥彩虹蓝光科技有限公司 | Cutting method and manufacturing method of semiconductor element |
| CN109920759B (en) * | 2019-02-03 | 2021-03-09 | 中国科学院微电子研究所 | Method for cutting chip |
| US11289378B2 (en) * | 2019-06-13 | 2022-03-29 | Wolfspeed, Inc. | Methods for dicing semiconductor wafers and semiconductor devices made by the methods |
| JP7443097B2 (en) * | 2020-03-09 | 2024-03-05 | キオクシア株式会社 | Semiconductor wafers and semiconductor chips |
| US20210296176A1 (en) * | 2020-03-23 | 2021-09-23 | Semiconductor Components Industries, Llc | Structure and method for electronic die singulation using alignment structures and multi-step singulation |
| US20220406601A1 (en) * | 2021-06-16 | 2022-12-22 | Monolithic Power Systems, Inc. | Laser induced semiconductor wafer patterning |
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| US20160211178A1 (en) | 2016-07-21 |
| CN108682648A (en) | 2018-10-19 |
| DE102015100783A1 (en) | 2016-07-21 |
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