CN105807842A - Improved type low-dropout linear regulator - Google Patents
Improved type low-dropout linear regulator Download PDFInfo
- Publication number
- CN105807842A CN105807842A CN201610312217.5A CN201610312217A CN105807842A CN 105807842 A CN105807842 A CN 105807842A CN 201610312217 A CN201610312217 A CN 201610312217A CN 105807842 A CN105807842 A CN 105807842A
- Authority
- CN
- China
- Prior art keywords
- circuit
- voltage
- cmos
- error amplifier
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Abstract
The invention discloses an improved low-dropout linear regulator, comprising a bandgap reference voltage source circuit, a CMOS two-stage error amplifier circuit, a regulator tube, a frequency compensation circuit and a feedback circuit. The bandgap reference voltage source circuit provides a voltage unrelated to a supply voltage and an ambient temperature, and is connected with the CMOS two-stage error amplifier circuit, and the CMOS two-stage error amplifier circuit is connected with the bandgap reference voltage source circuit, the feedback circuit and the regulator tube; the frequency compensation circuit is connected with the regulator tube, and the regulator tube is connected with the feedback circuit. Error amplifying signals are generated by the CMOS two-stage error amplifier circuit, and the regulator tube helps to feed back errors and reduce dropout; the phase margin of the circuit is compensated by the frequency compensation circuit, including Miller compensation and ESR (Equivalent Series Resistance) compensation, so that the phase margin requirements can be easily met; the output voltage is regulated by the feedback circuit.
Description
Technical field
The present invention relates to linear voltage regulator, particularly to frequency compensated circuit and band-gap reference circuit.
Background technology
Manostat is able to the circuit of regulated output voltage, it can be automatically adjusted output voltage, by fluctuating, supply voltage that is relatively big or that be unsatisfactory for product work demand is stable in the normal range of operation of its setting, a constant output voltage is provided, so that load can at normal operation under rated operational voltage for load.Low pressure difference linear voltage regulator refers to the difference between minimum input voltage and stable output voltage, and difference is more little, then the scope of running voltage is more big, and the requirement of input is also more little.
Divide from the angle of technique, mainly include the linear voltage regulator of the linear voltage regulator of bipolar technology, the linear voltage regulator of CMOS technology and BiCMOS technique.
Divide with the duty of conduction device, DC-DC manostat and linear voltage regulator can be divided into.What conduction device was operated on off state is called DC-DC manostat, what conduction device was operated in linear condition is called linear voltage regulator, they are respectively arranged with pluses and minuses: the maximum advantage of DC-DC manostat is that efficiency is high, be possible not only to boosting can also blood pressure lowering, shortcoming is that precision is low, volume big, stability is not high, noise is big.The maximum advantage of linear voltage regulator is precision height, good stability, noise is little, volume is little, and shortcoming is inefficient, and can only blood pressure lowering can not boost.
As previously mentioned, the present invention is adopting on traditional linear voltage regulator structure of CMOS technology and the basis of linear voltage regulator structure, input is improved to band gap reference voltage source circuit, the voltage provided will not be changed along with the floating of supply voltage and ambient temperature, reduce the unstability of circuit, the ESR of the present invention compensates circuit and also adds phase place on the basis of script circuit simultaneously so that the phase margin of whole circuit more easily reachs 60 °.
Summary of the invention
(1) to solve the technical problem that
This modified model to solve the technical problem that: how to make linear stabilizer output voltage reach desired value and utilize ESR to compensate, reduces the unstability of circuit.
(2) technical scheme
For solving the problems referred to above, this modified model provides a kind of low pressure difference linear voltage regulator, including: band gap reference voltage source circuit, CMOS two-stage error amplifier circuit, adjustment pipe, frequency compensated circuit and feedback circuit.Described band gap reference voltage source circuit connects described CMOS two-stage error amplifier circuit；Described CMOS two-stage error amplifier circuit connects described band gap reference voltage source circuit, feedback circuit and adjustment pipe；Described frequency compensated circuit connects described adjustment and manages；Described adjustment pipe connects described feedback circuit.Described band gap reference voltage source circuit is used for providing the burning voltage unrelated with operating temperature；Described CMOS two-stage error amplifier circuit is used for producing error amplification signal；The described pipe that adjusts for feedback error and reduces pressure reduction；Described frequency compensated circuit is for compensating the phase margin of circuit；Described feedback circuit is used for adjusting output voltage.Finally make output voltage reach desired value, and add the stability of circuit.
Wherein, described band gap reference voltage source circuit includes start-up circuit part, electric capacity C1, NMOS tube M1, PMOS M2 are connected with NMOS tube M3 drain electrode, and M2 source class connects supply voltage composition；The current generating circuit part unrelated with power supply, is connected by PMOS M4 and PMOS M5 grid, and drain electrode is connected with PNP pipe Q1 emitter stage again, PNP pipe Q2, resistance R1 are one group of composition；Two grades of error amplifier circuit parts in band gap reference voltage source circuit, are one group are formed by NMOS tube M6 and PMOS M7, PMOS M9 pipe, NMOS tube M10 pipe, NMOS tube M8, NMOS tube M11, NMOS tube M12, PMOS M13；PMOS M13 and resistance R2 is connected and is connected with the emitter stage of PNP pipe Q3, the last circuit exporting bandgap voltage reference of composition.Described CMOS two-stage error amplifier circuit includes resistance R3, PMOS (M14, M17), PMOS (M17, M18), NMOS tube (M16, M19) are one group, forms current mirroring circuit；PMOS (M20, M22), NMOS tube (M21, M23) and tail current source capsule NMOS tube M24, NMOS tube M26, resistance R4, electric capacity C2, PMOS M25 are one group, the composition two grades of error amplifier circuits with miller compensation；Described adjustment pipe circuit is connected with described feedback circuit, PMOS M27 drain electrode be composed in series with resistance R5, resistance R6, and M27 source electrode connects supply voltage.Described frequency compensated circuit composes in parallel with resistance R8 after being connected with resistance R7 by electric capacity C3 again.
(3) beneficial effect
This modified model low pressure difference linear voltage regulator not only remains the feature that cost specific to linear voltage regulator is low, PSRR is high, quiescent current is low, also reduce the minimum pressure drop of linear voltage regulator, namely the difference of input minimum voltage and output voltage is reduced, reduce circuit power consumption, this modified model low pressure difference linear voltage regulator utilizes frequency acquisition and tracking simultaneously so that circuit is more stable.
Accompanying drawing explanation
Fig. 1 is modified model low differential voltage linear voltage stabilizer circuit structural representation in the embodiment of the present invention；
Fig. 2 is bandgap voltage reference structural representation in the embodiment of the present invention；
Fig. 3 is CMOS two-stage error amplifier structural representation in the embodiment of the present invention；
Fig. 4 adjusts pipe circuit and frequency compensated circuit structural representation in the embodiment of the present invention；
Detailed description of the invention
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following example are used for illustrating the present invention, but are not limited to the scope of the present invention.
The present embodiment proposes a kind of modified model low pressure difference linear voltage regulator design, as shown in Figure 1.Including: bandgap voltage reference, CMOS two-stage error amplifier, adjust pipe, frequency compensation and feedback circuit.Described band gap reference voltage source circuit connects described CMOS two-stage error amplifier circuit；Described CMOS two-stage error amplifier circuit connects described band gap reference voltage source circuit, described feedback circuit and adjustment pipe circuit；Described frequency compensated circuit connects described adjustment pipe circuit；Described adjustment pipe connects described feedback circuit.Described band gap reference voltage source circuit is used for providing the burning voltage unrelated with supply voltage and operating temperature；Described CMOS two-stage error amplifier circuit is used for producing error amplification signal；Described adjustment pipe circuit is for feedback error and reduces pressure reduction；Described frequency compensated circuit is for compensating the phase margin of circuit；Described feedback circuit is for adjusting the output voltage of low pressure difference linear voltage regulator.
In the present embodiment, band gap reference voltage source circuit have employed seven NMOS tube (M1, M3, M6, M8, M10) in Fig. 2, six PMOS (M2, M4, M5, M7, M9, M15), three PNP diodes (Q1, Q2, Q3), electric capacity (C1) structure and two resistance (R1, R2) structures.nullM2、The grid of M3 is all connected with band-gap reference Iref，M2、The drain electrode of M3 links together with the grid of M1，M2、M4、M5、M7、M9、The source class of M15 and one end of C1 are connected to supply voltage，M1、M3、M8、The source electrode of M12，Q1、Q2、The colelctor electrode of Q3 is connected to ground，The drain electrode of M1 and the other end of C1 and M4、M5、The grid of M15 links together，The drain electrode of M4、The emitter stage of Q1 and the grid of M10 connect together，The drain electrode of M5、One end of R1、The grid of M6 connects together，The other end of R1 and the emitter stage of Q2 connect together，The grid of M7 and drain electrode、The grid of M9 and the drain electrode of M6 connect together，The drain electrode of M9 connects together with the drain electrode of M10，M6、The source electrode of M10 and the drain electrode of M8 connect together，The grid of M8、The drain electrode of M12 and grid、The drain electrode of M11 and grid connect together，The drain electrode of M15 is connected with one end of R2，The other end of R2 and the emitter stage of Q3 link together.When the circuit is energized, node 1 is in electronegative potential, the grid of the PMOS M2 of coupled phase inverter is now electronegative potential, and M2 turns on thus drawing high the voltage of node 2, when node 2 voltage exceeds the threshold voltage of NMOS tube M1, M1 turns on, node 3 voltage is pulled low, the PMOS conducting being connected with node 3, and node 1 voltage is driven high, then the grid of the NMOS tube M3 of phase inverter is now high potential, due to VrefBeing generally 1.2V, more than the deflection voltage of phase inverter, now M3 pipe conducting, node 2 voltage is pulled low, thus M1 turns off, start-up circuit cuts out.In this circuit arrangement we assume that Im6=Im10(i.e. the leakage current of M6 and M10), then circuit must is fulfilled for Vm6s=Vm10s(i.e. the source potential of M6 and M10), but owing to the matching of mirror image circuit is good not in side circuit, do not reach Vm6s=Vm10s, and resistance R1And R2Ratio can vary with temperature, the reference voltage resulted in is undesirable, thus use error amplifier force Vm6s=Vm10s, thus obtaining desirable reference voltage.
In the present embodiment, CMOS two-stage error amplifier circuit have employed six NMOS tube (M16, M19, M21, M23, M24, M26) in Fig. 3, seven PMOS (M14, M15, M17, M18, M20, M22, M25), two resistance (R3, R4) and electric capacity (C2) structure.nullThe source electrode of R3 and M14 is connected，The other end of R3、M17、M20、M22、The source electrode of M25 is connected to supply voltage，M16、M19、M24、The drain electrode of M26 is connected to ground，The grid of M14、The grid of M17、Drain electrode、The source electrode of M18 connects together，The drain electrode of M14、The source electrode of M15 connects together，The grid of M15、The grid of M18、Drain electrode、The drain electrode of M19 connects together，M19、M24、The grid of M26、The grid of M16、Drain electrode、The drain electrode of M15 connects together，The grid of M22、The grid of M20、Drain electrode、The drain electrode of M21 connects together，The drain electrode of M22、The grid of M25，One end of R3 and the drain electrode of M23 connect together，M21、The source electrode of M23 and the drain electrode of M24 connect together，The grid of M21 connects the output of bandgap voltage reference，The grid of M23 connects the output of feedback circuit，R3 and C2 is connected，The other end of C2 and M25、The drain electrode of M26 is connected.M14～19 export the electric current unrelated with power supply according to current-mirror structure and to provide bias current to M24, M26, and M20～24 are the difference amplifier of standard, and input is bandgap voltage reference VrefAnd adjust the feedback voltage V in pipe circuitf, when feedback voltage changes because of load change, homogeneous tube can be exchanged by difference amplifier output voltage and be biased.R4 and C2 is the miller compensation to output limit.Namely M25, M26 form the common-source amplifier of the second level so that circuit has very strong load capacity, and the grid of last M25 is connected with adjusting pipe M27 grid, output voltage Vout.
In the present embodiment, adjust pipe and have employed a NMOS tube (M27) in Fig. 4, four resistance (R5, R6, R7, R8) and electric capacity (C3) structure with frequency compensated circuit.The grid of M27 receives the output end vo ut of error amplifier, the source electrode of M27 is connected to supply voltage, and the drain electrode of M27, one end of R5, one end of C3 and one end of R8 are connected together, and R5 and R6 is connected together, C3 and R7 is connected together, and the other end of R6, R7, R8 is connected together.C3 is bulky capacitor, and circuit can introduce a zero point, increases the phase place of 90 ° of circuit, and R7, R8 are then used to the position of zero point is modified.R5, R6 mainly regulate the size of circuit output voltage.
The modified model low pressure difference linear voltage regulator specific works process of the present invention is as follows:
1) during open circuit, node 1 is in electronegative potential, the grid of the PMOS M2 of coupled phase inverter is now electronegative potential, and M2 turns on thus drawing high the voltage of node 2, when node 2 voltage exceeds the threshold voltage of NMOS tube M1, M1 turns on, node 3 voltage is pulled low, the PMOS conducting being connected with node 3, and node 1 voltage is driven high, then the grid of the NMOS tube M3 of phase inverter is now high potential, due to VrefBeing generally 1.2V, more than the deflection voltage of phase inverter, now M3 pipe conducting, node 2 voltage is pulled low, thus M1 turns off, start-up circuit cuts out.
2) this example adopts the band-gap reference design of CMOS technique compatible, when start-up circuit normal operation, PMOS M4 and PMOS M5 grid is connected, M4 drain electrode is connected with PNP pipe Q1 emitter stage, produce electric current I1, PMOS M5 drain electrode is connected with PNP pipe Q2 emitter stage, producing electric current I2, to make M4 drain voltage be V1, M5 drain voltage is V2, when having V1=V2 only, I1=I2, due to circuit non complete symmetry, so having added two grades of error amplifiers between V1, V2, when making work, V1, V2 voltage automatic feedback regulates equal.Now owing to PMOS M15 grid is connected with M4, M5, current mirroring circuit creates PTAT (proportionaltoabsolutetemperature) electric current on M15, this electric current becomes positive temperature coefficient with temperature, again pass through PNP pipe Q3, and in negative temperature coefficient relation between the PN junction of Q3 positively biased, after have employed suitable R2 and R1 ratio and emitter area ratio, temperature coefficient can be approximately 0, now output voltage VrefTemperature independent, for 1.2V.
3) this example have employed the dual-stage amplifier of CMOS difference amplifier and common-source amplifier composition.M14～19 export the electric current unrelated with power supply according to current-mirror structure and to provide bias current to M24, M26, and M20～24 are the difference amplifier of standard, and input is bandgap voltage reference output VrefAnd adjust the feedback voltage V in pipe circuitf, when feedback voltage changes because of load change, homogeneous tube can be exchanged by difference amplifier output voltage and be biased.R4 and C2 is the miller compensation to output limit.Namely M25, M26 form the common-source amplifier of the second level so that circuit has very strong load capacity, and the grid of last M25 is connected with adjusting pipe M27 grid, output voltage Vout.
4) when ESR compensates circuit work, the series equivalent resistance of electric capacity C3 C3 series resistance R7, R8 in parallel circuit in introduce a zero point, add phase margin, improve circuit stability.
Embodiment of above is merely to illustrate the present invention; and and the restriction of non-invention; those of ordinary skill about technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all equivalent technical schemes fall within scope of the invention, and the scope of patent protection of the present invention should be defined by the claims.
Claims (1)
1. a modified model low pressure difference linear voltage regulator, including: band gap reference voltage source circuit, CMOS two-stage error amplifier circuit, adjustment pipe, frequency compensated circuit and feedback circuit, it is characterised in that:
Described band gap reference voltage source circuit connects CMOS two-stage error amplifier circuit；Described CMOS two-stage error amplifier circuit connects band gap reference voltage source circuit, feedback circuit and adjustment pipe；Frequency compensated circuit connects described adjustment pipe circuit；Described adjustment pipe connects described feedback circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610312217.5A CN105807842A (en) | 2016-05-12 | 2016-05-12 | Improved type low-dropout linear regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610312217.5A CN105807842A (en) | 2016-05-12 | 2016-05-12 | Improved type low-dropout linear regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105807842A true CN105807842A (en) | 2016-07-27 |
Family
ID=56455811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610312217.5A Pending CN105807842A (en) | 2016-05-12 | 2016-05-12 | Improved type low-dropout linear regulator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105807842A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519789A (en) * | 2017-04-11 | 2018-09-11 | 长泰品原电子科技有限公司 | A kind of reference voltage circuit and programmable power supply |
| CN110794907A (en) * | 2019-08-20 | 2020-02-14 | 上海禾赛光电科技有限公司 | Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system |
| CN112558668A (en) * | 2020-12-08 | 2021-03-26 | 大连民族大学 | LDO circuit based on chopping technology |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518737B1 (en) * | 2001-09-28 | 2003-02-11 | Catalyst Semiconductor, Inc. | Low dropout voltage regulator with non-miller frequency compensation |
| CN101339443A (en) * | 2008-08-08 | 2009-01-07 | 武汉大学 | Broad output current scope low pressure difference linear manostat |
| CN103092241A (en) * | 2011-10-27 | 2013-05-08 | 厦门立昂电子科技有限公司 | Mixed compensating type high-stability LDO (low-dropout regulator) chip circuit |
| CN103309384A (en) * | 2012-03-16 | 2013-09-18 | 擎泰科技股份有限公司 | Voltage regulator with adaptive miller compensation |
| US8970188B2 (en) * | 2013-04-05 | 2015-03-03 | Synaptics Incorporated | Adaptive frequency compensation for high speed linear voltage regulator |
-
2016
- 2016-05-12 CN CN201610312217.5A patent/CN105807842A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518737B1 (en) * | 2001-09-28 | 2003-02-11 | Catalyst Semiconductor, Inc. | Low dropout voltage regulator with non-miller frequency compensation |
| CN101339443A (en) * | 2008-08-08 | 2009-01-07 | 武汉大学 | Broad output current scope low pressure difference linear manostat |
| CN103092241A (en) * | 2011-10-27 | 2013-05-08 | 厦门立昂电子科技有限公司 | Mixed compensating type high-stability LDO (low-dropout regulator) chip circuit |
| CN103309384A (en) * | 2012-03-16 | 2013-09-18 | 擎泰科技股份有限公司 | Voltage regulator with adaptive miller compensation |
| US8970188B2 (en) * | 2013-04-05 | 2015-03-03 | Synaptics Incorporated | Adaptive frequency compensation for high speed linear voltage regulator |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519789A (en) * | 2017-04-11 | 2018-09-11 | 长泰品原电子科技有限公司 | A kind of reference voltage circuit and programmable power supply |
| CN108693910A (en) * | 2017-04-11 | 2018-10-23 | 段遵虎 | A kind of programmable power supply including reference voltage circuit |
| CN110794907A (en) * | 2019-08-20 | 2020-02-14 | 上海禾赛光电科技有限公司 | Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system |
| CN110794907B (en) * | 2019-08-20 | 2022-06-03 | 上海禾赛科技有限公司 | Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system |
| CN112558668A (en) * | 2020-12-08 | 2021-03-26 | 大连民族大学 | LDO circuit based on chopping technology |
| CN112558668B (en) * | 2020-12-08 | 2022-05-20 | 大连民族大学 | LDO circuit based on chopping technology |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100504710C (en) | Band-gap reference source with high power supply restraint | |
| WO2017049840A1 (en) | Band-gap reference voltage source with high power supply rejection ratio | |
| CN103389769B (en) | Band-gap reference voltage source with high power supply rejection ratio | |
| CN109976424B (en) | Non-capacitor type low dropout linear voltage regulator | |
| CN104679088A (en) | Low dropout linear regulator and frequency compensating circuit thereof | |
| CN101727119B (en) | Low-dropout linear voltage source with effective compensation | |
| CN103345290B (en) | Band-gap reference voltage source with high power source restraining and low technology deviation | |
| CN207488871U (en) | A kind of CMOS low pressure difference linear voltage regulators using novel buffer | |
| CN104699162B (en) | A kind of low pressure difference linear voltage regulator of quick response | |
| CN102609031B (en) | Highly integrated low-power reference source | |
| CN102882482B (en) | Ultralow power consumption error amplifier | |
| CN101957625B (en) | Low dropout linear voltage regulator for driving nF-stage load | |
| CN105807842A (en) | Improved type low-dropout linear regulator | |
| CN202110463U (en) | Variable curvature-compensated band gap voltage reference source | |
| CN106094966A (en) | A kind of linear voltage regulator of wideband high PSRR | |
| CN201936216U (en) | Reference voltage source with wide input voltage and high power supply rejection ratio | |
| CN106444947B (en) | It is a kind of for the compensation circuit without capacitive LDO | |
| CN201097250Y (en) | High-power restraint standard source with gap | |
| CN114204805B (en) | Power rail circuit for high-voltage Buck converter | |
| CN204480101U (en) | A kind of low pressure difference linear voltage regulator of quick response | |
| CN102393779B (en) | LDO (low dropout regulator) circuit with compensation circuit | |
| CN103163926A (en) | High-accuracy low drop-out voltage regulator | |
| CN204102018U (en) | A kind of fast transient response low pressure difference linear voltage regulator | |
| CN114967811B (en) | Off-chip capacitor LDO (low dropout regulator) capable of improving PSR (power supply rejection) performance | |
| CN110879629A (en) | Low dropout linear voltage stabilizing circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160727 |