CN105807263B - A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing - Google Patents
A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing Download PDFInfo
- Publication number
- CN105807263B CN105807263B CN201610181834.6A CN201610181834A CN105807263B CN 105807263 B CN105807263 B CN 105807263B CN 201610181834 A CN201610181834 A CN 201610181834A CN 105807263 B CN105807263 B CN 105807263B
- Authority
- CN
- China
- Prior art keywords
- fpga
- signal
- module
- network interface
- host computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
Abstract
A kind of FPGA portion of the present invention reconstructs device and implementation method in Radar Signal Processing, and the method reconstructed using FPGA portion realizes the switching at runtime in radar signal between different wave.The device includes fpga core chip and its peripheral circuit, ADC sampling A/D chips and its peripheral circuit, network interface chip circuit, power circuit.The implementation method is：Step 1：Analyze under multiple-working mode identical handling process and different handling processes in FPGA programs.Step 2：The FPGA for writing modules realizes algorithm.Step 3：Region distribution is carried out using palnahead12.4 softwares, generates FPGA programming file.Step 4：Host computer transmitting portion configuration file carries out the switch test of functional mode.The present invention uses the method for partially dynamical reconfiguration to realize different functions on a hardware platform, and the switching of function is real-time, and reduces resource consumption, reduces power consumption.
Description
【Technical field】
The present invention reconstructs the implementation method in Radar Signal Processing for a kind of FPGA portion, and this method uses FPGA portion
The function of reconstruct can carry out switching at runtime between many kinds of radar mode of operation, belong to digital processing field.
【Background technology】
FPGA allows it to easily to carry out user to determine with its highdensity logical resource and abundant hardware module
Make and reconfigure.Dynamic reconfigurable is a kind of FPGA key characteristic, and it can be such that FPGA enters while normal work
Row is reconfigured to realize the change of logic function.Dynamic restructuring is entirely set by the logical resource for the FPGA that is time-multiplexed to improve
The resource utilization of meter, reduce system power dissipation.
FPGA restructurals can be divided into dynamic restructuring and static reconfiguration from reconstruct mode, and static reconfiguration can only stop in system
It could be carried out when only running, relative dynamic, which reconstructs, larger configuration time slot, and flexibility is low.Dynamic restructuring is according to configuring area
Big I is divided into dynamic total reconfiguration and the class of partially dynamical reconfiguration two, and partially dynamical reconfiguration can configure the logic in local FPGA
Function, the sequential in whole system can have continuity, and dynamic total reconfiguration is that whole FPGA is configured, in configuration shape
The logical miss of system is unpredictable under state, and the sequential of whole system will appear from mark of break.Partially dynamical reconfiguration is global compared to dynamic
It is relatively small to reconstruct its change region, there is smaller configuration bit stream file, configuration time slot is also relative to diminish.Dynamic part weight
Structure technology is modified in the case of being currently running to hardware system, realizes different logic functions, shortens the construction cycle,
There is good application prospect.
The resource utilization that partially dynamical reconfiguration can largely improve FPGA reduces system power dissipation, its advantage
Have：
(1) resource utilization is improved.Generally hardware resource profit is represented with the calculating task density of reconfigurable logic device
With rate, partial reconfiguration technology improves resource utilization by the time division multiplexing to resource.Logical common configuration is in restructural
Stock number that calculating task on logical device takes and the ratio of the logical resource amount of whole reconfigurable logic devices calculate
Resource utilization.
(2) the system reconfiguration time is shortened.When FPGA is reconfigured, configuration data stream smaller then required setup time
It is fewer.When being reconstructed, partial reconfiguration technology is only reconfigured to Local resource, and existing perform is appointed
Reconstruct is sightless for business, so can reduce the system reconfiguration time in theory.
(3) stability of a system is improved.When system goes wrong, partial reconfiguration technology can be carried out hardware partition
Isolation, by being reconfigured to remaining logical resource, overall task is completed using part resource, so as to improve the steady of system
It is qualitative.
With the requirement of real-time more and more higher of Radar Signal Processing, signal transacting bandwidth is also more and more wider, and this is to FPGA
Performance it is also proposed higher requirement.For the higher FPGA of performance, its internal logical resource is relatively also more, so right
Some problems will be run into FPGA design：
(1) the wiring difficulty of FPGA internal logic resources improves, and the difference of routing strategy has very to fpga logic and performance
Big influence, in general FPGA wiring difficulty and die size are into a square ratio；
(2) FPGA logical resource occupancy increases and increased also with the difficulty of actual system design；
(3) FPGA spoilage carries also with the increase of its internal logic resource quantity and the increase of wiring difficulty
Rise.
FPGA dynamic restructurings are exactly that its logic function is dynamically changed on FPGA hardware resource, meet different circuit systems
The functional requirement of system.Dynamic restructuring can be in resource than on relatively limited FPGA, being time-multiplexed in fact by being realized to hardware resource
The project of fairly large resource is now needed, FPGA resource utilization is so not only greatly improved but also saves system cost,
Reduce the energy consumption of system.
For situation above and actual items demand, a kind of FPGA portion reconstruct of my invention is in Radar Signal Processing
In device and implementation method.This platform can handle different wave (such as linear frequency modulation ripple, step frequency in radar signal
Ripple, frequency shift keying ripple, phase-shift keying (PSK) ripple, amplitude keying ripple), can be according to the different processing mould of different waveform switching at runtime
Formula.The system is using FPGA as core processing device, comprising two-way ADC sampling modules and all the way network interface communication module, ADC sampling moulds
Block is sampled to the guinea pig waveform of input, and network interface communication module receiving portion configuration file is simultaneously matched somebody with somebody again to FPGA
Put, realize the processing to different radar waveforms, waveform processing result is transferred to host computer by network interface communication module.
【The content of the invention】
It is an object of the invention to provide a kind of FPGA portion to reconstruct device and implementation method in Radar Signal Processing.
The method reconstructed using FPGA portion realizes different wave in radar signal (such as linear frequency modulation ripple, step frequency ripple, frequency shift keying
Ripple, phase-shift keying (PSK) ripple, amplitude keying ripple) between switching at runtime.The present invention uses the ISE12.4 development environments of Xilinx companies
FPGA Software for Design is carried out, and region division is carried out using Planahead12.4 and realizes partial reconfiguration, is compiled using VC++6.0
Pc control procedure is write to be controlled partial reconfiguration.
A kind of FPGA portion of the present invention reconstructs device and implementation method in Radar Signal Processing, and the implementation of this method is
Based on FPGA hardware system and device, the FPGA hardware include fpga core chip and its peripheral circuit, ADC sampling A/D chips and its
Peripheral circuit, network interface chip circuit, power circuit.The installation drawing of system is as shown in Figure 1.
Fpga core chip is responsible for the realization of all logic functions.FPGA control ADC chips are sampled, and receive sampling
Data, (pulse compression of linear frequency modulation ripple, the pulse compression of step frequency ripple, frequency are handled sampled data inside FPGA
Move the demodulation of keying wave, the demodulation of phase-shift keying (PSK) ripple, the demodulation of amplitude keying ripple).FPGA controls network interface chip realizes host computer
Communication between FPGA：Radar waveform result after FPGA processing is transferred to host computer by network interface, while in FPGA receptions
The partial profiles and order that position machine is sent, such as mode handover command, start work order, system reset command.
That fpga chip is selected is the Virtex-6XC6VLX75T of Xilinx companies.The Virtex- that Xilinx companies release
6 Series FPGAs include some new, advanced characteristics.The logic of the FPGA institutes band of Virtex-6 series, Digital Signal Processing, height
Speed connection and microprocessor function are high performance logic design, High Performance DSP design and high performance embedded system design provide
Best solution.Virtex-6 series uses third generation ASMBLTM (high level silicon wafer composite module) pillar framework, includes
Three different subfamilies, each subfamily include different property combinations, can meet a variety of higher-order logic design requirements.
Three kinds of subfamilies of Virtex-6 series are LXT, SXT, HXT respectively.Wherein LXT has the high-performance of advanced serial connection function
Logic；SXT has the peak signal processing function of advanced serial connection function；HXT has the highest bandwidth of serial connection function.
In addition, the FPGA of Virtex-6 series employs the 40nm process for copper technologies at tip, providing one kind for customization asic technology can
The selection scheme of programming, its inside include multiple system-level blocks.
The computing that FPGA need not be complicated in the present invention, can meet to require from LXT.FPGA is only responsible for ADC sampling controls
The functions such as system, network interface communication, radar waveform processing, so from the XC6VLX75T of Virtex-6 series, its resource disclosure satisfy that
Design requirement.
XC6VLX75T main features：
1) 11640 slice；
2) 6 MMCM (Mixed-Mode Clock Managers) modules；
3)5616K bits RAM；
4) 360 general purpose Is/O pins；
5) 4 Ethernet MACs.
FPGA peripheral circuit includes electric source filter circuit, clock circuit, configuration mode control circuit and program storage
FLASH circuits.Electric source filter circuit is for the voltage smaller, stable to FPGA offer noises.Clock circuit is the normal of FPGA
Work provides required clock signal, and clock circuit is generally crystal oscillator, and it produces the frequency required for FPGA.FPGA's
Various ways are configured with, can be selected by configuring the level of three configuration pins.FPGA its internal cloth after power is turned off
Line logic can be eliminated, and upper electricity is required for reconfiguring every time, it is therefore desirable to is cured to the configuration file of FPGA Program Generatings
In program storage FLASH, upper electric FPGA reads configuration file from the FLASH and configured every time.
The FPGA program storages FLASH that the design selects is the XCF128X that Xilinx companies are recommended, and this FLASH is
The supporting program storage of Virtex-5 and Virtex-6 Series FPGAs.The capacity of the chip is 128Mbit, and configured rate is theoretical
Highest can arrive 800Mb/s.
ADC sampling A/D chips are responsible for sampling external input signal, and analog signal is converted to data signal, sampled
The data signal arrived, which is sent into inside FPGA, carries out digital processing.The present invention is using two panels ADC sampling A/D chips to two-way radar waveform
It is acquired.The input signal of ADC sampling A/D chips is differential signal, it is therefore desirable in signal input part by the single-ended signal of input
Switch to corresponding differential signal.The signal that ADC is converted is transferred to FPGA in a manner of LVDS DDR.
ADC peripheral circuits include single-ended transfer difference circuit, signal level shift circuit.Single-ended transfer difference used in the present invention
Conversion chip model AD8138, the single-ended radar signal of input can be converted to corresponding differential signal.Signal level turns
It is in order to which the control signal for+2.5V for exporting FPGA is converted to the+3.3V level with ADC matchings to change circuit.
The conversion chip is the AD8138 of Analog Devices companies, and he is responsible for being converted to the single-ended signal of input
Differential signal, its key property are as follows：
1) simple realization single-ended signal switchs to both-end differential signal；
2) it is controllable outside gain；
3)-three dB bandwidth 320MHz.
The AD is the ADS5562 of Texas Instruments companies, and it is responsible for the analog signal of input being converted to number
Word signal, its key property are as follows：
1) use+3.3V analog powers and+3.3V digital powers are powered；
2) binary channels while 80Msps, 16 AD are sampled, aims at and high frequency, wide dynamic range signals are entered
Digitized is handled and designed；
3) it is very good to low-frequency noise rejection；
4) numeral output includes Double Data Rate LVDS DDR and parallel C MOS patterns；
5) external reference voltage and internal reference voltage are supported while.
Network interface chip is the kernel control chip of network interface communication circuit module, and it is as the bridge between FPGA and host computer
Beam, it is responsible for completing the data transfer between them.Network interface chip upper layer signal is connected with FPGA by GMI interfaces；Its bottom is believed
Number it is connected with the RJ45 connector of networked physics layer；FPGA controls network interface chip is operated in kilomega network pattern.After FPGA processing
Radar waveform result is transferred to host computer by network interface, while FPGA receives the partial profiles that host computer is sent by network interface
And order, such as mode handover command, start work order, system reset command.
The network interface chip is 88E1111-BAB1, and its key property is as follows：
1) compatible 10/100/1000BASE-T IEEE 802.3；
2) it is internally integrated 1.25GHz SERDES；
3) low power consuming pattern；
4) three local loopback interfaces are diagnosed；
5) four kinds of RGMII clock modules.
Power circuit provides voltage needed for work for whole system.System input voltage+5V, mainly by 5 Power converts
Chip (three PTH05000WAD, a piece of LM1085 and a piece of AMS1117ADJ) is converted to other voltages needed for system.Three
+ 5V voltages are respectively converted into D+3.3V, D+1.0V and D+2.5V required for system by PTH05000WAD；LM1085 provides D+
1.8V；AMS1117 provides A+3.3V, and these power supplys are respectively supplied to fpga chip (D+2.5V, D+1.0V), program storage
FLASH (D+2.5V, D+1.8V), clock provide source (D+2.5V), ADC sampling A/D chips (D+3.3V, A+3.3V), network interface chip (D
+2.5V、D+1.0V)。
PTH05000WAD key property is as follows：
1) input voltage range 4.5V to 5.5V；
2) highest output current 6A, out-put supply scope 0.9V to 3.6V；
3) overcurrent and overheating protection；
4) output voltage overvoltage protection；
5) efficiency is up to 94%.
LM1085 key property is as follows：
1) input voltage range is big, can be to 7V by 4.5V；
2) output current 3A, output voltage are fixed or adjustable；
3) efficient linear Power convert；
4) SOT223 is encapsulated.
AMS1117 key property is as follows：
1) input voltage highest 20V；
2) output current 3A, out-put supply scope 1.25V to 13.8V；
3) efficient linear Power convert；
4) SOT223 is encapsulated.
(2) a kind of FPGA portion of my invention reconstructs device and implementation method in Radar Signal Processing, is summarized as follows：
A kind of device of the FPGA portion reconstruct of the present invention in Radar Signal Processing can be run with implementation method in FPGA
During, receive the partial profiles that host computer is sent and FPGA is carried out partly to reconfigure, dynamic changes FPGA's in real time
Logic function is handled radar waveform (pulse compression of linear frequency modulation ripple, the pulse compression of step frequency ripple, frequency displacement key
Control the demodulation of ripple, the demodulation of phase-shift keying (PSK) ripple, the demodulation of amplitude keying ripple), and result is sent to by network interface upper
Machine.Logical resource inside FPGA is divided into dynamic area and static region, and the logic function of static region keeps constant, dynamic
The logic function in region can be changed in real time by loading new configuration file.It can thus realize on the same hardware platform not
The switching at runtime of congenerous.
A kind of FPGA portion of the present invention reconstructs device and implementation method in Radar Signal Processing, and this method includes following
Several steps：
Step 1：Analyze under multiple-working mode identical handling process and different handling processes in FPGA programs.This
Invent a kind of FPGA portion and reconstruct device and implementation method in Radar Signal Processing, its function is exactly to receive host computer hair
The partial profiles sent, part is carried out to FPGA and reconfigured, dynamic handles many kinds of radar waveform and result is passed through into net
Mouth is sent to host computer.
By analysis, the processing to radar waveform is required for sampling by ADC, converts analog signals into data signal simultaneously
Handled inside FPGA；The Processing Algorithm of different radar waveforms is different；Result after processing is uploaded to by network interface
Host computer；The partial profiles that FPGA receives host computer transmission by network interface reconfigure to FPGA.Therefore different radars
The processing of waveform includes identical handling process：ADC samples to the analog signal of input, and FPGA is by network interface to host computer
Transmitted waveform result, host computer is by network interface to FPGA hop configuration files.Difference is different radar waves
The Processing Algorithm of shape is different.Handling process (the arteries and veins of linear frequency modulation ripple according to different wave is just needed when writing FPGA programs
Punching press contracting, the pulse compression of step frequency ripple, the demodulation of frequency shift keying ripple, the demodulation of phase-shift keying (PSK) ripple, the solution of amplitude keying ripple
Adjust) it is designed, the algorithm of different radar waveforms needs individually to write.
Step 2：The FPGA for writing modules realizes algorithm.The function mould of the invention designed is understood by above-mentioned analysis
Block is broadly divided into following four：ADC acquisition modules, part configuration module, waveform processing module, network interface transport module.
(1) design of ADC acquisition modules.The functions of modules is mainly controls of the FPGA to ADS5562 chips, FPGA pairs
ADS5562 control is exactly to read change data after converting every time.The data that ADS5562 is returned are LVDS DDR formats
, the differential data of return is converted to single ended data by FPGA, so as to the processing of follow-up process.ADS5562 control sequential is such as
Shown in Fig. 2, FPGA and ADS5562 line control are as shown in Figure 3.The input signal of ADS5562 sampling A/D chips is differential signal,
Therefore need that the single-ended signal of input is switched into corresponding differential signal in signal input part.The signal that ADC is converted with
LVDS DDR mode is transferred to FPGA.
(2) design of part configuration module.Cutting for different mode is realized using the method for FPGA portion reconstruct in the present invention
Change, FPGA uses the mode achievement unit of ICAP (Internal Configuration Access Port, inside configuration interface)
Divide reconstruct.The configuration data of dynamic restructuring can dynamically be reconfigured by ICAP interfaces to FPGA.ICAP interfaces such as Fig. 4
Shown, it includes single data input bus (DIB) and data-out bus, and the width of these data/address bus can be configured, right
In the FPGA of Virtex-5 and Virtex-6 series, ICAP data-bus width can be selected as 8,16 or 32；
ICAP interface clock needs outside offer, and highest can be with the stream of control data no more than 100MHz, control signal " WRITE "
To；" CE " signal can enable ICAP.ICAP data-bus width is arranged to 32 by the present invention, and configurable clock generator is arranged to
100MHz, the configured rate so set are 3200Mbits/s.
When partial reconfiguration is realized, it is necessary first under the control at host computer VC interfaces, partial reconfiguration file is led to
Cross network interface and be sent to FPGA, FPGA receives partial profiles and stored into internal RAM, and FPGA detects part configuration text
During the end mark of part, stop writing number into RAM, start simultaneously at the data that partial profiles are read from RAM, and be sent to
ICAP interfaces, as shown in Figure 5.
Controls of the FPGA to ICAP is realized by way of state machine, as shown in Figure 6.When state machine receives the life of reconstruct
When making, " WRITE " signal is dragged down first, enabled ICAP writes function, drags down " CE " signal in next rising edge clock, makes
Can ICAP, subsequently enter ICAP states, in a state just according to clock frequency, transmitting portion reconstructs data, when detecting portion
When dividing the end mark of reconstruct configuration file, jumped out from ICAP states, now FPGA part configuration is completed.
(3) design of waveform processing module.FPGA is mainly designed to at different wave to waveform processing module
Reason, including the pulse compression of linear frequency modulation ripple, the pulse compression of step frequency ripple, the demodulation of frequency shift keying ripple, phase-shift keying (PSK) ripple
Demodulation, the demodulation of amplitude keying ripple.
(5) design of network interface transport module.The module is responsible for the data transfer between FPGA and host computer, including FPGA will
Data packing after processing uploads to host computer, while partial profiles are transferred to FPGA and realize part weight by host computer
Structure, in addition host computer send control command to FPGA also by network interface, such as mode handover command, to start work order, system multiple
Order of the bit.
Step 3：Region distribution is carried out using palnahead12.4 softwares, generates FPGA programming file.
(1) it is raw before region distribution is carried out using palnahead12.4, it is necessary in FPGA development environments ISE12.4
Into ngc files.The ADC acquisition modules in FPGA programs, part configuration module, waveform processing module, network interface are passed in the present invention
Defeated module, artificially it is divided into static module (ADC acquisition modules, part configuration module, network interface transport module) and dynamic module (ripple
Shape processing module).Need dynamic module (waveform processing module) being arranged to top layer mould in project file in ISE12.4
Block, and " add IO BUF " are not selected, then the ngc texts of comprehensive generation dynamic module (waveform processing module) in synthesis options
Part, this document can be used in the planahead12.4 below.Except the ngc texts of generation dynamic module (waveform processing module)
Part also needs to generate the ngc files of top-level module, and the generation of top-level module ngc files is needed dynamic module (waveform processing mould
Block) code file deleted from engineering, to the calling of the module in a prewired program, it is comprehensive equally only to carry out the first step here
Close, need exist for choosing and " add IO BUF ", generate corresponding ngc files.
In the present invention a variety of different radar waveforms are handled with (pulse compression of linear frequency modulation ripple, step frequency ripple
Pulse compression, the demodulation of frequency shift keying ripple, the demodulation of phase-shift keying (PSK) ripple, the demodulation of amplitude keying ripple), to any of which waveform
Processing routine will according to above-mentioned steps generate dynamic module (waveform processing module) ngc files and static module ADC adopt
Collect module, part configuration module, network interface transport module) ngc files.
(2) can is generated after these ngc files in planahead12.4 to dynamic module (waveform processing module)
Carry out region division.Newly-built one new planahead12.4 engineering is needed exist for, needs to hook when engineering attribute is selected
Choose and " option just occurs after the license of set PR project ", only mounting portion reconstruct.Below with regard to needing to press
Add corresponding file according to prompting, it is necessary first to addition be top-level module ngc files, the following corresponding pipe of prompting addition
Pin unbound document (ucf files).Next just need to be configured this dynamic module (waveform processing module).Firstly the need of
The module is arranged to reconfigurable module, the dynamic module (waveform processing module) that above generates then is added in the module
Ngc files, with regard to needing to carry out region division to the dynamic module (waveform processing module) after addition, selected FPGA's
Region need to meet in dynamic module (waveform processing module) required for logical resource, including slice, BUFO, BUFR, DCI,
DSP48, IOB, RSMB18, RAMB36 etc..Need to detect by drc after selecting good region, can exists after detection is out of question
It is configured in planahead12.4, by the configuration text that dynamic module (waveform processing module) can be generated after placement-and-routing
Part and global configuration file.There are these file cans to realize that the dynamic part of fpga logic function reconfigures.
(3) after above-mentioned steps completion, global configuration file and partial profiles have all generated, but need to this
A little files carry out validation checking.Detection method is exactly that on-line loaded is tested, and verification portion configuration file can be correctly complete
Into recombination function.
Step 4：Host computer transmitting portion configuration file carries out the switch test of functional mode.
Function switch test can be carried out by host computer VC interfaces.In the setting at VC interfaces, it is necessary first to initialize
Network interface communicates.Then selected section configuration file is transmitted, can automatic detection part configuration text when option and installment file
The validity of part is simultaneously judged.If the effective can of partial profiles is transmitted to FPGA, FPGA receives part and matched somebody with somebody
Put file to be first stored in RAM afterwards, detect that configuration file proceeds by FPGA configuration after finishing receiving.
Advantage and beneficial effect of the present invention are：
【Brief description of the drawings】
Fig. 1 is system and device figure.
Fig. 2 is ADS5562 control sequential.
Fig. 3 is FPGA and ADS5562 line control figure.
Fig. 4 is ICAP interfaces.
Fig. 5 is access partial profiles state machine.
Fig. 6 is ICAP state of a control machines.
Fig. 7 is linear FM signal process chart.
Fig. 8 is step frequency signal handling process.
【Embodiment】
A kind of FPGA portion of the present invention reconstructs device and implementation method in Radar Signal Processing, can be used for radar letter
The processing of linear frequency-modulated wave and step frequency ripple in number, the processing of both waveforms can carry out reality by way of partial reconfiguration
When switch.Embodiment mainly comprises the steps of：
Step 1：The handling process of linear both radar waveforms of frequency-modulated wave and step frequency ripple is analyzed, determines FPGA journeys
Identical handling process and different handling processes in sequence.By analysis, to linear frequency modulation ripple and step frequency ripple both thunders
Processing up to waveform is required for sampling by ADC, converts analog signals into data signal and is handled inside FPGA；This
The algorithm of two kinds of radar waveform processing is different；Result after processing uploads to host computer by network interface；FPGA passes through network interface
The partial profiles that host computer is sent are received to reconfigure FPGA.Therefore to linear frequency modulation ripple and step frequency ripple this two
The processing of kind radar waveform includes identical handling process：The analog signal of input is sampled by ADC, FPGA passes through net
Mouth passes through network interface hop configuration file to host computer transmitted waveform result.Difference is both radar waves
The Processing Algorithm of shape is different.Just needed when writing FPGA programs according to linear frequency modulation ripple and step frequency ripple both different ripples
The handling process of shape is designed.
Step 2：The FPGA for writing modules realizes algorithm.The function mould of the invention designed is understood by above-mentioned analysis
Block is broadly divided into following five：ADC acquisition modules, part configuration module, linear frequency modulation ripple processing module, the processing of step frequency ripple
Module, network interface transport module.
(1) design of ADC acquisition modules.The main FPGA of the functions of modules is the control to ADS5562 chips, FPGA pairs
ADS5562 control is exactly to read change data after converting every time.The data that ADS5562 is returned are LVDS DDR formats
, the differential data of return is converted to single ended data by FPGA, so as to the processing of follow-up process.ADS5562 control sequential is such as
Shown in Fig. 2, FPGA and ADS5562 line control are as shown in Figure 3.The input signal of ADS5562 sampling A/D chips is differential signal,
Therefore need that the single-ended signal of input is switched into corresponding differential signal in signal input part.The signal that ADC is converted with
LDVS DDR mode is transferred to FPGA.
(2) design of part configuration module.Cutting for different mode is realized using the method for FPGA portion reconstruct in the present invention
Change, FPGA uses the mode achievement unit of ICAP (Internal Configuration Access Port, inside configuration interface)
Divide reconstruct.The configuration data of dynamic restructuring can dynamically be reconfigured by ICAP interfaces to FPGA.ICAP interfaces such as Fig. 4
Shown, it includes single data input bus (DIB) and data-out bus, and the width of these data/address bus can be configured, right
In the FPGA of Virtex-5 and Virtex-6 series, ICAP data-bus width can be selected as 8,16 or 32；
ICAP interface clock needs outside offer, and highest can be with the stream of control data no more than 100MHz, control signal " WRITE "
To；" CE " signal can enable ICAP.ICAP data-bus width is arranged to 32 by the present invention, and configurable clock generator is arranged to
100MHz, such configured rate are 3200Mbits/s.
When with partial reconfiguration is realized, it is necessary first to which under the control at host computer VC interfaces, host computer passes through network interface
Partial reconfiguration file is sent to FPGA, FPGA receives partial profiles and stored into internal RAM, and FPGA detects portion
When dividing the end mark of configuration file, stop writing number into RAM, start simultaneously at the data that partial profiles are read from RAM,
And ICAP interfaces are sent to, as shown in Figure 5.
Controls of the FPGA to ICAP is realized by way of state machine, as shown in Figure 6.When state machine receives the life of reconstruct
When making, " WRITE " signal is dragged down first, enabled ICAP writes function, drags down " CE " signal in next rising edge clock, makes
Can ICAP, subsequently enter ICAP states, in a state just according to clock frequency, transmitting portion reconstructs data, when detecting portion
When dividing the end mark of reconstruct configuration file, jumped out from ICAP states, now FPGA part configuration is completed.
(3) design of linear frequency modulation ripple processing module.The processing of linear FM signal is broadly divided into Digital Down Convert, pulse
The flows such as compression.The purpose of Digital Down Convert is to be transformed to be appropriate for subsequent treatment by the digital intermediate frequency signal after sampling
Baseband digital signal.Baseband signal can be realized pulse compression by pulse compression by the method for matched filter, such as
Shown in Fig. 7.The baseband signal of time domain is converted to the signal of frequency domain using FFT first, then carries out CM with matching factor
Method, it will finally multiply result again and carry out IFFT, frequency-region signal is gone back into time-domain signal.
(4) design of step frequency ripple processing module.The handling process of step frequency ripple is similar with linear frequency modulation ripple, first
Intermediate-freuqncy signal progress Digital Down Convert is converted into baseband signal, IFFT is carried out after obtained two ways of digital signals.Step frequency
The sampling of N number of stepped frequency radar is received in each range gate of ripple, can be written as range-pulse matrix.For it is above away from
From-dither matrix, by each column data, i.e., IFFT is carried out relative to N number of frequency stepped pulse trains data of specific range door, so that it may
So that the specific range door is resolved into N number of equal sub- range gate, the figure being made up of N number of sub- range gate is exactly high-resolution one
Range Profile is tieed up, represents the reflectivity distribution of target different piece in a range gate.M (the samplings in a pulse repetition period
Number) group Range Profile splice after extracting valid data can obtain whole one-dimensional range profile, so as to know to target
Not, while the range information of target is obtained.Data after above-mentioned processing are transferred to network interface transmission after simple arrange
Module, and then host computer is uploaded to, whole step frequency ripple handling process is as shown in Figure 8.
(5) design of network interface transport module.The module is responsible for the data transfer between FPGA and host computer, including FPGA will
Data packing after processing uploads to host computer, while partial profiles are transferred to FPGA and realize part weight by host computer
Structure, in addition host computer send control command to FPGA also by network interface, such as mode handover command, to start work order, system multiple
Order of the bit.
Step 3：Region distribution is carried out using palnahead12.4 softwares, generates FPGA programming file.
(1) it is raw before region distribution is carried out using palnahead12.4, it is necessary in FPGA development environments ISE12.4
Into ngc files.In the present invention by the ADC acquisition modules in FPGA programs, part configuration module, linear frequency modulation ripple processing module,
Step frequency ripple processing module, network interface transport module, be artificially divided into static module (ADC acquisition modules, part configuration module,
Network interface transport module) and dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module).In ISE12.4
Need dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module) being arranged to top-level module in setting, and
" add IO BUF " are not selected, then comprehensive generation dynamic module (linear frequency modulation ripple processing module, Step Frequency in synthesis options
Rate ripple processing module) ngc files, this document can use in the planahead12.4 below.Except generating dynamic module
The ngc files of (linear frequency modulation ripple processing module, step frequency ripple processing module) also need to generate the ngc files of top-level module,
The generation of top-level module ngc files is needed dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module)
Code file is deleted from engineering, to the calling of the module in a prewired program, equally only carries out first step synthesis here, here
Need to choose and " add IO BUF ", generate corresponding ngc files.
(2) can is generated after these ngc files in planahead12.4 to dynamic module (at linear frequency modulation ripple
Manage module, step frequency ripple processing module) carry out region division.Newly-built one new planahead12.4 engineering is needed exist for,
Need to choose " after the license of set PR project ", only mounting portion reconstruct when engineering attribute is selected
The option just occurs.Just need to add corresponding file according to prompting below, it is necessary first to addition be top-level module ngc
Corresponding pin unbound document (ucf files) is added in file, next prompting.Next just need this dynamic module (line
Property frequency-modulated wave processing module, step frequency ripple processing module) it is configured.Reconfigurable module is arranged to firstly the need of by the module
Then the dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module) that above generates is added in the module
Ngc files, with regard to needing to carry out the dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module) after addition
Region division, selected FPGA region need to meet dynamic module (at linear frequency modulation ripple processing module, step frequency ripple
Manage module) in required for logical resource, including slice, BUFO, BUFR, DCI, DSP48, IOB, RSMB18, RAMB36 etc..
Need to detect by drc after selecting good region, can is configured in planahead12.4 after detection is out of question, is passed through
The configuration file of dynamic module (linear frequency modulation ripple processing module, step frequency ripple processing module) can be generated afterwards by crossing placement-and-routing
And global configuration file.There are these file cans to realize that the dynamic part of fpga logic function reconfigures.
(3) in the case where above-mentioned steps are completed, global configuration file and partial profiles have all generated, but need
Validation checking is carried out to these files.Detection method is exactly that on-line loaded is tested, and verification portion configuration file can be just
Really complete recombination function.
A, the global configuration file of linear frequency-modulated wave mode of operation is loaded first, verifies whether correctly handle linear tune
Frequency signal；
B, the partial profiles of step frequency ripple are loaded on this basis, verify whether correctly handle step frequency
Signal, realize function switch；
C, the global configuration file of on-line loaded step frequency ripple mode of operation, verify whether correctly handle Step Frequency
Rate signal；
D, partial profiles of on-line loaded linear FM signal on this basis, verify whether correctly handle line
Property FM signal.
Step 4：Host computer transmitting portion configuration file carries out the switch test of functional mode.
Function switch test can be carried out by host computer VC interfaces.In the operation at VC interfaces, it is necessary first to initialize
Network interface transport module.Then selected section configuration file is transmitted, when option and installment file can automatic detection part match somebody with somebody
Put the validity of file and judged.If the effective can of partial profiles is transmitted to FPGA, FPGA receives portion
Divide configuration file to be first stored in afterwards in RAM, detect that configuration file carries out FPGA configuration after the completion of receiving.It can observe
FPGA can be handled correctly linear frequency modulation ripple and step frequency ripple.
A kind of implementation method of the FPGA restructurals of the present invention in multi-Mode Radar signal transacting, is existed with VHDL language
FPGA partially dynamical reconfiguration is realized in Xilinx officials development environment ISE 12.4 and Planahead 12.4, and in host computer
It is controlled using VC++ programs, realizes the real-time switching to linear frequency modulation ripple and step frequency ripple processing function.
Claims (9)
1. a kind of implementation method of device of FPGA portion reconstruct in Radar Signal Processing, the implementation of this method is to be based on FPGA
Device of the partial reconfiguration in Radar Signal Processing, the device include FPGA and its peripheral circuit, ADC and its peripheral circuit, net
Mouth chip circuit and power circuit；
The FPGA is acp chip, is responsible for the realization of all logic functions；FPGA controls ADC is sampled, and receives sampling
Data, sampled data is handled inside FPGA；FPGA controls network interface chip realizes the communication between host computer and FPGA：
Radar waveform result after FPGA processing is transferred to host computer by network interface, while FPGA receives the part configuration that host computer is sent
File and order；
The peripheral circuit of the FPGA includes electric source filter circuit, clock circuit, configuration mode control circuit and program storage
FLASH circuits；Electric source filter circuit provides noise small and stable voltage to FPGA；Clock circuit for FPGA provide needed for when
Clock signal；FPGA is selected by configuring the level of three configuration pins；FPGA its internal wiring logic meeting after power is turned off
It is eliminated, upper electricity is required for reconfiguring every time, it is therefore desirable to which the configuration file of FPGA Program Generatings is cured into program storage
In FLASH, upper electric FPGA reads configuration file from the FLASH and configured every time；
ADC is sampling A/D chip, is responsible for sampling external input signal, and analog signal is converted to data signal, ADC samplings
Obtained data signal, which is sent into inside FPGA, carries out digital processing；Two-way radar waveform is acquired using two panels ADC；ADC
Input signal be differential signal, it is therefore desirable to the single-ended signal of input is switched into corresponding differential signal in signal input part；
The signal that ADC is converted is transferred to FPGA in a manner of LVDS DDR；
The ADC peripheral circuits include single-ended transfer difference circuit and signal level shift circuit；Single-ended transfer difference circuit can incite somebody to action
The single-ended radar signal of input is converted to corresponding differential signal；Signal level shift circuit is the control in order to which FPGA is exported
Signal is converted to and ADC matched levels；
The network interface chip circuit is the kernel control chip of network interface communication circuit module, and it is as between FPGA and host computer
Bridge, it is responsible for completing the data transfer between them；Network interface chip circuit upper layer signal is connected with FPGA by GMI interfaces；Bottom
Layer signal is connected with the RJ45 connector of networked physics layer；FPGA control network interface chip circuits are operated in kilomega network pattern；FPGA
Radar waveform result after processing is transferred to host computer by network interface, while FPGA receives the part that host computer is sent by network interface
Configuration file and order；
The power circuit reconstructs the device in Radar Signal Processing for FPGA portion and provides voltage needed for work；
It is characterized in that：Implementation method comprises the following steps：
Step 1：Analyze under multiple-working mode identical handling process and different handling processes in FPGA programs；In reception
The partial profiles that position machine is sent, part is carried out to FPGA and reconfigured, dynamic handles many kinds of radar waveform and by result
Host computer is sent to by network interface；
By analysis, the processing to radar waveform is required for sampling by ADC, convert analog signals into data signal and
Handled inside FPGA；The Processing Algorithm of different radar waveforms is different；Result after processing is uploaded to by network interface
Position machine；The partial profiles that FPGA receives host computer transmission by network interface reconfigure to FPGA；Simulations of the ADC to input
Signal is sampled, and FPGA is by network interface to host computer transmitted waveform result, and host computer is by network interface to FPGA transport parts
Divide configuration file；
Step 2：The FPGA for writing modules realizes algorithm；By analysis, it is divided into following four functional module：ADC is adopted
Collect module, part configuration module, waveform processing module and network interface transport module；
The ADC acquisition modules；It is controls of the FPGA to ADS5562 chips, controls of the FPGA to ADS5562 chips is exactly every
It is secondary convert after read change data；The data that ADS5562 chips return are LVDS DDR formats, and FPGA is by the difference of return
Divided data is converted to single ended data；The input signal of ADS5562 chips is differential signal, it is therefore desirable to will be defeated in signal input part
The single-ended signal entered switchs to corresponding differential signal；The signal that ADC is converted is transferred to FPGA in a manner of LVDS DDR；
The part configuration module；FPGA realizes partial reconfiguration by the way of internal configuration interface ICAP；Dynamic restructuring is matched somebody with somebody
Data are put dynamically to reconfigure FPGA by ICAP interfaces；ICAP interfaces include single data input bus (DIB) and data
Output bus；
When partial reconfiguration is realized, it is necessary first under the control at host computer VC interfaces, partial reconfiguration file is passed through into net
Mouth is sent to FPGA, and FPGA receives partial profiles and stored into internal RAM, and FPGA detects partial profiles
During end mark, stop writing number into RAM, start simultaneously at the data that partial profiles are read from RAM, and be sent to ICAP
Interface；
Controls of the FPGA to ICAP is realized by way of state machine；
The waveform processing module；Designs of the FPGA to waveform processing module is that different wave is handled, including linear tune
The pulse compression of frequency ripple, the pulse compression of step frequency ripple, the demodulation of frequency shift keying ripple, the demodulation of phase-shift keying (PSK) ripple and amplitude key
Control the demodulation of ripple；
The network interface transport module；After the module is responsible for the data transfer between FPGA and host computer, including FPGA will be handled
Data packing upload to host computer, while partial profiles are transferred to FPGA and realize partial reconfiguration by host computer, in addition on
Position machine sends control command also by network interface to FPGA；
Step 3：Region distribution is carried out using palnahead12.4 softwares, generates FPGA programming file
Ngc texts are generated before region distribution is carried out using palnahead12.4, it is necessary in FPGA development environments ISE12.4
Part；Need waveform processing module being arranged to top-level module, and the handle in synthesis options in project file in ISE12.4
" add IO BUF " are not selected, then the ngc files of comprehensive generation waveform processing module, and this document is below
It can be used in planahead12.4；Ngc files except generating waveform processing module also need to generate the ngc texts of top-level module
Part, the generation of top-level module ngc files needs to delete the code file of waveform processing module from engineering, in a prewired program
It is same only to carry out first step synthesis to the calling of waveform processing module, need exist for choosing that " add IO BUF ", generation are corresponding
Ngc files；
Generate these ngc files and region division is carried out to waveform processing module in planahead12.4 afterwards；Need exist for new
A new planahead12.4 engineering is built, need to choose when engineering attribute is selected " set PR project ", only
The option just occurs afterwards in the license for having mounting portion to reconstruct；Just need to add corresponding file according to prompting below, it is first
First need to add is the ngc files of top-level module, and corresponding pin unbound document is added in next prompting；Next just need
This waveform processing module is configured；Reconfigurable module is arranged to firstly the need of by waveform processing module, then in waveform
The ngc files of the waveform processing module above generated are added in processing module, are just needed after addition to the waveform processing module
Region division is carried out, selected FPGA region needs to meet logical resource required in waveform processing module, selected
Need to detect by drc behind region, be just configured after detection is out of question in planahead12.4, by placement-and-routing
The configuration file and global configuration file of waveform processing module can be generated afterwards；
Need to carry out validation checking to these files；Detection method is exactly that on-line loaded is tested, verification portion configuration text
Whether part can be correctly completed recombination function；
Step 4：Host computer transmitting portion configuration file carries out the switch test of functional mode；
Function switch test is carried out by host computer VC interfaces；In the setting at VC interfaces, it is necessary first to initialize network interface communication；
Then selected section configuration file is transmitted, when option and installment file can automatic detection part configuration file validity
And judged；If partial profiles are effectively just transmitted to FPGA, FPGA is first deposited after receiving partial profiles
Storage detects that configuration file proceeds by FPGA configuration after finishing receiving in RAM.
2. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：That fpga chip is selected is the Virtex-6XC6VLX75T of Xilinx companies.
3. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：Carrying out processing inside described FPGA to sampled data includes pulse compression, the step frequency ripple of linear frequency modulation ripple
Pulse compression, the demodulation of frequency shift keying ripple, the demodulation of phase-shift keying (PSK) ripple and the demodulation of amplitude keying ripple.
4. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：Described order is mode handover command, starts work order and system reset command.
5. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：Clock circuit is crystal oscillator, produces the frequency required for FPGA.
6. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：The FPGA program storages FLASH is the XCF128X of Xilinx companies, and the capacity of the chip is 128Mbit, is matched somebody with somebody
800Mb/s can be arrived by putting speed.
7. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：Network interface chip is included in the network interface chip circuit, is 88E1111-BAB1.
8. a kind of implementation method of device of the FPGA portion reconstruct according to claim 1 in Radar Signal Processing, its
It is characterised by：In the power circuit, input voltage+5V, other required voltages are converted to by 5 power conversion chips；Bag
Include three PTH05000WAD and+5V voltages are respectively converted into required D+3.3V, D+1.0V and D+2.5V；A piece of LM1085
D+1.8V is provided；A piece of AMS1117 provides A+3.3V.
9. a kind of implementation method of device of the FPGA portion reconstruct according to claim 8 in Radar Signal Processing, its
It is characterised by：It is D+2.5V and D+1.0V that the voltage, which is respectively supplied to FPGA,；Program storage FLASHD is D+2.5V and D+
1.8V；Clock circuit is D+2.5V；ADC is D+3.3V and A+3.3V；Network interface chip circuit is D+2.5V and D+1.0V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610181834.6A CN105807263B (en) | 2016-03-28 | 2016-03-28 | A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610181834.6A CN105807263B (en) | 2016-03-28 | 2016-03-28 | A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105807263A CN105807263A (en) | 2016-07-27 |
| CN105807263B true CN105807263B (en) | 2018-03-16 |
Family
ID=56454015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610181834.6A Active CN105807263B (en) | 2016-03-28 | 2016-03-28 | A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105807263B (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107784007B (en) * | 2016-08-29 | 2023-04-18 | 普源精电科技股份有限公司 | Waveform editing method and device |
| CN106886505A (en) * | 2017-01-20 | 2017-06-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The local dynamic reconfigurable system of many waveform operations |
| CN108872940A (en) * | 2017-05-12 | 2018-11-23 | 南京理工大学 | The satellite-borne SAR initial data BAQ compression method of dynamically configurable compression ratio |
| CN107450948B (en) * | 2017-07-28 | 2019-10-08 | 西安电子科技大学 | A kind of FPGA adaptive allocation method and system of low-power consumption |
| CN107255814B (en) * | 2017-07-31 | 2020-04-10 | 西安电子科技大学 | LFMSK waveform-based radar target detection method |
| CN107807902B (en) * | 2017-10-25 | 2021-05-14 | 电子科技大学 | FPGA dynamic reconfiguration controller resisting single event effect |
| CN108173555A (en) * | 2017-11-16 | 2018-06-15 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | A kind of waveform controlling method based on multi-parameter state machine |
| CN109729031A (en) * | 2018-11-21 | 2019-05-07 | 山东省科学院海洋仪器仪表研究所 | A kind of XCTD telecommand and data transmission method |
| CN110096007B (en) * | 2019-04-26 | 2020-11-24 | 西安电子科技大学 | Radar echo signal acquisition circuit chip based on SIP technique |
| CN112098959B (en) * | 2019-10-31 | 2023-11-14 | 上海交通大学 | Reconfigurable radar target/interference simulator based on FPGA and implementation method |
| CN111158710B (en) * | 2019-12-30 | 2023-08-25 | 杭州迪普科技股份有限公司 | Program programming method, device and network equipment |
| CN111291523A (en) * | 2020-01-16 | 2020-06-16 | 南京航空航天大学 | System and method for realizing PUF (physical unclonable function) based on dynamic reconfigurable technology |
| CN111427857B (en) * | 2020-04-01 | 2022-10-25 | 西安交通大学 | FPGA configuration file compression and decompression method based on partition reference technology |
| CN111984480B (en) * | 2020-08-07 | 2022-07-22 | 苏州浪潮智能科技有限公司 | Power consumption pressurization test method and device of FPGA accelerator card and storage medium |
| CN112214955B (en) * | 2020-10-13 | 2023-03-24 | 飞腾信息技术有限公司 | Method for extracting power model parameters of very large scale integrated circuit chip |
| CN112198492B (en) * | 2020-10-21 | 2023-09-19 | 武汉滨湖电子有限责任公司 | Method for generating real-time on-line reconstruction waveform by array radar multichannel waveform |
| CN112904285B (en) * | 2021-02-03 | 2023-12-15 | 北京航空航天大学杭州创新研究院 | Signal acquisition method and device based on FPGA chip |
| CN114706811B (en) * | 2022-01-19 | 2023-05-30 | 中国电子科技集团公司第十研究所 | Signal processing platform with dynamically reconfigurable functional waveform |
| CN114911749A (en) * | 2022-07-20 | 2022-08-16 | 中科亿海微电子科技（苏州）有限公司 | Method with programmable logic block partial reconfiguration function and FPGA |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8476926B1 (en) * | 2012-02-08 | 2013-07-02 | Altera Corporation | Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration |
| CN103605309A (en) * | 2013-11-25 | 2014-02-26 | 北京航空航天大学 | Four-channel high-capacity waveform storage system and construction method thereof |
-
2016
- 2016-03-28 CN CN201610181834.6A patent/CN105807263B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8476926B1 (en) * | 2012-02-08 | 2013-07-02 | Altera Corporation | Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration |
| CN103605309A (en) * | 2013-11-25 | 2014-02-26 | 北京航空航天大学 | Four-channel high-capacity waveform storage system and construction method thereof |
Non-Patent Citations (2)
| Title |
|---|
| "可重构雷达信号处理系统的设计与实现";孙大亮;《中国优秀硕士学位论文全文数据库 信息科技辑》;20160315(第3期);第4、39、44、54页 * |
| "基于脉冲压缩技术的船用导航雷达数字信号处理设计";潘伟;《中国优秀硕士学位论文全文数据库 工程科技II辑》;20160315(第3期);第3、55、58-60、75、80页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105807263A (en) | 2016-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105807263B (en) | A kind of FPGA portion reconstructs device and its implementation in Radar Signal Processing | |
| CN102495565B (en) | Phased array radar antenna beam control device | |
| CN101363900B (en) | Method for testing FPGA device | |
| CN103091620B (en) | Optimization method of capturing power consumption in scan test | |
| CN102073032A (en) | Modular generation method for multi-waveform radar signal | |
| CN106886505A (en) | The local dynamic reconfigurable system of many waveform operations | |
| CN1991731B (en) | Chip burn-recording system | |
| CN100458731C (en) | Method for checking IC design with hardware logic | |
| CN103605309B (en) | A kind of construction method of Four-channel high-capacity waveform storage system | |
| CN101140314B (en) | On-site programmable gate array wire laying channel verification method and system thereof | |
| Paulsson et al. | Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. | |
| Paulsson et al. | Implementation of a virtual internal configuration access port (JCAP) for enabling partial self-reconfiguration on Xilinx Spartan III FPGAs | |
| CN104007300B (en) | Digital fluorescence oscilloscope stochastical sampling disturbs circuitry phase method for designing | |
| CN202216989U (en) | Direct current electronic load based on FIFO architecture bus control mode | |
| CN106021025A (en) | Oversampling data clock recovery FPGA realizing system and method | |
| CN106406286B (en) | A kind of verification method of radar signal processor high-speed digital-analog hybrid circuit | |
| CN100588981C (en) | On-site programmable gate array duplex selector verification method | |
| CN101673097B (en) | Comprehensive control device of digitizer | |
| Liang et al. | A hardware in the loop design methodology for FPGA system and its application to complex functions | |
| Gama et al. | FPGA prototyping using the STEMlab board with application on frequency response analysis of electric machinery | |
| CN101521500B (en) | Data-latching circuit adopting phase selector | |
| CN101788645B (en) | Test circuit and method for increasing scanning coverage rate of chip circuit | |
| US9348619B1 (en) | Interactive datasheet system | |
| CN105203946A (en) | Embedded core wrapper device and design method thereof | |
| CN107479411A (en) | Device and method for field programmable control of chip IO |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220926 Address after: Building 1, No. 768, Jianghong Road, Changhe Street, Binjiang District, Hangzhou City, Zhejiang Province, 310051 Patentee after: Hangzhou Leishi Technology Co.,Ltd. Address before: 100191 No. 37, Haidian District, Beijing, Xueyuan Road Patentee before: BEIHANG University |
|
| TR01 | Transfer of patent right |