CN105790776A - Method and device for parallel decoding of turbo code of 3G protocol - Google Patents

Method and device for parallel decoding of turbo code of 3G protocol Download PDF

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Publication number
CN105790776A
CN105790776A CN201410790475.5A CN201410790475A CN105790776A CN 105790776 A CN105790776 A CN 105790776A CN 201410790475 A CN201410790475 A CN 201410790475A CN 105790776 A CN105790776 A CN 105790776A
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parallel
parallelism
degree
interleaver matrix
parallel block
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杜凡平
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Shenzhen ZTE Microelectronics Technology Co Ltd
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Shenzhen ZTE Microelectronics Technology Co Ltd
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Priority to PCT/CN2015/079466 priority patent/WO2016095426A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

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Abstract

The invention provides a method for parallel decoding of a turbo code of a 3G (3rd Generation) protocol. The method is characterized in that parallel decoding is realized by adopting a parallel interleaving technology. The specific realization method of the parallel interleaving technology comprises the following steps of firstly, dividing a data storage space in a way of an interleaving matrix and requiring that each row of the interleaving matrix is provided with an independent storage space; secondly, setting degree of parallelism and requiring that the degree of parallelism is not greater than the number of the rows of the interleaving matrix; thirdly, determining the length of a parallel block and requiring that the length of the parallel block and the number of the rows of the interleaving matrix are relatively prime; fourthly, parallelly computing parallel interleaving addresses according to the degree of parallelism and the length of the parallel block; and lastly, carrying out parallel read-write on the data storage space according to the parallel interleaving addresses. The invention also discloses a device for parallel decoding of the turbo code of the 3G protocol.

Description

The turbo code parallel decoding method of 3G agreement and device
Technical field
The present invention relates to the decoding technique in mobile communication, particularly relate to turbo code parallel decoding method and device in a kind of 3G (Third Generation) Moblie (3G, 3rdGeneration) agreement.
Background technology
3G all ratio Generation Mobile Telecommunication System (2G in multiple access technology, modulation technique, chnnel coding and intertexture, multi-channel Technology etc., 2ndGeneration) make moderate progress, particularly chnnel coding aspect, have employed coding gain and exceeds the turbo code of 1-2db than convolutional code in 3G.Turbo code is excellent performance when weaving length is bigger, but the complexity of Turbo code decoding is higher, time delay is longer, therefore, how to improve Turbo code decoding speed and is always up the bottleneck problem of turbo code.
Forth generation mobile communication (4G, Long Term Evolution (LTE 4thGeneration), LongTermEvolution) system have employed twice replaced polynomial (QPP, QuadraticPermutationPolynomials) interleaver, parallel intertexture is made to be possibly realized, but, the turbo interleaver of 3G is not supported parallel in theory, along with high-speed packet accesses (HSPA, High-SpeedPacketAccess) speed is more and more higher, the turbo how improving 3G is decoded into for a key issue, therefore the significant parallel of decoding is realized, for terminal, resource can be reduced, reduce time delay and power consumption；For base station, it is possible to multiple users are simultaneously connected with to make base station support, improve the handling capacity of base station, reduce the process time delay of single user.
4G why can parallel decoding, be because employing parallel interleaver, therefore, it is achieved parallel decoding it is crucial that realize parallel intertexture.
The interleaver principle of the turbo code in 3G is as follows:
Turbo code interleaving process includes inputting and increase filling bit by row and constitutes interleaver matrix, and row matrix is interior and in the ranks replaces, and exports by row and delete filling bit.The input bit of Turbo code interleaver is designated as x1,x2,x3,…,xK, wherein, K is bit number, and value is 40≤K≤5114.
Here, following parameter is first defined:
KTurbo code interleaver input bit number；
R interleaver matrix line number；
C interleaver matrix columns；
P prime number；
V primitive root；
〈s(j)〉j∈{0,1,…,p-2}Displacement basic sequence in row；
qiMinimum matter integer sequence；
riMatter integer sequence after displacement；
〈T(i)〉i∈{0,1,…,R-1}Displacement patterns in the ranks；
〈Ui(j)〉j∈{0,1,…,C-1}Displacement patterns in the row of the i-th row；
I interleaver matrix line number pointer；
J interleaver matrix column number pointer；
K bit sequence pointer；
The first step, constitutes interleaver matrix by row input:
Input to the bit sequence x of Turbo code interleaver1,x2,x3,…,xKWrite in interleaver matrix with the following step:
(1) the line number R of interleaver matrix is determined so that:
R = 5 , if ( 40 ≤ K ≤ 159 ) 10 , if ( ( 160 ≤ K ≤ 200 ) or ( 481 ≤ K ≤ 530 ) ) 20 , if ( K = any other value )
The each row of interleaver matrix is 0,1 according to order number consecutively from top to bottom ..., R-1.
(2) prime number that in row, displacement is required, p, and the columns of interleaver matrix, C are determined so that:
if(481≤K≤530)then
P=53andC=p
else
Minimum prime number p is found from table 1 so that:
K≤R×(p+1)；
And determine C so that:
C = p - 1 if K &le; R &times; ( p - 1 ) p if R &times; ( p - 1 ) < K &le; R &times; p p + 1 if R &times; pK <
endif
It is 0,1 that intertexture battle array respectively arranges according to order number consecutively from left to right ..., C-1.
Wherein, table 1 is prime number p and corresponding primitive root v list；
P v p v p v p v p v
7 3 47 5 101 2 157 5 223 3
11 2 53 2 103 5 163 2 227 2
13 2 59 2 107 2 167 5 229 6
17 3 61 2 109 6 173 2 233 3
19 2 67 2 113 3 179 2 239 7
23 5 71 7 127 3 181 2 241 7
29 2 73 5 131 2 191 19 251 6
31 3 79 3 137 3 193 5 257 3
37 2 83 2 139 2 197 2
41 6 89 3 149 2 199 3
43 3 97 5 151 6 211 2
Table 1
(3) line by line by bit sequence x1,x2,x3,…,xKIn the interleaver matrix of write R × C, first bit y1Insert 0 row 0 to arrange:
y 1 y 2 y 3 . . . y C y ( C + 1 ) y ( C + 2 ) y ( C + 3 ) . . . y 2 C . . . . . . . . . . . . . . . y ( ( R - 1 ) C + 1 ) y ( ( R - 1 ) C + 2 ) y ( ( R - 1 ) C + 3 ) . . . y R &times; C
Wherein, yk=xk；Fork=1,2 ..., K, and if R × C > K, then uses dummy bits yk=0or1, k=K+1, K+2 ..., R × C fills.These dummy bits, having performed in row and after displacement in the ranks, need during output to delete from interleaver matrix.
Second step: go interior and in the ranks replace:
After in the interleaver matrix of input bit write R × C, perform in row according to the steps (A1) (A6) and displacement in the ranks:
(A1) selecting a primitive root from table 1, in table, all primitive roots are all listed in the right side of prime number p；
(A2) basic sequence < s (j) > replaced it is configured in row as followsj∈{0,1,…,p-2}:
S (j)=(ν × s (j-1)) modp, j=1,2 ... (p-2), and s (0)=1；
(A3) q is specified0=1 is sequence < qi〉i∈{0,1,…,R-1}In first prime number, sequence < qi〉i∈{0,1,…,R-1}Other prime number defining method are: for each i=1,2 ..., R 1, qiIt is meet g.c.d (qi, p-1)=1, qi> 6, and qi>q(i-1)Minimum matter integer.Here g.c.d. represents greatest common divisor；
(A4) constant series < qi〉i∈{0,1,…,R-1}, obtain sequence < ri〉i∈{0,1,…,R-1}So that:
rT(i)=qi, i=0,1 ...., R 1；
Wherein < T (i) >i∈{0,1,…,R-1}Being in the ranks displacement patterns, be defined as the one in four shown in table 2 kind pattern, concrete model selection depends on input bit number K；
In the ranks displacement patterns is as shown in table 2:
Table 2
(A5) displacement in the row of the i-th row is performed:
If (C=p) then
Ui(j)=s ((j × ri) mod (p-1)), j=0,1 ..., (p-2), andUi(p-1)=0,
Wherein, UiJ () is the home position of the bit of the jth needs displacement of the i-th row.
Endif
If (C=p+1) then
Ui(j)=s ((j × ri) mod (p-1)), j=0,1 ..., (p-2)；Ui(p-1)=0, andUi(p)=p,
Wherein UiJ () is the home position of the bit of the jth needs displacement of the i-th row, and
If (K=R × C) then
Exchange UR-1(p) and UR-1(0).
endif
endif
If (C=p-1) then
Ui(j)=s ((j × ri) mod (p-1))-1, j=0,1 ..., (p-2)；
Wherein, UiJ () is the home position of the bit of the jth needs displacement of the i-th row.
endif
(A6) according to pattern < T (i) >i∈{0,1,…,R-1}Performing the displacement in the ranks of interleaver matrix, wherein T (i) is the raw line position of i-th displacement row.
3rd step, by row output:
In row and after displacement execution in the ranks, the interleaver matrix bit after displacement is with y'kRepresent:
y &prime; 1 y &prime; ( R + 1 ) y &prime; ( 2 R + 1 ) . . . y &prime; ( ( C - 1 ) R + 1 ) y &prime; 2 y &prime; ( R + 2 ) y &prime; ( 2 R + 2 ) . . . y &prime; ( ( C - 1 ) R + 2 ) . . . . . . . . . . . . . . . y &prime; R y &prime; 2 R y &prime; 3 R . . . y &prime; C &times; R
The output of Turbo code interleaver is the bit sequence sequential read out according to the order of string string from R × C interleaver matrix, and this matrix space is interior and in the ranks replaces, and bit sequence starts from the y' of 0 row 0 row1, terminate at the y' of R-1 row C-1 rowCR.Delete that operation is all dummy bits filling up in Input matrix before deleting be expert at interior and displacement in the ranks, namely corresponding to yk, the bit y' of k > KkNeed to delete from output.
Owing to the deinterleaving method in above-mentioned 3G is complex, therefore, prior art generally all thinks that the interleaver that 3G agreement specifies can not realize parallel intertexture, therefore realize parallel decoding all to be realized by some other skill, such as, realized by pre-reads data to buffer area, or use the methods such as base 4,8,16 to process 2,3,4 bits raising efficiency simultaneously.But prior art does not fundamentally use parallel interleaving technology, but is improve efficiency by some other skills so that it is reach a degree of parallel effect.
Summary of the invention
In view of this, present invention contemplates that the turbo code parallel decoding method that a kind of 3G agreement is provided and device, it is possible to by adopting parallel interleaving technology to realize the turbo code parallel decoding of 3G agreement.
For reaching above-mentioned purpose, the technical scheme is that and be achieved in that:
Embodiments providing the turbo code parallel decoding method of a kind of 3G agreement, described method includes:
Adopt parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；
The turbo code of 3G agreement is carried out parallel decoding by the result according to concurrent reading and concurrent writing.
In such scheme, data space is carried out concurrent reading and concurrent writing and includes by the parallel interleaving technology of described employing:
Divide data space；
Degree of parallelism is set；
Determine parallel block length；
According to described degree of parallelism and parallel block length, the parallel interleaving address of parallel computation；
According to described parallel interleaving address, data space is carried out concurrent reading and concurrent writing.
In such scheme, described division memory space includes:
By the data space model split according to interleaver matrix, every a line of interleaver matrix is divided into independent memory space.
In such scheme, the described degree of parallelism that arranges includes:
Line number according to interleaver matrix determines degree of parallelism, and described degree of parallelism is not more than the line number of described interleaver matrix.
In such scheme, described determine that parallel block length includes:
According to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；
Parallel block initial length is modified, obtains parallel block length.
In such scheme, described it is modified including to parallel block initial length:
Choose and be not less than parallel block initial length, and relatively prime with interleaver matrix line number worthwhile make revised parallel block length；
Especially, parallel block length includes but not limited to the minima that is not less than in parallel block initial length and all values relatively prime with interleaver matrix line number.
In such scheme, described according to degree of parallelism with parallel block length, the parallel interleaving address of parallel computation includes:
Determine every time the parallel independent parallel interleaving address number produced according to degree of parallelism, determine the number of times producing parallel interleaving address according to parallel block length, calculate parallel interleaving address by parallel protocols.
The embodiment of the present invention additionally provides the turbo code parallel decoding device of a kind of 3G agreement, and described device includes: concurrent reading and concurrent writing module, parallel decoding module, wherein,
Described concurrent reading and concurrent writing module, is used for adopting parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；
Described parallel decoding module, carries out parallel decoding for the result according to concurrent reading and concurrent writing to the turbo code of 3G agreement.
In such scheme, described concurrent reading and concurrent writing module includes data space division submodule, degree of parallelism arranges submodule, parallel block length determines submodule, parallel interleaving address calculating sub module, read-write submodule, wherein,
Described data space divides submodule, is used for dividing data space；
Described degree of parallelism arranges submodule, is used for arranging degree of parallelism；
Described parallel block length determines submodule, is used for determining parallel block length；
Described parallel interleaving address calculating sub module, for according to described degree of parallelism and parallel block length, the parallel interleaving address of parallel computation；
Described read-write submodule, for according to described parallel interleaving address, carrying out concurrent reading and concurrent writing to data space.
In such scheme, described data space divide submodule specifically for: by the data space model split according to interleaver matrix, every a line of interleaver matrix is divided into independent memory space.
In such scheme, described degree of parallelism arrange submodule specifically for: determining degree of parallelism according to the line number of interleaver matrix, described degree of parallelism is not more than the line number of described interleaver matrix.
In such scheme, described parallel block length determine submodule specifically for: according to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；Parallel block initial length is modified, obtains parallel block length.
In such scheme, described parallel block length determine submodule specifically for: choose and be not less than parallel block initial length, and relatively prime with interleaver matrix line number worthwhile make revised parallel block length；Especially, parallel block length includes but not limited to the minima that is not less than in parallel block initial length and all values relatively prime with interleaver matrix line number.
In such scheme, parallel interleaving address calculating sub module specifically for: determine every time the parallel independent parallel interleaving address number produced according to degree of parallelism, determine the number of times producing parallel interleaving address according to parallel block length, calculate parallel interleaving address by parallel protocols.
The turbo code parallel decoding method of 3G agreement provided by the present invention and device, by adopting parallel interleaving technology to realize parallel decoding, realize parallel intertexture, just require that data space can read or write parallel, therefore first by the data space model split according to interleaver matrix, each provisional capital of interleaver matrix is made to have independent memory space；Then degree of parallelism is set；Parallel block length is calculated further according to degree of parallelism；Then according to described degree of parallelism and the parallel interleaving address of parallel block length parallel computation, finally, according to described parallel interleaving address, data space is carried out concurrent reading and concurrent writing.The present invention overthrown before about 3G agreement turbo interleaver can not this disconnected opinion of Parallel Implementation, by realizing the parallel intertexture of the turbo code of 3G agreement, and then realize the parallel decoding of the turbo code of 3G agreement.
Accompanying drawing explanation
Fig. 1 is the parallel interweaving realization method schematic flow sheet in parallel decoding method of the present invention；
Fig. 2 of the present invention determines parallel block length method schematic flow sheet；
Fig. 3 is the General Principle schematic diagram of turbo decoder；
Fig. 4 is that turbo parallel decoding of the present invention realizes schematic diagram；
Fig. 5 is division and the service condition schematic diagram of memory space of the present invention；
Fig. 6 is the turbo code parallel decoding apparatus structure schematic diagram of 3G agreement of the present invention.
Detailed description of the invention
Realize parallel decoding, it is crucial that realize parallel intertexture, will realize parallel intertexture, as long as can according to the conflict free parallel interleaving address of the generation of parallel protocols, therefore, the core of the present invention be how the conflict free parallel interleaving address that generation is parallel.
As described in agreement, 3G is intertwined with following features:
First, as described in agreement second step, interweave and be divided in row replace and in the ranks replace two steps, in row, displacement does not change the position of the row residing for bit, although having carried out again in the ranks replacing, but in the ranks displacement is that full line data are replaced together, the relative position of change row residing for bit, namely the bit of same a line it is in after displacement in the ranks still in same a line, the bit of different rows or different rows, to sum up, it is in before intertexture after the Bit Interleave of same a line still in same a line, after being not at the Bit Interleave of same a line before intertexture, is still not at same a line.Known based on being still not at same a line this point after being not at the Bit Interleave of same a line before interweaving, as long as the bit of each parallel block of concurrent reading and concurrent writing is not at same a line before intertexture, so, also not in same a line during parallel intertexture read-write, it is possible to controlled the original position of each parallel block of concurrent reading and concurrent writing simply by this feature not in same a line of interleaver matrix.
Secondly, as described in agreement the 3rd step, the output that interweaves is to be sequentially output according to the direction of row, namely interweaves and always accesses every a line of interleaver matrix in particular order, and next provisional capital of every a line determines that, different.Therefore, as long as the original position of each parallel block of concurrent reading and concurrent writing is not at same a line of interleaver matrix, so, the position of the read-write of each parallel block of subsequent time is certainly not also in same a line of interleaver matrix, and namely concurrent reading and concurrent writing always reads and writes the different row of interleaver matrix.To sum up, as long as data are stored according to the mode of interleaver matrix, each row is stored in independent memorizer, it is possible to avoid concurrent reading and concurrent writing conflict.
Therefore, how to divide the size of parallel block, make parallel interweave read-write interleaver matrix time initial row do not realize exactly interweaving parallel conflict free key in same a line, be also the key of the present invention.To sum up, this invention address that when the method that concurrent reading and concurrent writing conflict adopts is parallel intertexture read-write interleaver matrix, initial row staggers, therefore the method for the present invention is properly termed as wrong row method.
The turbo code parallel decoding method of 3G agreement of the present invention comprises the following steps: first, adopts parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；Then, the turbo code parallel decoding of 3G agreement is realized by parallel interleaving technology.
Below in conjunction with drawings and the specific embodiments, the enforcement of technical solution of the present invention is described in further detail.Fig. 1 is the parallel interweaving realization method schematic flow sheet in parallel decoding method of the present invention, comprises the following steps:
Step 100: divide data space；By the data space model split according to interleaver matrix, every a line of interleaver matrix is divided into independent memory space；
In this step, owing to requiring that memory space is according to the model split of interleaver matrix, and each row can individually access, it is therefore desirable to interleaver matrix line number r independent memorizer, each memory size is interleaver matrix columns c；In practical application, in order to Encoding Block Length maximum in compatible protocol, the size of memorizer and quantity to take maximum, namely various data are required for the SAM Stand Alone Memory of 20 256 degree of depth.
Step 101: degree of parallelism para is set；Described degree of parallelism is not more than interleaver matrix line number；
Concrete, determine degree of parallelism according to the line number of interleaver matrix, because the line number r of interleaver matrix is fixing, and the number of independent memorizer is equal to the line number of interleaver matrix, and therefore, set degree of parallelism para can not more than the line number r of interleaver matrix；If described degree of parallelism para is more than the line number r of interleaver matrix, then concurrent reading and concurrent writing is certain to access same a line of interleaver matrix, and address conflict occurs.
The false code arranging degree of parallelism is expressed as:
Para≤r；
Step 102: determine parallel block length pk；The length pk of described parallel block and interleaver matrix line number r is relatively prime；
Concrete, according to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；Parallel block initial length is modified, obtains parallel block length.In the present invention, the parallel block length pk finally determined to make the original position of each parallel block not in same a line of interleaver matrix, and this just requires that the length pk and interleaver matrix line number r of parallel block are relatively prime, i.e. gcd (pk, r)=1, gcd for taking greatest common divisor function.
Fig. 2 of the present invention determines parallel block length method schematic flow sheet, comprises the following steps:
Step 102A: according to the line number r of interleaver matrix, columns c and degree of parallelism para, it is determined that parallel block initial length pk0；
In this step, described determine parallel block initial length pk0False code be expressed as:
pk0=ceil (c*r/para)；
Wherein, ceil is flow in upper plenum, and its function is to return the smallest positive integral more than or equal to specifying expression formula.
Step 102B: to parallel block initial length pk0It is modified, obtains parallel block length, and make parallel block length pk and interleaver matrix line number r relatively prime.
Due to parallel block initial length pk0Not necessarily meet relatively prime with interleaver matrix line number r, it is therefore desirable to look for and be not less than parallel block initial length pk0And the value relatively prime with interleaver matrix line number is as the parallel block length after revising.
Further, in order to make parallel block length little as far as possible, the embodiment of the present invention adopts closest to parallel block initial length pk0Value as revise parallel block length.
Utilize written in pseudocode as follows:
Wherein gcd seeks greatest common divisor function.
Step 103: according to described degree of parallelism para and parallel block length pk, the parallel interleaving address of parallel computation；
In this step, determine the quantity of the parallel interleaving address of generation every time according to degree of parallelism, determine the number of times producing parallel interleaving address according to parallel block length, calculate parallel interleaving address by parallel protocols.
Concrete, according to the method producing parallel interleaving address that the degree of parallelism para of described setting and parallel block length pk and agreement specify, produce para address of degree of parallelism, to produce parallel block length pk time every time.Implement in process, it is necessary to degree of parallelism para independent address calculation, calculate degree of parallelism para parallel interleaving address simultaneously.
The false code that the present invention produces parallel interleaving address is as follows:
Wherein row be interweave before this bit line number in interleaver matrix, col be interweave before this bit columns in interleaver matrix, xrow be interweave after this bit line number in interleaver matrix, xcol for interweave after this bit in interleaver matrix midrange.R, c are line number and the columns of interleaver matrix, and p is the determined prime number of table 1, q is the prime number sequence that agreement specifies, T_row is displacement patterns in the ranks as shown in table 2, and s (mod (col*q (row), p-1)) is Transformation formula in row.
Can be seen that according to above false code, row address displacement relation before and after interweaving is: xrow=T_row (row), namely not interleaver matrix with a line data through intertexture after still not in same a line of interleaver matrix, as long as therefore ensure that the read and write position of each parallel block before intertexture is not in same a line of interleaver matrix, then during intertexture read-write, the read and write position of each parallel block is not certainly also in same a line of interleaver matrix.
Step 104: according to described parallel interleaving address, data space is carried out concurrent reading and concurrent writing.
In sum, parallel decoding method of the present invention is from interleaver, by realizing interweaving parallel and then achieving the parallel decoding of the turbo code of 3G agreement.And by the concrete grammar that the present invention provides, can not this disconnected opinion of Parallel Implementation about the turbo interleaver in 3G before having overthrown.Using the method for the invention, the Parallel Implementation method of the turbo interleaver of the 3G QPP interleaver unlike the 4G designed exclusively for Parallel Implementation is complicated.It is also possible that assume, if before the QPP interleaver invention of 4G, find that the turbo interleaver of 3G can pass through parallel decoding method Parallel Implementation easily described in the embodiment of the present invention, so even for 4G, the QPP interleaver incompatible with 3G need not individually be proposed, cause 3G, 4G needs two kinds of different interleaving devices, not only increases the complexity of design, also brings incompatible problem.
Fig. 3 is the General Principle schematic diagram of turbo decoder, and the concrete principle present invention just repeats no more here.In whole realization, in order to reduce resource, only use a set of decoding module, interweaved by sequential write and read to realize the intertexture of data, write order by interweaving and read to realize the deinterleaving of data.Specifically, be interweave or deinterleave to be determined by the parity of iterations, i.e. odd-times iteration, systematic bits order is read, and prior information order is read, external information sequential write；Even-times iteration, systematic bits interweaves and reads, and prior information interweaves and reads, and external information interweaves and writes, and once strange iteration constitutes once complete decoding iteration with once even iteration.
Fig. 4 is that turbo parallel decoding of the present invention realizes schematic diagram, including systematic bits memory module, the first check bit memory module, the second check bit memory module, external information memory module, decoding module, and parallel interleaving address generation module.Wherein, external information memory module is a both-end ram, and read-write can independently carry out, and reads end and reads prior information, write end write external information, furthermore it is possible to this for hard-decision bits single-bit memory space and the splicing of extrinsic information data memory space, reduce amount of storage space, and use both-end ram to store the added advantage brought of hard-decision bits to be, write can be compared with the hard-decision bits read, control the iterations of turbo decoder according to comparative result, it is achieved early stop.Be it can also be seen that by Fig. 4, the quantity that decoding module produces module with parallel interleaving address is determined by maximum parallelism degree, can have up to 20 sets, the degree of parallelism proposed owing to meet the present invention in real work is not more than the condition of interleaver matrix line number, and para can only be had to be enclosed within work；Every kind of data memory module has 20 sets, in real work, only uses interleaver matrix line number r set.Division and the service condition of concrete memory space are as it is shown in figure 5, division that Fig. 5 is memory space of the present invention and service condition schematic diagram, and the 20 set degree of depth are in the memory space of 256, only employ the space of interleaver matrix size therein.
The present invention is only for said process, does not limit protection scope of the present invention, for instance, parallel decoding method of the present invention can further be used for the turbo parallel decoding of 3G and 4G bimodulus.
The embodiment of the present invention additionally provides the turbo code parallel decoding device of a kind of 3G agreement.Fig. 6 is the turbo code parallel decoding apparatus structure schematic diagram of 3G agreement of the present invention, and as shown in Figure 6, described device includes: concurrent reading and concurrent writing module 61, parallel decoding module 62, wherein,
Described concurrent reading and concurrent writing module 61, is used for adopting parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；
In the present invention, described concurrent reading and concurrent writing module 61 includes data space division submodule 611, degree of parallelism arranges submodule 612, parallel block length determines submodule 613, parallel interleaving address calculating sub module 614, read-write submodule 615, wherein,
Described data space divides submodule 611, is used for dividing data space；
Concrete, described data space divides submodule 611 by the data space model split according to interleaver matrix, and every a line of interleaver matrix is divided into independent memory space；
Owing to requiring that memory space is according to the model split of interleaver matrix, and each row can individually access, it is therefore desirable to interleaver matrix line number r independent memorizer, each memory size is interleaver matrix columns c；In practical application, in order to Encoding Block Length maximum in compatible protocol, the size of memorizer and quantity to take maximum, namely various data are required for the SAM Stand Alone Memory of 20 256 degree of depth.
Described degree of parallelism arranges submodule 612, is used for arranging degree of parallelism；Described degree of parallelism is not more than interleaver matrix line number；
Concrete, described degree of parallelism arranges submodule 612 and determines degree of parallelism according to the line number of interleaver matrix, and described degree of parallelism is not more than the line number of described interleaver matrix.Because the line number r of interleaver matrix is fixing, and the number of independent memorizer is equal to the line number of interleaver matrix, and therefore, set degree of parallelism para can not more than the line number r of interleaver matrix；If described degree of parallelism para is more than the line number r of interleaver matrix, then concurrent reading and concurrent writing is certain to access same a line of interleaver matrix, and address conflict occurs.
Described parallel block length determines submodule 613, is used for determining parallel block length；Wherein, the length pk of described parallel block and interleaver matrix line number r is relatively prime；
Concrete, described parallel block length determines that submodule 613 is first according to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；Then parallel block initial length is modified, obtains parallel block length.Described parallel block length determine in the process that parallel block initial length is modified by submodule 613 specifically for: choose and be not less than parallel block initial length, and relatively prime with interleaver matrix line number worthwhile make revised parallel block length；Especially, parallel block length includes but not limited to the minima that is not less than in parallel block initial length and all values relatively prime with interleaver matrix line number.
Parallel block length pk owing to finally determining to make the original position of each parallel block not in same a line of interleaver matrix, this just requires that the length pk and interleaver matrix line number r of parallel block are relatively prime, namely (pk, r)=1, gcd for taking greatest common divisor function for gcd.
Described parallel block length determines that submodule 613 is first according to the line number r of interleaver matrix, columns c and degree of parallelism para, it is determined that parallel block initial length pk0；Then to parallel block initial length pk0It is modified, obtains parallel block length pk and make parallel block length pk and interleaver matrix line number r relatively prime.
Due to parallel block initial length pk0Not necessarily meet relatively prime with interleaver matrix line number r, it is therefore desirable to look for and be not less than parallel block initial length pk0And the value relatively prime with interleaver matrix line number is as the parallel block length after revising.Further, in order to make parallel block length little as far as possible, the embodiment of the present invention adopts closest to parallel block initial length pk0Value as revise parallel block length.
Described parallel interleaving address calculating sub module 614, for according to described degree of parallelism and parallel block length, the parallel interleaving address of parallel computation；
Concrete, described parallel interleaving address calculating sub module 614 determines every time the parallel independent parallel interleaving address number produced according to degree of parallelism, determines the number of times producing parallel interleaving address according to parallel block length, calculates parallel interleaving address by parallel protocols.
Concrete, the method for the parallel interleaving address of generation that described parallel interleaving address calculating sub module 614 specifies according to degree of parallelism para and parallel block length pk and the agreement of described setting, produce para address of degree of parallelism every time, produce parallel block length pk time.Implement in process, it is necessary to degree of parallelism para independent address calculation, calculate degree of parallelism para parallel interleaving address simultaneously.
Described read-write submodule 615, for according to described parallel interleaving address, carrying out concurrent reading and concurrent writing to data space.
Described parallel decoding module 62, carries out parallel decoding for the result according to concurrent reading and concurrent writing to the turbo code of 3G agreement.
The embodiment of the present invention is only for said process, implements in process, according to practical application scene, concrete steps can be adjusted, replaces, deletion etc..Those skilled in the art the present invention is carried out simply variation and modification still without departing from the spirit and scope of the present invention.Such as, under being capable of goal of the invention situation of the present invention, above-mentioned steps can suitably adjust, and omits or increases partial routine, and to form new method, these adjustment belong to scope of the present invention.
Each processing module in the turbo code parallel decoding device of the 3G agreement shown in Fig. 6 realize function, can refer to the associated description of the turbo code parallel decoding method of aforementioned 3G agreement and understand.Skilled artisan would appreciate that, in the turbo code parallel decoding device of the 3G agreement shown in Fig. 6, the function of each processing unit can be realized by the program that runs on processor, realize also by concrete logic circuit, such as: can be realized by central processing unit (CPU), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA)；Described memory element can also be realized by various memorizeies or storage medium.
In several embodiments provided by the present invention, it should be understood that disclosed method, device, it is possible to realize in other way.Device embodiment described above is merely schematic, such as, the division of described module, it is only a kind of logic function to divide, actual can have other dividing mode when realizing, and as: multiple modules or assembly can be in conjunction with, or is desirably integrated into another system, or some features can ignore, or do not perform.It addition, the communication connection that shown or discussed each ingredient is each other can be through INDIRECT COUPLING or the communication connection of some interfaces, equipment or module, it is possible to be electrical, machinery or other forms.
The above-mentioned module illustrated as separating component can be or may not be physically separate, and the parts shown as module can be or may not be physical location, namely may be located at a place, it is also possible to be distributed on multiple NE；Part or all of module therein can be selected according to the actual needs to realize the purpose of the present embodiment scheme.
It addition, each functional module in various embodiments of the present invention can be fully integrated in a processing module, it is also possible to be that each module is individually as a module, it is also possible to two or more modules are integrated in a module；Above-mentioned integrated module both can adopt the form of hardware to realize, it would however also be possible to employ hardware adds the form of SFU software functional unit and realizes.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can be completed by the hardware that programmed instruction is relevant, aforesaid program can be stored in computer read/write memory medium, this program upon execution, performs to include the step of said method embodiment；And aforesaid storage medium includes: the various media that can store program code such as movable storage device, read only memory (ROM, Read-OnlyMemory), magnetic disc or CDs.
Or, if the above-mentioned integrated module of the embodiment of the present invention realizes using the form of software function module and as independent production marketing or when using, it is also possible to be stored in a computer read/write memory medium.Based on such understanding, the part that prior art is contributed by the technical scheme of the embodiment of the present invention substantially in other words can embody with the form of software product, this computer software product is stored in a storage medium, including some instructions with so that a computer equipment (can be personal computer, server or the network equipment etc.) performs all or part of of method described in each embodiment of the present invention.And aforesaid storage medium includes: the various media that can store program code such as movable storage device, ROM, magnetic disc or CDs.
The present invention is that turbo code parallel decoding method in the 3G agreement recorded in example, device are only for above-described embodiment, but it is not limited only to this, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein some or all of technical characteristic is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit protection scope of the present invention.

Claims (14)

1. the turbo code parallel decoding method of a 3G agreement, it is characterised in that described method includes:
Adopt parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；
The turbo code of 3G agreement is carried out parallel decoding by the result according to concurrent reading and concurrent writing.
2. method according to claim 1, it is characterised in that data space is carried out concurrent reading and concurrent writing and includes by the parallel interleaving technology of described employing:
Divide data space；
Degree of parallelism is set；
Determine parallel block length；
According to described degree of parallelism and parallel block length, the parallel interleaving address of parallel computation；
According to described parallel interleaving address, data space is carried out concurrent reading and concurrent writing.
3. method according to claim 2, it is characterised in that described division memory space includes:
By the data space model split according to interleaver matrix, every a line of interleaver matrix is divided into independent memory space.
4. method according to claim 2, it is characterised in that the described degree of parallelism that arranges includes:
Line number according to interleaver matrix determines degree of parallelism, and described degree of parallelism is not more than the line number of described interleaver matrix.
5. method according to claim 2, it is characterised in that described determine that parallel block length includes:
According to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；
Parallel block initial length is modified, obtains parallel block length.
6. method according to claim 5, it is characterised in that described be modified including to parallel block initial length:
Choose and be not less than parallel block initial length, and relatively prime with interleaver matrix line number worthwhile make revised parallel block length；
Especially, parallel block length includes but not limited to the minima that is not less than in parallel block initial length and all values relatively prime with interleaver matrix line number.
7. method according to claim 2, it is characterised in that described according to degree of parallelism with parallel block length, the parallel interleaving address of parallel computation includes:
Determine every time the parallel independent parallel interleaving address number produced according to degree of parallelism, determine the number of times producing parallel interleaving address according to parallel block length, calculate parallel interleaving address by parallel protocols.
8. the turbo code parallel decoding device of a 3G agreement, it is characterised in that described device includes: concurrent reading and concurrent writing module, parallel decoding module, wherein,
Described concurrent reading and concurrent writing module, is used for adopting parallel interleaving technology that data space is carried out concurrent reading and concurrent writing；
Described parallel decoding module, carries out parallel decoding for the result according to concurrent reading and concurrent writing to the turbo code of 3G agreement.
9. device according to claim 8, it is characterised in that described concurrent reading and concurrent writing module includes that data space divides submodule, degree of parallelism arranges submodule, parallel block length determines submodule, parallel interleaving address calculating sub module, read-write submodule, wherein,
Described data space divides submodule, is used for dividing data space；
Described degree of parallelism arranges submodule, is used for arranging degree of parallelism；
Described parallel block length determines submodule, is used for determining parallel block length；
Described parallel interleaving address calculating sub module, for according to described degree of parallelism and parallel block length, the parallel interleaving address of parallel computation；
Described read-write submodule, for according to described parallel interleaving address, carrying out concurrent reading and concurrent writing to data space.
10. device according to claim 8, it is characterised in that described data space divide submodule specifically for: by the data space model split according to interleaver matrix, every a line of interleaver matrix is divided into independent memory space.
11. device according to claim 8, it is characterised in that described degree of parallelism arrange submodule specifically for: determining degree of parallelism according to the line number of interleaver matrix, described degree of parallelism is not more than the line number of described interleaver matrix.
12. device according to claim 8, it is characterised in that described parallel block length determine submodule specifically for: according to the line number of interleaver matrix, columns and degree of parallelism, it is determined that parallel block initial length；Parallel block initial length is modified, obtains parallel block length.
13. device according to claim 12, it is characterised in that described parallel block length determine submodule specifically for: choose and be not less than parallel block initial length, and relatively prime with interleaver matrix line number worthwhile make revised parallel block length；Especially, parallel block length includes but not limited to the minima that is not less than in parallel block initial length and all values relatively prime with interleaver matrix line number.
14. device according to claim 8, it is characterized in that, parallel interleaving address calculating sub module specifically for: determine every time the parallel independent parallel interleaving address number produced according to degree of parallelism, determine the number of times producing parallel interleaving address according to parallel block length, calculate parallel interleaving address by parallel protocols.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101116249A (en) * 2005-02-03 2008-01-30 松下电器产业株式会社 Parallel interleaver, parallel deinterleaver, and interleave method
CN101707490A (en) * 2009-09-22 2010-05-12 重庆重邮信科通信技术有限公司 Parallel Turbo code interleaving method
CN102035557A (en) * 2009-09-27 2011-04-27 中兴通讯股份有限公司 Method and device for interweaving turbo codes in parallel
US20130198529A1 (en) * 2010-10-18 2013-08-01 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Sample carrier unit having sample data encryption and method for use thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959403B2 (en) * 2006-11-10 2015-02-17 Optis Wireless Technology, Llc QPP interleaver/de-interleaver for turbo codes
CN101719810A (en) * 2009-11-13 2010-06-02 清华大学 Simulation generation method for parallel interleaver
CN101986584A (en) * 2010-10-22 2011-03-16 中国科学院计算技术研究所 Rate de-matching device and method in 3GPP LTE
CN102739358A (en) * 2012-06-01 2012-10-17 武汉邮电科学研究院 Method for realizing parallel Turbo code interweaver and used in LTE (Long Term Evolution)
US9325351B2 (en) * 2013-03-13 2016-04-26 Mediatek Singapore Pte. Ltd. Adaptive multi-core, multi-direction turbo decoder and related decoding method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101116249A (en) * 2005-02-03 2008-01-30 松下电器产业株式会社 Parallel interleaver, parallel deinterleaver, and interleave method
CN101707490A (en) * 2009-09-22 2010-05-12 重庆重邮信科通信技术有限公司 Parallel Turbo code interleaving method
CN102035557A (en) * 2009-09-27 2011-04-27 中兴通讯股份有限公司 Method and device for interweaving turbo codes in parallel
US20130198529A1 (en) * 2010-10-18 2013-08-01 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Sample carrier unit having sample data encryption and method for use thereof

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