CN112332870A - Decoding method, device, communication chip and network equipment - Google Patents

Decoding method, device, communication chip and network equipment Download PDF

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CN112332870A
CN112332870A CN202011264556.3A CN202011264556A CN112332870A CN 112332870 A CN112332870 A CN 112332870A CN 202011264556 A CN202011264556 A CN 202011264556A CN 112332870 A CN112332870 A CN 112332870A
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decoding
iterative decoding
decoder
iterative
extrinsic information
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刘君
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques

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Abstract

The embodiment of the application discloses a decoding method, a decoding device, a communication chip and network equipment, and belongs to the technical field of communication. The method comprises the following steps: in the process of carrying out iterative decoding on a code block, obtaining decoding bits and extrinsic information output by a current decoder, wherein the current decoder is a first decoder or a second decoder for carrying out iterative decoding; responding to the condition that the decoding bit does not pass the verification, and acquiring the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2; and stopping iterative decoding in response to the n absolute value means meeting the iterative decoding convergence condition. By adopting the scheme provided by the embodiment of the application, good decoding performance can be ensured, the iterative decoding times do not need to wait until reaching the maximum iterative decoding times, the decoding time delay is further reduced, and the effect of improving the decoding speed is achieved.

Description

Decoding method, device, communication chip and network equipment
Technical Field
The embodiment of the application relates to the technical field of communication, in particular to a decoding method, a decoding device, a communication chip and network equipment.
Background
The Turbo code is a parallel cascade convolutional code, and has superior performance and stronger anti-fading and anti-interference capabilities when the signal-to-noise ratio is low, so that the Turbo code is widely applied to a digital communication system.
In the related art, Turbo decoding uses two decoders to perform iterative decoding to achieve good decoding performance, iteration is stopped according to maximum iteration times and Cyclic Redundancy Check (CRC), when a Signal-to-Noise Ratio (SNR) is low, the CRC fails, and at this time, the setting of the maximum iteration times is not reasonable, which may cause poor decoding performance or long decoding delay.
Disclosure of Invention
The embodiment of the application provides a decoding method, a decoding device, a communication chip and network equipment. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a decoding method, where the method includes:
in the process of carrying out iterative decoding on a code block, obtaining decoding bits and extrinsic information output by a current decoder, wherein the current decoder is a first decoder or a second decoder for carrying out iterative decoding;
responding to the condition that the decoding bit does not pass the verification, and acquiring the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2;
and stopping iterative decoding in response to the n absolute value means meeting the iterative decoding convergence condition.
In another aspect, an embodiment of the present application provides a decoding apparatus, where the apparatus includes:
the decoding circuit is used for acquiring decoding bits and extrinsic information output by a current decoder in the iterative decoding process of a code block, wherein the current decoder is a first decoder or a second decoder for iterative decoding;
the check circuit is used for responding to the condition that the decoding bit does not pass the check, obtaining the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2;
and the control circuit is used for responding that the n absolute value mean values meet the convergence condition of iterative decoding and stopping the iterative decoding.
On the other hand, an embodiment of the present application provides a communication chip, where the communication chip is used to implement the above decoding method.
In another aspect, an embodiment of the present application provides a network device, where the network device includes a processor, a memory, and a transceiver, and the processor is connected to the transceiver and the memory respectively;
the processor includes a communication chip as described in the above aspect.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
in the embodiment of the application, decoding bits obtained by decoding of the first decoder or the second decoder are checked at first, if the check fails, the absolute value mean value of the extrinsic information of the latest n times of iterative decoding is obtained, and because the extrinsic information tends to be stable in the iterative decoding process, the absolute value mean value of the extrinsic information is used for judging whether the iterative decoding convergence condition is met or not, when the condition is met, the iterative decoding is stopped, good decoding performance is ensured, the iterative decoding times do not need to wait for reaching the maximum iterative decoding times, decoding time delay is reduced, and the effect of improving the decoding speed is achieved.
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FIG. 1 is a block diagram of a communication system provided in an exemplary embodiment of the present application;
FIG. 2 illustrates a method flow diagram of a decoding method provided by an exemplary embodiment of the present application;
FIG. 3 illustrates a method flow diagram of a decoding method provided by another exemplary embodiment of the present application;
FIG. 4 is a diagram illustrating an implementation of an encoding method provided by an exemplary embodiment of the present application;
fig. 5 is a schematic diagram illustrating an implementation of a decoding method according to an exemplary embodiment of the present application;
FIG. 6 illustrates a method flow diagram of a decoding method provided by another exemplary embodiment of the present application;
fig. 7 is a schematic diagram illustrating an implementation of a decoding method according to an exemplary embodiment of the present application;
fig. 8 is a block diagram illustrating a decoding apparatus according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a network device according to an exemplary embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
Fig. 1 shows a block diagram of a communication system provided by an exemplary embodiment of the present application, which may include: base station 101 and terminal 102.
The base station 101 is a device deployed in an access network to provide a wireless communication function for a terminal. The base stations may include various forms of macro base stations, micro base stations, relay stations, access points, and the like. In systems using different radio access technologies, names of devices having a base station function may be different, for example, in a Long Term Evolution (LTE) system, the device is called an evolved Node B (eNodeB) or eNB; in a 5G NR-U system, it is called gNodeB or gNB. The description of "base station" may change as communication technology evolves.
The terminal 102 may include various handheld devices, vehicle mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem with wireless communication capabilities, as well as various forms of user equipment, Mobile Stations (MSs), terminal equipment (terminal device), and so forth. For convenience of description, the above-mentioned devices are collectively referred to as a terminal. Base station 101 and terminal 102 may communicate wirelessly.
In the process of sending information to the terminal 102 by the base station 101, the base station 101 encodes and sends the information, and the terminal 102 can decode the received code block by using the decoding method provided by the embodiment of the application; in the process of transmitting information to the base station 101 by the terminal 102, the terminal 102 encodes and transmits the information, and the base station 101 may decode the received code block by using the decoding method provided by the embodiment of the present application. It can be seen that the decoding method provided in the embodiment of the present application can be applied to both a terminal and a base station, and the embodiment of the present application does not limit this. In order to facilitate the description of the embodiments of the present application, the following embodiments schematically illustrate an application of the decoding method to a network device.
In the related art, Turbo iterative decoding is terminated using the following two methods.
Firstly, presetting maximum iteration times, and terminating iterative decoding when the iteration times of a decoder reach the maximum iteration times;
and secondly, combining the maximum iteration times with CRC (cyclic redundancy check), performing CRC check on the decoded bits obtained by the decoder each time, if the CRC check passes, terminating iterative decoding, and if the CRC check does not pass, continuing checking until the check passes or the maximum iteration times are reached, and terminating iteration.
By adopting the scheme, if the maximum iteration times are set to be too small, the decoding performance is poor, namely the decoding block error rate is high; if the maximum iteration time is set to be too large, if the SNR is low and the CRC check is invalid, only the iterative decoding time can be waited for reaching the maximum iterative decoding time, and at the moment, overlong decoding time delay is caused, and the decoding efficiency is influenced.
In the embodiment of the application, the iterative decoding is terminated by utilizing the characteristic that the extrinsic information tends to be stable in the iterative decoding process. The setting of the maximum iteration times can be unlimited, and when the SNR is higher and the iteration decoding times are less, CRC check can be passed; when the SNR is low, the CRC check can not pass continuously, when the convergence of the external information is detected, the iteration is stopped, the iterative decoding times are reduced under the condition that the performance loss is small, the maximum iterative times do not need to be waited for, and the decoding time delay is reduced. In addition, in the present application, the maximum iteration number setting is large, which does not affect the decoding delay, and in the related art, the maximum iteration number needs to be used to stop the iteration, so the maximum iteration number setting cannot be too large.
Illustratively, if the maximum iteration number is set to 30, in the case that the CRC check cannot pass, the iteration decoding number in the related art must reach 30 to terminate the iteration, but in the actual decoding process, when the iteration decoding number may reach 10, the extrinsic information tends to be stable, and the decoding performance is not improved by the remaining 20 iteration decoding, but a longer decoding delay is caused. In the method, iteration is stopped when the external information is detected to be stable, the iterative decoding times are obviously reduced compared with those in the related technology, and the effect of reducing the decoding time delay is further achieved.
Referring to fig. 2, a flowchart of a decoding method according to an exemplary embodiment of the present application is shown. The embodiment is described by taking the method as an example for a network device, and the network device is provided with a communication chip to execute the method, and the method may include the following steps.
Step 201, in the process of performing iterative decoding on a code block, obtaining a decoding bit and extrinsic information output by a current decoder, where the current decoder is a first decoder or a second decoder performing iterative decoding.
The extrinsic information refers to reliability information extracted for each bit using codeword correlation between decoded bits. Each decoder can generate unique error correction information, namely extrinsic information in the decoding process, and the extrinsic information is provided for the next decoder to carry out further error correction, so that the error correction capability of the next decoder is improved, and the decoding block error rate is further reduced.
In a possible implementation manner, when performing iterative decoding on a code block, a first decoder decodes and outputs decoding bits and extrinsic information, the extrinsic information is input to a second decoder as prior information of the second decoder, the second decoder performs decoding by using the obtained extrinsic information and other information to obtain new decoding bits and extrinsic information, the new extrinsic information is input to the first decoder as prior information of the first decoder, the first decoder performs decoding according to the new extrinsic information and other information to obtain the decoding bits and extrinsic information again, and the first decoder and the second decoder perform iterative decoding by using continuously updated extrinsic information. And after the first decoder or the second decoder decodes each time, obtaining decoding bits and external information obtained by decoding so as to judge by using the decoding bits and the external information subsequently, and further terminating iterative decoding and outputting a final decoding result.
And 202, in response to the fact that the decoding bit does not pass the check, obtaining an absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2.
Optionally, in the embodiment of the present application, the iterative decoding may be terminated by decoding bits obtained by the decoding and the extrinsic information.
In a possible implementation manner, the decoding bits obtained by the decoder each time are checked, and if the check is successful, the iterative decoding is stopped; and if the check fails, acquiring extrinsic information output by iterative decoding of the current decoder, and carrying out average operation on the absolute value of the extrinsic information to obtain and store an absolute value mean value. Optionally, in order to reduce the amount of computation, in the embodiment of the present application, the obtained extrinsic information of a part of bits may be selected to perform an average operation. Namely, when the code block size is K, K' is less than or equal to K pieces of extrinsic information can be selected to calculate the mean absolute value, and the calculation mode is as follows:
Figure BDA0002775689970000051
wherein the content of the first and second substances,
Figure BDA0002775689970000052
mean absolute value, L, representing the nth extrinsic informatione(k) Represents the k-th bit of extrinsic information.
In the embodiment of the application, the network device stores the mean absolute value of the extrinsic information output by the latest n times of iterative decoding, and n is an integer greater than or equal to 2.
In a possible implementation manner, when the stored absolute value mean reaches n, the First decoder or the second decoder outputs new extrinsic information, the absolute value mean of the extrinsic information stored for the longest time needs to be deleted, and the new absolute value mean of the extrinsic information is added, that is, the stored absolute value mean is updated according to a First In First Out (FIFO) principle.
And step 203, stopping iterative decoding in response to that the n absolute value means meet the iterative decoding convergence condition.
In the iterative decoding process, the extrinsic information gradually tends to be stable, and at this time, when the first decoder or the second decoder generates new extrinsic information and inputs the new extrinsic information to the next decoder, new error correction information cannot be provided, further iteration cannot or only can bring small performance gain, but decoding delay is increased, and at this time, iterative decoding needs to be stopped.
In a possible implementation manner, when the n absolute value means satisfy the convergence condition of iterative decoding, that is, it is determined that the extrinsic information after n iterations converges and tends to be stable, and the iterative decoding is stopped.
Judging whether an iterative decoding convergence condition is reached according to the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, further determining the extrinsic information convergence, and indicating that the iterative decoding performance reaches or approaches to the best, stopping the iterative decoding at the moment can ensure the decoding performance, namely the decoding block error rate is lower, and compared with the prior art in which the iterative decoding can be stopped when the maximum iterative decoding frequency is reached, the method can reduce the iteration frequency after the extrinsic information tends to be stable, and further reduce the decoding time delay.
To sum up, in the embodiment of the present application, a decoding bit obtained by decoding by the first decoder or the second decoder is checked, if the check fails, an absolute value mean of extrinsic information of the latest n iterative decoding is obtained, and since the extrinsic information tends to be stable in the iterative decoding process, the embodiment of the present application determines whether an iterative decoding convergence condition is satisfied by using the absolute value mean of the extrinsic information, and when the condition is satisfied, the iterative decoding is stopped, so that a good decoding performance is ensured, and it is not necessary to wait for the iterative decoding times to reach the maximum iterative decoding times, so as to reduce the decoding delay, and achieve the effect of increasing the decoding speed.
During the iterative decoding process, the extrinsic information gradually tends to be stable. In the embodiment of the application, a fluctuation coefficient is introduced to represent the stability degree of the extrinsic information, the fluctuation coefficient is determined according to the mean value and the variance of the mean value of the absolute values of the n extrinsic information, and when the fluctuation coefficient meets a certain condition, iterative decoding is stopped.
Referring to fig. 3, a flowchart of a decoding method provided in another exemplary embodiment of the present application is shown, which may include the following steps.
Step 301, in the process of performing iterative decoding on a code block, obtaining a decoding bit and extrinsic information output by a current decoder, where the current decoder is a first decoder or a second decoder performing iteration.
Optionally, in this embodiment of the present application, the first decoder and the second decoder may use a Convolutional Code Decoder (DCC) using a Maximum A Posteriori (MAP) algorithm, and the Code block is obtained by using Turbo Code coding.
In one possible embodiment, as shown in FIG. 4, a Turbo encoder is composed of a first convolutional code encoder 401, a second convolutional code encoder 402, and an inner interleaver 403, and system information c is input to the first convolutional code encoder 401kObtaining mapped transmission symbols xkAnd encoding the check information zkC interleaved by the inner interleaver 403 is input to the second convolutional code encoder 402k', encoding to obtain check information zk'. The first convolutional code encoder 401 and the second convolutional code encoder 402 are respectively provided with 3 time delays, the number of states is 8, the code rate is 1/3, that is, 1 bit is input and 2 bits of redundant bits are added.
As shown in fig. 5, the Turbo decoder is composed of a first MAP DCC 501, a second MAP DCC 502, a first interleaver 503, a second interleaver 504, and a deinterleaver 505. When decoding for the first time, the extrinsic information is 0, and the system information c is decodedkLog likelihood ratio L ofr(ck) And log-likelihood ratio of the check information obtained by the first convolutional code encoder 401
Figure BDA0002775689970000071
Inputting the data into a first MAP DCC 501 for decoding to obtain decoded bits and extrinsic information Le,1(ck) The second MAP DCC 502 uses the log likelihood ratio of the system information interleaved by the second interleaver 504 and the log likelihood ratio of the check information obtained by the second convolutional code encoder 402
Figure BDA0002775689970000072
And the extrinsic information L interleaved by the first interleaver 503e,1(ck) Decoding to obtain new decoded bits and extrinsic information Le,2(ck) External information Le,2(ck) And the data is deinterleaved by a deinterleaver 505 and input into the first MAP DCC 501 again, the first MAP DCC 501 decodes again to obtain new decoding bits and extrinsic information, and the decoder continuously outputs the new extrinsic information by using the two MAP DCCs to realize iterative decoding.
Step 302, updating the iterative decoding times.
In the embodiment of the application, the maximum iteration times are set to terminate the iteration besides the iteration is terminated by using the decoding bits and the external information. In a possible embodiment, after each decoding of the decoder, the iterative decoding number is updated, i.e. the iterative decoding number is increased by one.
Step 303, in response to the iterative decoding times reaching the maximum iterative decoding times, stopping the iterative decoding.
In a possible implementation manner, after each decoding, the currently accumulated iterative decoding times are detected, and when the iterative decoding times reach the maximum iterative decoding times, the iterative decoding is stopped. It should be noted that, in the embodiment of the present application, if a decoded bit does not pass the check or an absolute value mean of extrinsic information does not reach an iterative decoding convergence condition, but reaches the maximum iterative decoding number, the iterative decoding still needs to be terminated, so as to avoid causing an excessive decoding delay.
And 304, responding to the condition that the decoding bit does not pass the verification, and acquiring the absolute value mean value of the external information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2.
Optionally, in this embodiment of the present application, CRC check is performed on the decoding bits output by the MAP DCC, if the check passes, a decoding result is output to terminate iteration, and if the check fails, an absolute value average of extrinsic information obtained by the last n times of iterative decoding needs to be obtained to determine whether an iterative decoding convergence condition is satisfied. It should be noted that CRC check may be directly performed on decoded bits output by first MAP DCC 501, and CRC check may be performed on decoded bits output by second MAP DCC 502 after deinterleaving by a deinterleaver.
And 305, determining a fluctuation coefficient according to the mean value and the variance of the mean value of the n absolute values, wherein the fluctuation coefficient is used for representing the stability degree of the external information.
In the embodiment of the application, the iterative decoding convergence condition is judged by using the fluctuation coefficient. In a possible implementation manner, the fluctuation coefficient is a ratio of a variance to a mean of n absolute values to represent a fluctuation degree of the continuously updated extrinsic information, and the fluctuation degree is represented by the variance and the mean, so that compared with the fluctuation degree represented by the variance, the problem that the judgment is interfered due to the fact that the variance is smaller because of the smaller mean can be avoided.
Alternatively, most recent N1The sequence of absolute mean values can be expressed as:
Figure BDA0002775689970000081
the mean value calculation method is as follows:
Figure BDA0002775689970000082
wherein mu is the nearest N1The mean of the individual absolute values,
Figure BDA0002775689970000083
is the nth mean absolute value.
The variance calculation mode is as follows:
Figure BDA0002775689970000084
wherein σ2Is the nearest N1Variance of mean absolute values.
In one possible embodiment, the coefficient of fluctuation is expressed as σ2/μ2。
It should be noted that, in order to reduce the calculation amount, in another possible implementation, the variance calculation method is as follows:
Figure BDA0002775689970000085
accordingly, the fluctuation coefficient can be expressed as σ/μ.
In step 306, the code block size of the code block is obtained.
The code block sizes of different code blocks are different, and the conditions that the external information tends to be stable in the decoding process are different. Therefore, in the embodiment of the present application, the code block size of the code block needs to be obtained, so as to determine a condition for measuring whether extrinsic information tends to be stable according to the code block size.
And 307, determining a fluctuation coefficient threshold according to the size of the code block, wherein the fluctuation coefficient threshold and the size of the code block are in a negative correlation relationship.
In the embodiment of the present application, the fluctuation coefficient threshold refers to a critical value of the fluctuation coefficient. In one possible implementation, the fluctuation coefficient threshold is obtained according to the obtained code block size simulation, and the threshold is in a negative correlation with the code block size, that is, the fluctuation coefficient threshold is smaller as the code block size increases.
It should be noted that, steps 306 and 307 may be executed when starting decoding, and the present application only describes the setting of the fluctuation coefficient threshold, and the execution timing of the two steps is not limited.
Optionally, the network device may store a correspondence table between the fluctuation coefficient threshold and the code block size in advance, and when the code block size is obtained, the fluctuation coefficient threshold may be determined using the correspondence table. Illustratively, the correspondence table may be as shown in table 1:
TABLE 1
Code block size Coefficient of fluctuation threshold
>5000 0.04
3000-5000 0.08
1000-3000 0.12
＜1000 0.16
For example, when the obtained code block size is 6144, the fluctuation coefficient threshold may be determined to be 0.04.
And step 308, in response to the fluctuation coefficient being smaller than the fluctuation coefficient threshold value, stopping iterative decoding.
In a possible implementation manner, when the ripple coefficient is smaller than the ripple coefficient threshold, it indicates that the n absolute value means converge, that is, the extrinsic information tends to be stable, the error correction capability of the next decoder is not further improved, and the iterative decoding needs to be stopped. Optionally, when σ is satisfied2/μ2And when the alpha is less than or equal to alpha, determining that the iterative decoding convergence condition is met, wherein the alpha is a fluctuation coefficient threshold, and at the moment, stopping the iterative decoding.
Combining the example in the above steps, the obtained code block size is 6144, if n is 8, the absolute value mean of the extrinsic information of the latest 8 times of iterative decoding is obtained, and when σ of 8 absolute value means is obtained2/μ2When the value is less than 0.04, the iterative decoding convergence condition is satisfied, and then the iterative decoding can be stopped.
In addition, after the fluctuation coefficient of the absolute value mean value of the extrinsic information of the latest n times of iterative decoding meets the convergence condition, the subsequently updated extrinsic information may still fluctuate, and in order to ensure that the extrinsic information is continuously in a stable state, a termination counter is introduced in the embodiment of the present application, and when the value of the termination counter reaches a certain condition, the iterative process is terminated.
Referring to fig. 6, a flowchart of a decoding method provided in another exemplary embodiment of the present application is shown, which may include the following steps.
Step 601, in the process of iterative decoding of the code block, obtaining the decoding bits and extrinsic information output by the current decoder, wherein the current decoder is the first decoder or the second decoder for iteration.
Step 602, updating the iterative decoding times.
Step 603, in response to the iterative decoding times reaching the maximum iterative decoding times, stopping the iterative decoding.
And step 604, in response to the fact that the decoding bit does not pass the check, obtaining an absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2.
And step 605, determining a fluctuation coefficient according to the mean value and the variance of the n absolute value means, wherein the fluctuation coefficient is used for representing the stability degree of the external information.
Step 606, code block size of the code block is obtained.
Step 607, determining the fluctuation coefficient threshold according to the code block size, wherein the fluctuation coefficient threshold and the code block size are in a negative correlation relationship.
Step 601 to step 607 refer to step 301 to step 307, which is not described again in this embodiment.
In response to the volatility factor being less than the volatility factor threshold, the termination counter is updated, step 608.
In a possible implementation manner, the stored absolute value mean of the extrinsic information of the latest n times of iterative decoding is continuously updated along with the iterative decoding, and after each update, the mean and the variance of n absolute value means in the latest sequence need to be calculated to obtain the fluctuation coefficient. And if the fluctuation coefficient of the mean value of the n absolute values in the latest sequence is smaller than the fluctuation coefficient threshold value, the count of the termination counter is increased by one, and the termination counter is used for indicating the termination of iterative decoding.
Illustratively, the absolute value mean value of the extrinsic information of the latest 8 iterative decoding can be obtained, the fluctuation coefficient of the absolute value mean value of the 1 st to 8 th iterative decoding is smaller than alpha, and the value rho of the stop counter becomes 1; after one iterative decoding is performed, the absolute value mean of the last 8 times is updated to the absolute value mean of the extrinsic information of the 2 nd to 9 th iterative decoding, and when the fluctuation coefficient of the absolute value mean of the 2 nd to 9 th iterative decoding is smaller than alpha, the count rho of the stop counter becomes 2.
And step 609, responding to the fluctuation coefficient being larger than the fluctuation coefficient threshold value, and clearing the termination counter.
In one possible embodiment, there may be a fluctuation coefficient of the absolute value mean of the last n times greater than a fluctuation coefficient threshold, i.e., σ2/μ2>When alpha is reached, the external information is not completely converged, and the termination counter needs to be cleared. And when the fluctuation coefficients of the n absolute value mean values in the sequence updated subsequently meet the convergence condition of iterative decoding, increasing the count of the termination counter by one.
With reference to the example in the above step, the count ρ of the current termination counter is 2, and when the fluctuation coefficient of the mean absolute value of the extrinsic information of the 3 rd to 9 th iterative decoding is greater than α, the termination counter needs to be cleared, that is, the value ρ of the termination counter becomes 0. If the fluctuation coefficient of the mean absolute value of the extrinsic information of the 4 th to 10 th iterative decoding is smaller than α, the value of the termination counter becomes 1.
Step 610, obtaining a decoding performance requirement, wherein the decoding performance requirement includes a decoding block error rate requirement and a decoding speed requirement.
Optionally, in this embodiment of the present application, a decoding performance requirement needs to be obtained to determine a count threshold of the termination counter in the following step, where the decoding performance requirement includes a decoding block error rate requirement and a decoding speed requirement. The higher the requirement of the decoding block error rate is, the lower the block error rate to be achieved by decoding is, and the requirement of the decoding block error rate can be represented by the upper limit of the decoding block error rate, for example, if the upper limit of the decoding block error rate is 10%, the requirement of the decoding block error rate is determined to be lower; and if the upper limit of the decoding block error rate is 1%, determining that the decoding block error rate is higher in demand.
Alternatively, the decoding speed may be determined according to the type of service to which the decoding is applied. In a possible implementation manner, the corresponding relationship between the service type and the decoding speed level may be stored in advance, and the decoding speed requirement may be determined according to the service applied by the current decoding. Schematically, as shown in table 2:
TABLE 2
Type of service Speed of decoding
Voice call service Fast speed
Video call service Medium and high grade
Short message service Low speed
Step 611, determining a counting threshold according to the decoding performance requirement, wherein the counting threshold is in a positive correlation with the decoding block error rate requirement, and the counting threshold is in a negative correlation with the decoding speed requirement.
In the embodiment of the present application, the count threshold of the termination counter is related to the decoding performance requirement. In one possible embodiment, the counting threshold is determined according to the coding block error rate requirement, and the coding block error rate requirement is in positive correlation with the counting threshold. When the requirement of the decoding block error rate is higher, the requirement of higher decoding accuracy rate is indicated, and a larger counting threshold value needs to be set to ensure the decoding accuracy. For example, the count threshold may be set to 5 when the upper limit of the decoding block error rate is 1%, and the count threshold may be set to 2 when the upper limit of the decoding block error rate is 10%.
In another possible embodiment, the count threshold is determined based on a decoding speed requirement, which is inversely related to the count threshold. When the decoding speed requirement is higher, the iterative decoding needs to be terminated as soon as possible, a smaller counting threshold value can be set, and the decoding speed is increased. For example, if the currently performed service type is a voice call service, the count threshold may be set to 2, and if the currently performed service type is a short message service, the count threshold may be set to 5.
In response to the count of the termination counter reaching a count threshold, iterative decoding is stopped, step 612.
In a possible implementation manner, when the count of the termination counter reaches the count threshold, which indicates that the latest n absolute value means all satisfy the convergence condition of the iterative decoding, the extrinsic information is continuously in a stable state, and the iterative decoding needs to be stopped at this time. I.e. satisfies rho>ρthThen stop the iterative decoding, rhothIs the count threshold.
In the embodiment of the application, the stability of the external information is measured by using the fluctuation coefficient, and in order to ensure that the external information is continuously in a stable state, the fluctuation coefficient of n mean absolute values is judged for many times, the termination counter is updated when the convergence condition of iterative decoding is met, and iterative decoding is stopped when the count of the termination counter reaches a certain value, so that the decoding performance is further ensured, and the requirement of the decoding block error rate is ensured.
The method is applied to Turbo decoding, the first decoder and the second decoder are MAP DCC, and CRC is adopted for decoding bits output by the first decoder and the second decoder. In an illustrative example, the complete process of the decoding method is shown in fig. 7.
Step 701, decoding the first MAP DCC or the second MAP DCC;
step 702, outputting decoding bits and extrinsic information;
step 703, detecting whether the maximum iteration number is reached, if so, executing step 712, and if not, executing step 704;
step 704, performing CRC check on the decoded bits, if successful, performing step 712, and if failed, performing step 705;
step 705, calculating and storing the absolute value mean value of the extrinsic information;
step 706, detecting whether the stored absolute value mean value reaches n, if yes, executing step 707;
step 707, calculating the mean and variance of the n absolute value means to obtain a fluctuation coefficient;
step 708, determining whether the fluctuation coefficient is smaller than α, if so, executing step 709, and if so, executing step 710;
step 709, ending the counter and adding one;
step 710, clearing the termination counter;
step 711, detecting whether the count of the termination counter is greater than ρ, if so, executing step 712, and if not, executing step 701;
step 712, stop the iterative decoding.
Referring to fig. 8, a block diagram of a decoding apparatus according to an embodiment of the present application is shown. The device includes:
a decoding circuit 801, configured to obtain a decoding bit and extrinsic information output by a current decoder during iterative decoding of a code block, where the current decoder is a first decoder or a second decoder that performs iterative decoding;
the check circuit 802 is configured to, in response to that the decoded bit fails to pass the check, obtain an absolute value average of the extrinsic information obtained by the last n iterative decoding, where n is an integer greater than or equal to 2;
and the control circuit 803 is configured to stop the iterative decoding in response to that the n absolute value averages satisfy an iterative decoding convergence condition.
Optionally, the control circuit 803 is further configured to:
determining a fluctuation coefficient according to the mean value and the variance of the n absolute value means, wherein the fluctuation coefficient is used for representing the stability degree of the extrinsic information;
and stopping the iterative decoding in response to the fluctuation coefficient being smaller than a fluctuation coefficient threshold value.
Optionally, the decoding circuit 801 is further configured to obtain a code block size of the code block;
optionally, the control circuit 803 is further configured to determine the fluctuation coefficient threshold according to the code block size, where the fluctuation coefficient threshold and the code block size are in a negative correlation relationship.
Optionally, the control circuit 803 is further configured to:
updating a termination counter in response to the volatility coefficient being less than the volatility coefficient threshold;
in response to the count of the termination counter reaching a count threshold, stopping iterative decoding.
Optionally, the decoding circuit 801 is further configured to obtain decoding performance requirements, where the decoding performance requirements include a decoding block error rate requirement and a decoding speed requirement.
Optionally, the control circuit 803 is further configured to determine the count threshold according to the decoding performance requirement, where the count threshold is in a positive correlation with the decoding block error rate requirement, and the count threshold is in a negative correlation with the decoding speed requirement.
Optionally, the control circuit 803 is further configured to clear the termination counter in response to the fluctuation coefficient being greater than the fluctuation coefficient threshold.
Optionally, the decoding circuit 801 is further configured to update the iterative decoding times.
Optionally, the control circuit 803 is further configured to stop the iterative decoding in response to that the iterative decoding number reaches the maximum iterative decoding number.
Optionally, the first decoder and the second decoder in the decoding apparatus are MAP DCC decoders, the code block is obtained by Turbo code encoding, and the check mode of the decoded bits is CRC check.
In the embodiment of the application, decoding bits obtained by decoding of the first decoder or the second decoder are checked at first, if the check fails, the absolute value mean value of the extrinsic information of the latest n times of iterative decoding is obtained, and because the extrinsic information tends to be stable in the iterative decoding process, the absolute value mean value of the extrinsic information is used for judging whether the iterative decoding convergence condition is met or not, when the condition is met, the iterative decoding is stopped, good decoding performance is ensured, the iterative decoding times do not need to wait for reaching the maximum iterative decoding times, decoding time delay is reduced, and the effect of improving the decoding speed is achieved.
In the embodiment of the application, the stability of the external information is measured by using the fluctuation coefficient, and in order to ensure that the external information is continuously in a stable state, the fluctuation coefficient of n absolute value means is judged for many times, the termination counter is updated when the condition is met, and iterative decoding is stopped when the count of the termination counter reaches a certain value, so that the decoding performance is further ensured, and the requirement of the decoding block error rate is ensured.
The embodiment of the application also provides a communication chip which executes the decoding method.
Referring to fig. 9, a schematic structural diagram of a network device according to an exemplary embodiment of the present application is shown. The communication device comprises a processor 901, a memory 902 and a transceiver 903, wherein the processor 901 is connected with the transceiver 903 and the memory 902 respectively. The processor 901 includes a communication chip as provided in the above embodiments.
Processor 901 may include one or more processing cores. The processor 901 connects various parts within the overall network device using various interfaces and lines, and performs various functions of the network device and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 902 and calling data stored in the memory 902. Alternatively, the processor 901 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 901 may integrate one or a combination of several of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural-Network Processing Unit (NPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing contents required to be displayed by the touch display screen; the NPU is used for realizing an Artificial Intelligence (AI) function; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 901, but may be implemented by a single chip. And the processor 901 includes the communication chip provided in the above embodiments.
The Memory 902 may include a Random Access Memory (RAM) or a Read-Only Memory (ROM). Optionally, the memory 902 includes a non-transitory computer-readable medium. The memory 902 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 902 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like; the storage data area may store data (such as audio data, a phonebook) created according to the use of the network device, and the like.
The transceiver 903 may be implemented as a communication component, which may be a chip.
Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (11)

1. A method of decoding, the method comprising:
in the process of carrying out iterative decoding on a code block, obtaining decoding bits and extrinsic information output by a current decoder, wherein the current decoder is a first decoder or a second decoder for carrying out iterative decoding;
responding to the condition that the decoding bit does not pass the verification, and acquiring the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2;
and stopping iterative decoding in response to the n absolute value means meeting the iterative decoding convergence condition.
2. The method of claim 1, wherein stopping iterative decoding in response to n of the absolute value means satisfying an iterative decoding convergence condition comprises:
determining a fluctuation coefficient according to the mean value and the variance of the n absolute value means, wherein the fluctuation coefficient is used for representing the stability degree of the extrinsic information;
and stopping the iterative decoding in response to the fluctuation coefficient being smaller than a fluctuation coefficient threshold value.
3. The method of claim 2, wherein before stopping iterative decoding in response to the ripple coefficient being less than a ripple coefficient threshold, the method further comprises:
obtaining a code block size of the code block;
and determining the fluctuation coefficient threshold according to the code block size, wherein the fluctuation coefficient threshold and the code block size are in a negative correlation relationship.
4. The method of claim 2, wherein stopping iterative decoding in response to the ripple coefficient being less than a ripple coefficient threshold comprises:
updating a termination counter in response to the volatility coefficient being less than the volatility coefficient threshold;
in response to the count of the termination counter reaching a count threshold, stopping iterative decoding.
5. The method of claim 4, wherein before stopping iterative decoding in response to the count of the termination counter reaching a count threshold, the method further comprises:
acquiring decoding performance requirements, wherein the decoding performance requirements comprise a decoding block error rate requirement and a decoding speed requirement;
and determining the counting threshold according to the coding performance requirement, wherein the counting threshold is in positive correlation with the coding block error rate requirement, and the counting threshold is in negative correlation with the coding speed requirement.
6. The method of claim 4, further comprising:
clearing the termination counter in response to the ripple coefficient being greater than the ripple coefficient threshold.
7. The method according to any one of claims 1 to 6, wherein after obtaining the decoded bits and extrinsic information output by the current decoder, the method further comprises:
updating the iterative decoding times;
and stopping the iterative decoding in response to the iterative decoding times reaching the maximum iterative decoding times.
8. The method according to any of claims 1 to 6, wherein said first decoder and said second decoder are maximum a posteriori convolutional decoders MAP DCC, said code blocks are obtained by Turbo coding, and said check mode of said decoded bits is cyclic redundancy check CRC.
9. An apparatus for decoding, the apparatus comprising:
the decoding circuit is used for acquiring decoding bits and extrinsic information output by a current decoder in the iterative decoding process of a code block, wherein the current decoder is a first decoder or a second decoder for iterative decoding;
the check circuit is used for responding to the condition that the decoding bit does not pass the check, obtaining the absolute value mean value of the extrinsic information obtained by the latest n times of iterative decoding, wherein n is an integer greater than or equal to 2;
and the control circuit is used for responding that the n absolute value mean values meet the convergence condition of iterative decoding and stopping the iterative decoding.
10. A communication chip, characterized in that the communication chip is used to implement the decoding method according to any one of claims 1 to 8.
11. A network device, comprising a processor, a memory, and a transceiver, wherein the processor is connected to the transceiver and the memory, respectively;
the processor comprises the communication chip of claim 10.
CN202011264556.3A 2020-11-12 2020-11-12 Decoding method, device, communication chip and network equipment Pending CN112332870A (en)

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