CN105789152A - Multi-chip laminating structure with electromagnetic shielding function and manufacturing method thereof - Google Patents

Multi-chip laminating structure with electromagnetic shielding function and manufacturing method thereof Download PDF

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Publication number
CN105789152A
CN105789152A CN201610272416.8A CN201610272416A CN105789152A CN 105789152 A CN105789152 A CN 105789152A CN 201610272416 A CN201610272416 A CN 201610272416A CN 105789152 A CN105789152 A CN 105789152A
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CN
China
Prior art keywords
chip
upper strata
substrate
lower layer
layer chip
Prior art date
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Pending
Application number
CN201610272416.8A
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Chinese (zh)
Inventor
王仕勇
包旭升
王孙艳
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201610272416.8A priority Critical patent/CN105789152A/en
Publication of CN105789152A publication Critical patent/CN105789152A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention relates to a multi-chip laminating structure with an electromagnetic shielding function and a manufacturing method thereof. The multi-chip laminating structure comprises a substrate (1) on which an upper-layer chip (2) and a lower-layer chip (6) are arranged. The front surface of the upper-layer chip is connected with the substrate (1) through a welding wire (5). The back surface of the upper-layer chip (2) is provided with a trough (3). The surface of the trough (3) and the back surface of the upper-layer chip (2) are respectively provided with a shielding metal layer (4). The lower-layer chip (6) is arranged in the area of the trough (3) at the back surface of the upper-layer chip (2). Molding compound (8) packages the peripheral areas of the upper-layer chip (2) and the welding wire (5). According to the multi-chip laminating structure with the electromagnetic shielding function and the manufacturing method thereof, through forming the trough on the back surface of the upper-layer chip, sputtering the shielding metal layer and accommodating the lower-layer chip in the trough of the upper-layer chip, electromagnetic shielding on the lower-layer chip is formed.

Description

A kind of multi-chip closed assembly structure with electro-magnetic screen function and manufacture method thereof
Technical field
The present invention relates to a kind of multi-chip closed assembly structure with electro-magnetic screen function and manufacture method thereof, belong to technical field of semiconductor encapsulation.
Background technology
The electromagnetic shielding method of existing encapsulating structure is roughly divided into two kinds: use metal cap to be covered by the chip needing shielding, play shielding action, or on plastic-sealed body, directly pass through the mode sputtering or electroplating, cover metal on plastic-sealed body surface, play the effect of electromagnetic shielding.But both approaches is difficult to apply to the structure of multi-layer stacked chip.
Summary of the invention
The technical problem to be solved is to provide a kind of multi-chip closed assembly structure with electro-magnetic screen function and manufacture method thereof for above-mentioned prior art, it by doing sputtering shielding metal level after upper strata chip back is slotted, the groove of upper strata chip holds lower layer chip, thus reaching effectiveness.
This invention address that the technical scheme that the problems referred to above adopt is: a kind of multi-chip closed assembly structure with electro-magnetic screen function, it includes substrate, described substrate is provided with upper strata chip and lower layer chip, it is connected by bonding wire between described upper strata chip front side and substrate, described upper strata chip back offers groove, described groove surfaces and upper strata chip back are respectively provided with shielding metal level, described lower layer chip is arranged in the grooved area of upper strata chip back, and described upper strata chip and bonding wire outer peripheral areas are encapsulated with plastic packaging material.
It is electrically connected by metal ball between described lower layer chip and substrate.
The manufacture method of a kind of multi-chip closed assembly structure with electro-magnetic screen function, described method comprises the steps:
Step one, take a substrate, it would be desirable to the lower layer chip of shielding and substrate interconnection；
Step 2, taking a upper strata chip, the back side of upper strata chip is done slot treatment, the big I of groove covers lower layer chip；
Step 3, the bottom surface of upper strata chip after fluting and grooved area are formed follow-up required shielding metal level by sputtering；
Step 4, by, in upper strata chip attachment to substrate, making lower layer chip be contained in the grooved area of upper strata chip, will interconnect between upper strata chip and substrate；
Step 5, chip periphery region, upper strata is carried out plastic packaging material encapsulating.
Described lower layer chip has multiple.
Compared with prior art, it is an advantage of the current invention that:
A kind of multi-chip closed assembly structure with electro-magnetic screen function of the present invention and manufacture method thereof, it by doing sputtering shielding metal level after upper strata chip back is slotted, the groove of upper strata chip holds lower layer chip, thus lower layer chip is formed electromagnetic shielding, it is possible to suitable in the electromagnetic shielding between multiple laminated chips.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of multi-chip closed assembly structure with electro-magnetic screen function of the present invention.
Fig. 2 ~ Fig. 6 is each process flow chart of manufacture method of a kind of multi-chip closed assembly structure with electro-magnetic screen function of the present invention.
Wherein:
Substrate 1
Upper strata chip 2
Groove 3
Shielding metal level 4
Bonding wire 5
Lower layer chip 6
Metal ball 7
Plastic packaging material 8.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Figure 1, a kind of multi-chip closed assembly structure with electro-magnetic screen function in the present embodiment, it includes substrate 1, described substrate 1 is provided with upper strata chip 2 and lower layer chip 6, it is connected by bonding wire 5 between chip 2 front, described upper strata and substrate 1, groove 3 is offered at chip 2 back side, described upper strata, described groove 3 surface and upper strata chip 2 back side are respectively provided with shielding metal level 4, described lower layer chip 6 is arranged in groove 3 region at upper strata chip 2 back side, and described upper strata chip 2 and bonding wire 5 outer peripheral areas are encapsulated with plastic packaging material 8；
It is electrically connected by metal ball 7 phase between described lower layer chip 6 and substrate 1.
Its manufacturing process comprises the following steps:
Step one, referring to Fig. 1, take a substrate, it would be desirable to the lower layer chip of shielding is by upside-down mounting, bonding wire or other technique and substrate interconnection；
Step 2, referring to Fig. 2, take a upper strata chip, slot treatment done at the back side of upper strata chip, the big I of groove covers lower layer chip；
Step 3, referring to Fig. 3, the bottom surface of the upper strata chip after fluting and grooved area are formed follow-up required shielding metal level by sputtering；
Step 4, referring to Fig. 4, by, in upper strata chip attachment to substrate, making lower layer chip be contained in the grooved area of upper strata chip, will interconnect between upper strata chip and substrate；
Step 5, referring to Fig. 5, chip periphery region, upper strata is carried out plastic packaging material encapsulating.
Described lower layer chip can have multiple.
In addition to the implementation, present invention additionally comprises the technical scheme that other embodiments, all employing equivalents or equivalence substitute mode are formed, all should fall within the protection domain of the claims in the present invention.

Claims (4)

1. a multi-chip closed assembly structure with electro-magnetic screen function, it is characterized in that: it includes substrate (1), described substrate (1) is provided with upper strata chip (2) and lower layer chip (6), it is connected by bonding wire (5) between chip (2) front, described upper strata and substrate (1), groove (3) is offered at chip (2) back side, described upper strata, described groove (3) surface and upper strata chip (2) back side are respectively provided with shielding metal level (4), described lower layer chip (6) is arranged in groove (3) region at upper strata chip (2) back side, described upper strata chip (2) and bonding wire (5) outer peripheral areas are encapsulated with plastic packaging material (8).
2. a kind of multi-chip closed assembly structure with electro-magnetic screen function according to claim 1, it is characterised in that: it is electrically connected mutually by metal ball (7) between described lower layer chip (6) with substrate (1).
3. the manufacture method of a multi-chip closed assembly structure with electro-magnetic screen function, it is characterised in that described method comprises the steps:
Step one, take a substrate, it would be desirable to the lower layer chip of shielding and substrate interconnection；
Step 2, taking a upper strata chip, the back side of upper strata chip is done slot treatment, the big I of groove covers lower layer chip；
Step 3, the bottom surface of upper strata chip after fluting and grooved area are formed follow-up required shielding metal level by sputtering；
Step 4, by, in upper strata chip attachment to substrate, making lower layer chip be contained in the grooved area of upper strata chip, will interconnect between upper strata chip and substrate；
Step 5, chip periphery region, upper strata is carried out plastic packaging material encapsulating.
4. the manufacture method of a kind of multi-chip closed assembly structure with electro-magnetic screen function according to claim 3, it is characterised in that: described lower layer chip has multiple.
CN201610272416.8A 2016-04-28 2016-04-28 Multi-chip laminating structure with electromagnetic shielding function and manufacturing method thereof Pending CN105789152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610272416.8A CN105789152A (en) 2016-04-28 2016-04-28 Multi-chip laminating structure with electromagnetic shielding function and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610272416.8A CN105789152A (en) 2016-04-28 2016-04-28 Multi-chip laminating structure with electromagnetic shielding function and manufacturing method thereof

Publications (1)

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CN105789152A true CN105789152A (en) 2016-07-20

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564436A (en) * 2020-05-25 2020-08-21 甬矽电子(宁波)股份有限公司 Fan-out type packaging structure and packaging method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1819190A (en) * 2005-01-25 2006-08-16 松下电器产业株式会社 Semiconductor device
CN104701273A (en) * 2015-03-27 2015-06-10 江阴长电先进封装有限公司 Chip packaging structure with electromagnetic shielding function

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1819190A (en) * 2005-01-25 2006-08-16 松下电器产业株式会社 Semiconductor device
CN104701273A (en) * 2015-03-27 2015-06-10 江阴长电先进封装有限公司 Chip packaging structure with electromagnetic shielding function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111564436A (en) * 2020-05-25 2020-08-21 甬矽电子(宁波)股份有限公司 Fan-out type packaging structure and packaging method

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Application publication date: 20160720

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