CN105789108A - Power transistor chip manufacturing method and power transistor chip - Google Patents
Power transistor chip manufacturing method and power transistor chip Download PDFInfo
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- CN105789108A CN105789108A CN201410784914.1A CN201410784914A CN105789108A CN 105789108 A CN105789108 A CN 105789108A CN 201410784914 A CN201410784914 A CN 201410784914A CN 105789108 A CN105789108 A CN 105789108A
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Abstract
The present application discloses a power transistor chip manufacturing method and a power transistor chip. The manufacturing method comprises the following steps: forming a semiconductor substrate, and forming a power transistor on a front surface of the semiconductor substrate; forming a metal layer on a back surface of the semiconductor substrate; and forming a protective film on the metal layer, so as to stop steam from contacting the metal layer. According to the manufacturing method, the protective film is formed on the metal layer, and the protective film is used for stopping the steam from contacting the metal layer, so that white spot defects formed in the power transistor chip because the metal layer is oxidized by the steam in the air are reduced, and thus the performance of the power transistor chip is improved.
Description
Technical field
The application relates to the technical field of semiconductor integrated circuit, in particular to manufacture method and the power transistor chip of a kind of power transistor chip.
Background technology
Power transistor refers to the work for controlling power electronic device, and provides the semiconductor device of high-power output for load by controlling power electronic device.Common power transistor includes pin diode, IGCT, power field effect transistor and insulated gate bipolar transistor etc..At present, power transistor is widely used in control power output, and in the scanning circuit of the application resistance equipment of HF power transistor, for instance the power amplifier of transmitter, the rf output circuit of mobile phone, high-frequency oscillating circuits and high speed electronic switch circuit etc..
In the manufacturing process of power transistor chip, it is necessary to form metal level (i.e. back side metallization technology) at the back side of chip.Metal level mainly has the effect of two main aspects: first aspect is a main electrical current path of the operating current as power transistor chip, has electric action；When second aspect is transmission power transistor chip work, the thermal dissipating path of produced heat, has conductive force.Therefore, back side metallization technology all has a great impact for the performance of power transistor chip, reliability and stability.One good back side metallization technology requires its prepared metal level to have, and contact resistance is little, thermal resistance is low, stress is little and the feature such as good reliability.
After forming above-mentioned metal level, it is necessary to chip is carried out reliability testing and defect inspection, then again chip is carried out Vacuum Package.But, being formed to before Vacuum Package after metal level, the metal level of chip back is constantly exposed in air so that metal level by the steam in air (containing H2O and O2) oxidation, thus forming metal-oxide (i.e. white spot defect) on the surface of metal level, and then affect the performance (such as electric property etc.) of power transistor chip.For the problems referred to above, there is presently no effective solution.
Summary of the invention
The application aims to provide manufacture method and the power transistor chip of a kind of power transistor chip, with the white spot defect reduced in power transistor chip on metal level, thus improving the performance of power transistor chip.
To achieve these goals, this application provides the manufacture method of a kind of power transistor chip, this manufacture method comprises the following steps: forming semiconductor substrate, the front of semiconductor substrate is formed with power transistor；Metal level is formed at the back side of semiconductor substrate；Form protecting film on the metal layer, contact with metal level intercepting steam.
Further, protecting film is electron level adhesive film or hydrophobic membrane.
Further, electron level adhesive film is made up of organic polymer thin film and sticky agent.
Further, hydrophobic membrane is Kapton, polyethylene terephthalate, PEN polypropylene.
Further, when protecting film is electron level adhesive film, by attaching process metal level is formed protecting film；When protecting film is hydrophobic membrane, formed protecting film on the metal layer by depositing operation.
Further, before forming the step of protecting film, manufacture method also includes the step that the semiconductor substrate being formed with metal level carries out baking process.
Further, in the step that baking processes, carrying out baking process in a nitrogen atmosphere, baking temperature is 160～200 DEG C, baking time 100～180s.
Further, after forming the step of protecting film, manufacture method also includes the step carrying out reliability testing, defect inspection and Vacuum Package.
Further, the material of metal level is Ag, Ni or Ti.
Meanwhile, present invention also provides a kind of power transistor chip, this power transistor chip is made by the manufacture method that the application is above-mentioned.
The technical scheme of application the application; the application is by forming protecting film on the metal layer; and this protecting film is used for intercepting steam and contacts with metal level; thus decreasing the white spot defect formed by the steam oxidation in air in power transistor chip due to metal level, and then improve the performance of power transistor chip.
Accompanying drawing explanation
The Figure of description constituting the part of the application is used for providing further understanding of the present application, and the schematic description and description of the application is used for explaining the application, is not intended that the improper restriction to the application.In the accompanying drawings:
Fig. 1 illustrates the schematic flow sheet of the manufacture method of the power transistor chip that the application embodiment provides.
Detailed description of the invention
It should be noted that when not conflicting, the embodiment in the application and the feature in embodiment can be mutually combined.Describe the application below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to the restricted root illustrative embodiments according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to include plural form, in addition, it is to be further understood that, when using term " comprising " and/or " including " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For the ease of describing, here can use space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for describing the spatial relation of a device or feature and other devices or feature as shown in the figure.It should be appreciated that space relative terms is intended to the different azimuth in use or operation comprised except the orientation that device is described in the drawings.Such as, " in other devices or structure lower section " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can include " in ... top " and " in ... lower section " two kinds of orientation.This device can also other different modes location (90-degree rotation or be in other orientation), and space used herein above described relatively make respective explanations.
As what background technology was introduced, in the manufacture method of existing power transistor chip, be constantly exposed in air to the metal level of chip back before Vacuum Package being formed after metal level so that metal level by the steam in air (containing H2O and O2) oxidation, thus forming metal-oxide (i.e. white spot defect) on the surface of metal level, and then affect the performance of power transistor chip.
Present inventor studies for the problems referred to above, it is proposed that the manufacture method of a kind of power transistor chip.As it is shown in figure 1, this manufacture method comprises the following steps: forming semiconductor substrate, the front of semiconductor substrate is formed with power transistor；Metal level is formed at the back side of semiconductor substrate；Form protecting film on the metal layer, contact with metal level intercepting steam.
Above-mentioned manufacture method is by forming protecting film on the metal layer; and this protecting film is used for intercepting steam and contacts with metal level; thus decreasing the white spot defect formed by the steam oxidation in air in power transistor chip due to metal level, and then improve the performance of power transistor chip.
The illustrative embodiments of manufacture method according to provided herein power transistor chip is described in more detail below.But, these illustrative embodiments can be implemented by multiple different form, and should not be construed to be limited solely to embodiments set forth herein.It should be appreciated that these embodiments are provided so that disclosure herein is thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art.
First, forming semiconductor substrate, the front of this semiconductor substrate is formed with power transistor.Specifically, this step includes: provide wafer, forms power transistor in the front of wafer.Wherein, wafer is generally silicon chip, it is also possible to for new materials such as III-V such as SiGe (GeSi), carborundum (SiC) and GaAs.
In this step, power transistor can be pin diode, IGCT, power field effect transistor and insulated gate bipolar transistor etc..Being slightly different for its forming step of different power transistors, those skilled in the art is referred to prior art and makes power transistor.Being made as example with power field effect transistor, its manufacturing process includes being formed grid, source electrode and drain electrode and the step of groove and its manufacturing process more employing V trench process；Its grid is commonly made to V-type so that it is have the advantages such as raceway groove is short, voltage endurance capability is strong, transconductance linearity is good, switching speed is fast.
After completing the step of formation semiconductor substrate, form metal level at the back side of semiconductor substrate.Preferably, the material of metal level is Ag, Ni or Ti.Certainly, the material of metal level is not limited in above-mentioned preference.The technique forming metal level is generally adopted evaporation, it would however also be possible to employ chemical vapour deposition (CVD) or sputtering etc., its concrete technology parameter is referred to prior art.
To adopt evaporation to form Ag layer, it comprises the following steps: be placed in ag material as evaporation source in crucible, and is placed in vaporization chamber by semiconductor substrate；After evacuation, heating makes ag material evaporate so that silver atoms is deposited on the back side of semiconductor substrate with condensing mode.Its technological parameter can be set according to actual process demand, for instance evaporation temperature is 1000～1200 DEG C, and the evaporation time is 30～3min, the thickness of formed Ag layer be tens nanometers to a few micrometers.
Complete, after the back side of semiconductor substrate forms the step of metal level, to form protecting film on the metal layer, contact with metal level intercepting steam.This protecting film can be used in intercepting steam and contacts with metal level, thus realizing reducing the white spot defect formed by the steam oxidation in air in power transistor chip due to metal level, and improves the purpose of the performance of power transistor chip.
Those skilled in the art can set the kind of said protection film according to teachings of the present application.Preferably, protecting film is electron level adhesive film or hydrophobic membrane.Wherein, electron level adhesive film (Bluetape) is made up of organic polymer thin film and sticky agent, and organic polymer thin film can be Kapton etc., and sticky agent can be polyacrylic acid etc..When adopting electron level adhesive film as protecting film, it is possible to by attaching process metal level is formed protecting film.Visible, the while that the formation process of electron level adhesive film being simple, its removal is also easier to relatively, consequently facilitating reduce process costs etc..
Above-mentioned hydrophobic membrane can be have hydrophobic function in this area or intercept the material of steam function, for instance Kapton, polyethylene terephthalate, PEN polypropylene.This hydrophobic membrane is formed usually by depositing operation, and depositing operation can be chemical vapour deposition (CVD), evaporation etc., and its concrete technology parameter is referred to prior art.
In the manufacture method of the above-mentioned power transistor chip that the application provides; before forming the step of protecting film; the semiconductor substrate being formed with metal level can also be carried out baking process; steam with the evaporative removal semiconductor substrate back side (particularly on metal level); to reduce the contact of steam and metal level further; thus reducing the white spot defect formed by the steam oxidation in air due to metal level in power transistor chip further, and then improve the performance of power transistor chip further.
Above-mentioned baking processes can adopt technique common in prior art, and its technological parameter is referred to prior art.For example, in the step that baking processes, carrying out baking process in a nitrogen atmosphere, baking temperature is 160～200 DEG C, baking time 100～180s.Certainly, the technique that baking processes is not limited in above-described embodiment.
In the manufacture method of the above-mentioned power transistor chip that the application provides, after forming the step of protecting film, this manufacture method also includes the step carrying out reliability testing, defect inspection and Vacuum Package.Wherein, reliability testing includes resistance to puncturing test, leakage current test and life test etc., and its test process is referred to prior art；Defect inspection includes reducing whether contain residue defect etc., and its checking tool includes high power microscope, scanning electron microscope etc.；The step of Vacuum Package includes the technical processs such as metal bonding, and its concrete processing technology is referred to prior art.
Meanwhile, present invention also provides a kind of power transistor chip, this power transistor chip is made by the manufacture method that the application is above-mentioned.Metal level in this power transistor chip is formed with protecting film; this protecting film can be used in intercepting steam and contacts with metal level; thus decreasing the white spot defect formed by the steam oxidation in air in power transistor chip due to metal level, and then improve the performance of power transistor chip.
Illustrative embodiments according to the application is described in more detail below.But, these illustrative embodiments can be implemented by multiple different form, and should not be construed to be limited solely to embodiments set forth herein.It should be appreciated that these embodiments are provided so that disclosure herein is thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art.
The manufacture method of the power transistor chip that the application provides is further illustrated below in conjunction with embodiment.
Embodiment 1
Present embodiments provide the manufacture method of a kind of power transistor chip, comprise the following steps: first, form power field effect transistor in the front of silicon chip；Then, by evaporation process at the back side of silicon chip formation Ag layer；Finally, on Ag layer, electron level adhesive film (being made up of Kapton and polyacrylic acid) is formed by attaching process.
Embodiment 2
Present embodiments provide the manufacture method of a kind of power transistor chip, comprise the following steps: first, form power field effect transistor in the front of silicon chip；Then, by evaporation process at the back side of silicon chip formation Ag layer；Finally, formation of deposits Kapton on Ag layer.
Embodiment 3
Present embodiments provide the manufacture method of a kind of power transistor chip, comprise the following steps: first, form power field effect transistor in the front of silicon chip；Then, by evaporation process at the back side of silicon chip formation Ag layer；It follows that in a nitrogen atmosphere the wafer being formed with Ag layer is carried out baking process, baking temperature is 60 DEG C, and baking time is 2min；Finally, on Ag layer, electron level adhesive film (being made up of Kapton and polyacrylic acid) is formed by attaching process.
Comparative example 1
This comparative example provides the manufacture method of a kind of power transistor chip, comprises the following steps: first, forms power field effect transistor in the front of silicon chip；Then, by evaporation process at the back side of silicon chip formation Ag layer.
Test: by the surface topography of Ag layer in the power transistor chip that high power electron microscope observation embodiment 1 to 3 and comparative example 1 provide.It is shown that the Ag layer smooth surface in embodiment 1 to 3 is smooth, do not produce white spot defect；Ag layer surface in comparative example 1 creates a lot of white spot defect.
In from the description above; can be seen that; the application the above embodiments achieve following technique effect: the application is by forming protecting film on the metal layer; and this protecting film is used for intercepting steam and contacts with metal level; thus decreasing the white spot defect formed by the steam oxidation in air in power transistor chip due to metal level, and then improve the performance of power transistor chip.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.All within spirit herein and principle, any amendment of making, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (10)
1. the manufacture method of a power transistor chip, it is characterised in that described manufacture method comprises the following steps:
Forming semiconductor substrate, the front of described semiconductor substrate is formed with power transistor；
Metal level is formed at the back side of described semiconductor substrate；
Described metal level is formed protecting film, contacts with described metal level intercepting steam.
2. manufacture method according to claim 1, it is characterised in that described protecting film is electron level adhesive film or hydrophobic membrane.
3. manufacture method according to claim 2, it is characterised in that described electron level adhesive film is made up of organic polymer thin film and sticky agent.
4. manufacture method according to claim 2, it is characterised in that described hydrophobic membrane is Kapton, polyethylene terephthalate, PEN polypropylene.
5. the manufacture method according to any one of claim 2 to 4, it is characterised in that
When described protecting film is electron level adhesive film, by metal level described in attaching process is formed described protecting film；
When described protecting film is hydrophobic membrane, on described metal level, form described protecting film by depositing operation.
6. manufacture method according to claim 1, it is characterised in that before forming the step of described protecting film, described manufacture method also includes the step that the described semiconductor substrate being formed with described metal level carries out baking process.
7. manufacture method according to claim 6, it is characterised in that in the step that described baking processes, carries out described baking process in a nitrogen atmosphere, and baking temperature is 160～200 DEG C, baking time 100～180s.
8. manufacture method according to claim 1, it is characterised in that after forming the step of described protecting film, described manufacture method also includes the step carrying out reliability testing, defect inspection and Vacuum Package.
9. manufacture method according to claim 1, it is characterised in that the material of described metal level is Ag, Ni or Ti.
10. a power transistor chip, it is characterised in that described power transistor chip manufacture method according to any one of claim 1 to 9 is made.
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| CN201410784914.1A CN105789108B (en) | 2014-12-16 | 2014-12-16 | The production method and power transistor chip of power transistor chip |
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| CN201410784914.1A CN105789108B (en) | 2014-12-16 | 2014-12-16 | The production method and power transistor chip of power transistor chip |
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| CN108109901A (en) * | 2016-11-25 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of production method of semiconductor devices |
| CN112786459A (en) * | 2019-11-08 | 2021-05-11 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor device and test method thereof |
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