CN112786459B - Semiconductor device and test method thereof - Google Patents

Semiconductor device and test method thereof Download PDF

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Publication number
CN112786459B
CN112786459B CN201911088962.6A CN201911088962A CN112786459B CN 112786459 B CN112786459 B CN 112786459B CN 201911088962 A CN201911088962 A CN 201911088962A CN 112786459 B CN112786459 B CN 112786459B
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layer
metal layer
semiconductor device
protective layer
aluminum
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CN112786459A (en
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熊风涌
张俊江
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The embodiment of the invention provides a semiconductor device and a test method thereof. In the embodiment of the invention, the protective layer comprising the aluminum oxide is formed on the surface of the metal layer, so that the protective layer is thin and uniform and compact in structure, and can play a role in isolating the metal layer from impurities in the air. The defects of the semiconductor device caused by contact with impurities in the air are avoided. Meanwhile, the protective layer has the advantages of being easy to remove and not introducing impurities. Therefore, the accuracy of the subsequent detection result can be ensured.

Description

Semiconductor device and test method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a test method thereof.
Background
With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a semiconductor device and a testing method thereof to improve performance of the semiconductor device.
In a first aspect, an embodiment of the present invention provides a method for testing a semiconductor device, where the method includes:
providing a front-end chip;
forming a metal layer on the back of the front-end chip;
forming a protective layer covering the metal layer, wherein the material of the protective layer at least comprises aluminum oxide;
removing the protective layer; and
and testing the semiconductor device after the protective layer is removed.
Further, the forming of the protective layer covering the metal layer specifically includes:
depositing an aluminum layer on the metal layer;
and (4) oxidizing to form aluminum oxide.
Further, the depositing the aluminum layer on the metal layer specifically includes:
and depositing aluminum with the thickness of 100-500 angstroms on the metal layer by adopting a chemical vapor deposition process.
Further, the oxidation treatment specifically comprises:
and oxidizing at least part of the aluminum layer by adopting a thermal oxidation process to form aluminum oxide.
Further, the metal layer comprises a titanium layer, a nickel layer and a silver layer which are sequentially stacked.
Further, the removing the protection layer specifically includes:
and removing the protective layer by adopting a chemical mechanical polishing process.
Further, the removing the protection layer specifically includes:
and removing the protective layer by using weak acid solution or weak base solution.
Further, the weak acid solution is at least one of dilute hydrochloric acid, dilute sulfuric acid and dilute hydrochloric acid; the weak base solution is at least one of a sodium hydroxide solution, a potassium hydroxide solution and ammonia water.
Further, the weak acid solution or the weak base solution is an aqueous solution with the mass concentration of 1% -10%.
In a second aspect, an embodiment of the present invention provides a semiconductor device, including:
a front-end chip;
the metal layer is positioned on the back surface of the front-end chip; and
and the protective layer covers the metal layer, wherein the material of the protective layer at least comprises aluminum oxide.
Further, the thickness of the protective layer is 100-500 angstroms.
Further, the metal layer comprises a titanium layer, a nickel layer and a silver layer which are sequentially stacked.
The embodiment of the invention provides a semiconductor device and a test method thereof. In the embodiment of the invention, the protective layer comprising the aluminum oxide is formed on the surface of the metal layer, so that the protective layer is thin and uniform and compact in structure, and can play a role in isolating the metal layer from impurities in the air. The defects of the semiconductor device caused by contact with impurities in the air are avoided. Meanwhile, the protective layer has the advantages of being easy to remove and not introducing impurities. Therefore, the accuracy of the subsequent detection result can be ensured.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic view of a semiconductor device of a comparative example;
fig. 2 is a flowchart of a method of testing a semiconductor device of an embodiment of the present invention;
FIGS. 3-7 are schematic diagrams of structures formed at various steps of a method of testing a semiconductor device according to an embodiment of the present invention;
fig. 8 is a schematic structural view of a semiconductor device of an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description herein, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description herein, it is to be understood that the term "layer" is used in its broadest sense to include a film, a cap layer, or the like, and a layer may include a plurality of sub-layers.
Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and convert energy. Conventional Semiconductor devices include Metal-Oxide-Semiconductor Field-Effect transistors (MOS-FETs). The mosfet is the most basic device in semiconductor manufacturing, and is widely used in various integrated circuits, so that it is important to the development of the integrated circuits to improve the performance of the mosfet.
At present, in order to improve the electrical performance of the MOS transistor, a backskin thinning technique (BGBM) has been applied to the process of manufacturing the Metal oxide semiconductor field effect transistor and becomes a key link. The technology is to form a metal layer on the back of an MOS transistor, specifically as shown in fig. 1, the metal oxide field effect transistor in the prior art includes a front-end chip 1, and the metal layer is formed on the back of the front-end chip 1, where the front-end chip 1 includes, for example, a substrate, and a source-drain gate formed on the substrate, the metal layer includes a titanium (Ti) layer 2, a nickel (Ni) layer 3, and a silver (Ag) layer 4 deposited in sequence on the back of the front-end chip 1, and how the quality of the metal layer is directly related to the electrical performance of the obtained metal oxide field effect transistor.
However, since the metal layer formed on the back surface of the front-end chip 1 is usually exposed, the silver layer 4 on the outermost layer is contaminated, for example, by oxidation of oxygen, moisture, and other substances, and white spot defects 5 are formed on the silver layer 4, and particularly, in the case where cracks or the like occur in the metal layer, the problem of occurrence of the white spot defects 5 is particularly serious. These white point defects 5 adversely affect the test, resulting in a test that is not too critical. For example, in a wafer test (CP), for example, a voltage test, a current test, and the like are performed. The problem of defective detection often occurs, which results in low yield. How to solve the problem is of great significance in improving the yield of products.
In view of this, embodiments of the present invention provide a method for testing a semiconductor device, which realizes protection of a metal layer by introducing a protection layer, avoids generation of white point defects, and is beneficial to improving yield.
In view of this, the performance of the semiconductor device is improved. The embodiment of the invention provides a test method of a semiconductor device.
Fig. 2 is a flowchart of a method of testing a semiconductor device of an embodiment of the present invention. As shown in fig. 2, the method for testing a semiconductor device according to the embodiment of the present invention includes the steps of:
and step S100, providing a front-end chip.
And step S200, forming a metal layer on the back surface of the front-end chip.
Step S300, forming a protective layer covering the metal layer, wherein the material of the protective layer at least comprises aluminum oxide.
And step S400, removing the protective layer.
And step S500, testing the semiconductor device after the protective layer is removed.
Fig. 3-7 are schematic diagrams of structures formed at various steps of a method of testing a semiconductor device according to an embodiment of the present invention.
Referring to fig. 3, in step S100, a front-end chip 10 is provided.
Specifically, the front-end chip 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the front-end chip 10 may also include a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial-on-silicon structure, a compound front-end device layer, or an alloy front-end device layer. The compound front end device layer comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium phosphide, the alloy front end device layer comprises SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP, or combinations thereof, the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on a layer of insulating material having active and passive devices therein, the layer of insulating material protecting the active and passive devices disposed on the semiconductor layer.
Referring to fig. 4, in step S200, a metal layer 20 is formed on the back surface of the front-end chip 10.
Specifically, the metal layer 20 includes a titanium layer 21, a nickel layer 22, and a silver layer 23, which are sequentially stacked.
Specifically, a Chemical Vapor Deposition (CVD) method may be used to form the metal layer 20. For example, low Temperature Chemical Vapor Deposition (LTCVD), plasma Chemical Vapor Deposition (PCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
The metal layer formed in this step is used to assist in subsequent testing.
Referring to fig. 5 and 6, in step S300, a protective layer 30 is formed to cover the metal layer 20. Wherein, the material of the protection layer 30 at least comprises aluminum oxide.
The forming of the protective layer covering the metal layer comprises the following steps:
step S301, depositing an aluminum layer on the metal layer.
And S302, oxidizing to form aluminum oxide.
Referring to fig. 5, in step S301, an aluminum layer 30a is deposited on the metal layer 20.
Specifically, the aluminum layer 30a may be formed by chemical vapor deposition. For example, low temperature chemical vapor deposition, plasma chemical vapor deposition processes, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and fluid chemical vapor deposition processes are employed.
The aluminum layer has a thickness of 100-500 angstroms.
In an alternative implementation, a 200 angstrom thick aluminum layer 30a is deposited on the metal layer 20 using a chemical vapor deposition process.
The aluminum layer with thin thickness and uniform texture can be formed by adopting the chemical vapor deposition process.
Referring to fig. 6, in step S302, oxidation is performed to form alumina.
Specifically, at least a portion of the aluminum layer is oxidized using a thermal oxidation process to form aluminum oxide. A protective layer 30 of a material including alumina is formed.
The thermal oxidation process is to put the semiconductor device in an oxygen atmosphere and keep the temperature for a predetermined time. The temperature of the heat preservation can be 200-300 ℃.
The aluminum oxide has stable chemical properties, compact structure and good isolation effect.
In this embodiment, an aluminum layer is deposited on the surface of the metal layer, and the aluminum layer is completely or partially converted into aluminum oxide by a thermal oxidation process, so that a protective layer with a thin thickness and a uniform and dense tissue is finally formed on the surface of the metal layer. Can play a role in isolating the metal layer from impurities in the air. And further the accuracy of the subsequent detection result can be ensured.
Referring to fig. 7, in step S400, the protective layer 30 is removed.
Specifically, the protective layer 30 may be removed using a chemical mechanical polishing process. The protective layer 30 may also be removed using a weak acid solution or a weak base solution.
In an alternative implementation, the protective layer 30 is removed using a Chemical Mechanical Polishing (CMP) process. The chemical mechanical mask is a process for realizing planarization in an alternating process of chemical reaction and mechanical friction. Specifically, two processes can be divided:
the chemical process comprises the following steps: the chemical components in the slurry chemically react with the surface material of the semiconductor device to produce a substance that is relatively easy to remove. Such as converting insoluble materials into more soluble materials or softening materials with higher hardness.
Physical process: the abrasive grains in the polishing liquid and the surface material of the semiconductor device are subjected to mechanical and physical friction to remove chemical reaction products.
Specifically, the polishing liquid is composed of a chemical solution and abrasive grains, which may be Silica (SiO) 2 ) Etc., potassium hydroxide (KOH) etc. can be added to the chemical solution, and the Ph of the polishing solution is 10-13.
In another alternative implementation, the protective layer 30 is removed using a weak acid solution or a weak base solution.
The weak acid solution is at least one of dilute hydrochloric acid, dilute sulfuric acid and dilute hydrochloric acid; the weak base solution is at least one of a sodium hydroxide solution, a potassium hydroxide solution and ammonia water.
The weak acid solution or the weak base solution is an aqueous solution with the mass concentration of 1-10%.
Optionally, the protective layer 30 is removed using a weak base solution. The weak base solution is a sodium hydroxide (NaOH) aqueous solution with the mass concentration of 5%. The specific reaction principle is as follows:
Al 2 O 3 +2NaOH＝2NaAlO 2 +H 2 O
sodium aluminate (NaAlO) formed by the reaction 2 ) Dissolved in water and cleaned by water, and impurities can not be left on the semiconductor device.
In the embodiment, the formed protective layer is easy to remove, and impurities cannot be introduced, so that the accuracy of the detection result is improved.
In step S500, the semiconductor device after the protective layer 30 is removed is tested.
The test may be a wafer test, which is intended to ensure that each chip substantially meets the characteristics or design specifications of the device. Wafer testing typically includes verification of voltage, current, timing and functionality.
The equipment that wafer test used includes: the Tester (IC Tester), the Probe Card (Probe Card), the Probe station (Probe), and the Interface (Mechanical Interface) between the Tester and the Probe Card.
Specifically, in wafer testing, the metal layer is used for connecting a lead or an electrode of testing equipment. The quality of the metal layer directly affects the accuracy of the test results.
In the present embodiment, by forming the protective layer on the metal layer, the occurrence of white spot defects in the metal layer in the comparative example is avoided, and the accuracy of the test result can be ensured.
The embodiment of the invention provides a test method of a semiconductor device. In the embodiment of the invention, the protective layer comprising the aluminum oxide is formed on the surface of the metal layer, so that the protective layer is thin and uniform and compact in structure, and can play a role in isolating the metal layer from impurities in the air. The defects of the semiconductor device caused by contact with impurities in the air are avoided. Meanwhile, the protective layer has the advantages of being easy to remove and not introducing impurities. Therefore, the accuracy of the subsequent detection result can be ensured.
In another aspect, an embodiment of the present invention further provides a semiconductor device, where the semiconductor device includes: front end chip, metal level and protective layer.
Referring to fig. 8, the semiconductor device of the embodiment of the present invention includes: front chip 10', metal layer 20', and protective layer 30'.
The metal layer 20 'is located on the back side of the front-end chip 10'.
The protective layer 30 'covers the metal layer 20'. Wherein, the material of the protective layer 30' is aluminum oxide.
The protective layer 30' has a thickness of 100 angstroms to 500 angstroms.
The metal layer 20 'includes a titanium layer 21', a nickel layer 22', and a silver layer 23' stacked in this order.
In the embodiment of the invention, the protective layer with uniform and dense structure is formed by deposition on the surface of the metal layer. Can play a role in isolating the metal layer from impurities in the air. The defects of the semiconductor device caused by contact with impurities in the air are avoided.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A method of testing a semiconductor device, the method comprising:
providing a front-end chip;
forming a metal layer on the back of the front-end chip;
forming a protective layer covering the metal layer, wherein the material of the protective layer at least comprises aluminum oxide;
removing the protective layer by adopting a chemical mechanical polishing process; and
testing the semiconductor device after the protective layer is removed;
the forming of the protective layer covering the metal layer specifically includes:
depositing an aluminum layer on the metal layer;
oxidizing to form aluminum oxide;
and oxidizing at least part of the aluminum layer by adopting a thermal oxidation process to form aluminum oxide, wherein the forming material comprises a protective layer of the aluminum oxide.
2. The method for testing a semiconductor device according to claim 1, wherein the depositing the aluminum layer on the metal layer is specifically:
and depositing aluminum with the thickness of 100-500 angstroms on the metal layer by adopting a chemical vapor deposition process.
3. The method for testing a semiconductor device according to claim 1, wherein the metal layer comprises a titanium layer, a nickel layer and a silver layer which are stacked in this order.
4. A semiconductor device, characterized in that the semiconductor device comprises:
a front-end chip;
the metal layer is positioned on the back surface of the front-end chip; and
the protective layer covers the metal layer, wherein the material of the protective layer at least comprises aluminum oxide, and the aluminum oxide is formed by depositing an aluminum layer on the metal layer and then oxidizing the aluminum layer;
and removing the protective layer of the metal layer by adopting a chemical mechanical polishing process.
5. The semiconductor device according to claim 4, wherein a thickness of the protective layer is 100 to 500 angstroms.
6. The semiconductor device according to claim 4, wherein the metal layer comprises a titanium layer, a nickel layer and a silver layer which are sequentially stacked.
CN201911088962.6A 2019-11-08 2019-11-08 Semiconductor device and test method thereof Active CN112786459B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105789108A (en) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 Power transistor chip manufacturing method and power transistor chip
CN106997900A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure, its forming method and method of testing
CN108109901A (en) * 2016-11-25 2018-06-01 中芯国际集成电路制造(上海)有限公司 A kind of production method of semiconductor devices

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140110838A1 (en) * 2012-10-22 2014-04-24 Infineon Technologies Ag Semiconductor devices and processing methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105789108A (en) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 Power transistor chip manufacturing method and power transistor chip
CN106997900A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure, its forming method and method of testing
CN108109901A (en) * 2016-11-25 2018-06-01 中芯国际集成电路制造(上海)有限公司 A kind of production method of semiconductor devices

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