CN105789034A - Preparing method of top electrode of bypass diode - Google Patents
Preparing method of top electrode of bypass diode Download PDFInfo
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- CN105789034A CN105789034A CN201410798461.8A CN201410798461A CN105789034A CN 105789034 A CN105789034 A CN 105789034A CN 201410798461 A CN201410798461 A CN 201410798461A CN 105789034 A CN105789034 A CN 105789034A
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- electrode
- bypass diode
- top electrode
- evaporation
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Abstract
The invention relates to a preparing method of the top electrode of a bypass diode, and belongs to the technical field of a physical power supply. The preparing method of the top electrode of the bypass diode is characterized in that through adoption of a photolithography, the top electrode of the bypass diode is patterned through the photolithography, and then the top electrode is evaporated. The preparation process comprises following technological steps of (1), coating: adopting a substrate silicon wafer to which boron and phosphorus diffusion is carried out, and coating BP218 photoresist on a spin coater; (2), baking: baking for 19-22 minutes under a temperature condition of 88-93 degrees centigrade; (3), exposure: electrifying a lithography machine, putting a photomask away, and exposing for 16-20 seconds; (4), development: putting the silicon wafer in a developing solution for development; (5) top electrode evaporation: carrying out electrode evaporation on a vacuum coating machine, wherein a titanium layer, a palladium layer and a silver layer are evaporated on the top electrode; (6) photoresist removal: soaking a battery piece in an acetone solution; and removing the photoresist on the surface of the battery piece. The method has the advantages of simple technology, low technological difficulty, convenient processing and greatly reducing of the reverse leakage current index product of the top electrode.
Description
Technical field
The invention belongs to physical power source technical field, particularly relate to the preparation method of electrode on a kind of bypass diode.
Background technology
Currently for solar battery array, bypass diode is an extremely important part.Its principle is, when certain solar cell occurs that hot spot effect can not generate electricity, play bypass effect, allow electric current produced by other normal battery flow out from bypass diode, make solar power system can continue to generating, will not because of certain a piece of fail battery, and produce the situation that circuit is obstructed, when cell piece normal operation, bypass diode will reversely end, and circuit does not produce large effect.
For current level, existing bypass diode product, reverse leakage current is higher, all more than tens milliamperes, and still finds no same or like product；There is similar diode product www.azurspace.com website, its reverse leakage current reaches the level of 0.1uA～1.0uA (surveying with under condition), and its shortcoming is to there is reverse leakage current to meet the technical problem such as demand of the solar cell for space use less reverse leakage current of bypass diode requirement (nA level) index.
Summary of the invention
The present invention solves that the technical problem existed in known technology provides the preparation method of electrode on a kind of bypass diode.
The invention solves the technical problem that the reverse leakage current of background technology existence is big, it is provided that be capable of the bypass diode upper electrode arrangement with low reverse current leakage, it is possible to meet the demand of space bypass diode.
It is an object of the invention to provide one and have technique simply, manufacturing process difficulty is low, easy to process, and on product, electrode can reduce the preparation method of electrode on the bypass diode of the features such as reverse leakage current index.
On bypass diode of the present invention, the preparation method of electrode is adopted the technical scheme that:
The preparation method of electrode on a kind of bypass diode, is characterized in: on bypass diode, electrode adopts photoetching technique, and the aurora that will power on carve figure, then the upper electrode of evaporation, and preparation process comprises the following steps that:
(1) gluing
Adopting the silicon substrate having finished boron, phosphorus diffusion, be placed on sol evenning machine by silicon chip, be coated with BP218 photoresist, spin coating time is 15s～20s；
(2) drying glue
Under 88-93 DEG C of condition, dry 19-22min；
(3) exposure
Connect litho machine, intensity monitor light intensity 15mw/cm2～20mw/cm2, to put reticle well, make reticle figure in wafer-supporting platform center, reticle chromium is facing to silicon chip spin coating face, after Exposing Lamp stabilized intensity, is loaded by silicon chip on the wafer-supporting platform of litho machine, exposes 16s～20s；
(4) development
Being loaded in silicon wafer carrier by silicon chip after exposure, put in developer solution, developing time is 30s～40s；
(5) upper electrode evaporation
Being placed on mould by silicon chip, phosphorus extended surface down, loads in vacuum chamber, titanium, palladium, silverskin material is respectively put in corresponding crucible, vacuum coating equipment carries out electrode evaporation, upper electrode evaporation titanium layer, palladium layers and silver layer；
(6) remove photoresist
Cell piece is immersed in acetone soln, the photoresist on its surface is removed, completes electrode fabrication.
On bypass diode of the present invention, the preparation method of electrode may also take on following technical scheme:
The preparation method of electrode on described bypass diode, is characterized in: the design electrode pattern edge of reticle and silicon chip edge distance are 600 μm.
The preparation method of electrode on described bypass diode, is characterized in: the titanium film layer thickness of upper electrode evaporation isPalladium thicknesses of layers isSilver film gross thickness is
The preparation method of electrode on described bypass diode, is characterized in: during upper electrode evaporation, initial vacuum is not less than 3 × 10-4Pa。
The preparation method of electrode on described bypass diode, is characterized in: when removing photoresist, and it is 25-40min that cell piece is immersed in the acetone soln time.
The present invention has the advantage that and has the benefit effect that
The technical scheme that on bypass diode, the preparation method of electrode is brand-new owing to have employed the present invention, compared with prior art, the present invention is by adopting photoetching technique, and the aurora that will power on carve figure, then the upper electrode of evaporation.In order to reduce edge current leakage, in structural design, have employed the structural design of electrode local complexity, purpose is the connection having blocked upper electrode by silicon chip edge with lower surface electrode, namely the probability of physics short circuit between upper/lower electrode is greatly reduced, the design of this upper electrode arrangement and use so that reverse leakage current index reduces substantially, and its effect is notable.
Table 1 reverse leakage correction data
Accompanying drawing explanation
Fig. 1 is space bypass diode cross-sectional view；
Wherein, the upper electrode of 1-(Ti-Pd-Ag), the silica-based district of 2-(p-type), 3-bottom electrode (Al-Ti-Pd-Ag).
Fig. 2 is photoetching figure design structural representation；
In figure, A is a powering up border, pole, and B is silicon chip substrate border；
Fig. 3 is electrode plan structure structural representation on bypass diode.
Detailed description of the invention
For the summary of the invention of the present invention, feature and effect can be further appreciated that, hereby enumerate following example, and be described with reference to the accompanying drawings as follows:
Accompanying drawings 1, Fig. 2 and Fig. 3.
Embodiment 1
The preparation method of electrode on a kind of bypass diode, adopts photoetching technique, and the aurora that will power on carve figure, then the upper electrode of evaporation, and concrete preparation process comprises the following steps that:
Adopting the silicon substrate having finished boron, phosphorus diffusion, including last bottom electrode technique and scribing process thereof, its concrete technology, with the processing technology of general diode, repeats no more here；First it is photoetching figure design (see Fig. 2), then according to following processing technology carries out the making of the technique of upper electrode.
1. gluing:
Being placed on sol evenning machine by silicon chip, start hand coatings BP218 photoresist, by sol evenning machine speed setting at 3000rpm, spin coating time is 15s～20s；
2. drying glue:
Dry 20min for 90 DEG C；
3. exposure:
Connecting litho machine, intensity monitor light intensity should at 15mw/cm2～20mw/cm2Put reticle well, reticle graphic designs makes graph edge from 600 μm of diode edge (see Fig. 2), make reticle figure in wafer-supporting platform center, reticle chromium is facing to silicon chip spin coating face, after Exposing Lamp stabilized intensity, is loaded by silicon chip on the wafer-supporting platform of litho machine, set time of exposure as 16s～20s, then start exposure；
4. development:
Being loaded in silicon wafer carrier by silicon chip after exposure, put in developer solution, developing time is 30s～40s.
5. go up electrode evaporation:
Being placed on mould by silicon chip, phosphorus extended surface down, loads in vacuum chamber, and the appropriate titanium cleaning handled well, palladium, silverskin material are respectively put in corresponding crucible, start the control panel of high vacuum coating unit computer, perform vacuum pumping, and system starts evacuation.Recall electrode evaporation process, check that each parameter is arranged.Titanium film layer thickness is set asRate setting isControlPalladium thicknesses of layers is set asRate setting isControlSilver film gross thickness is set asRate setting isControl automatically to be deposited with in startup program.The initial vacuum of process is not less than 3 × 10-4Pa, upper electrode has been deposited with.
6. remove photoresist:
It is immersed in acetone soln by cell piece 30min, the photoresist on its surface is removed.
After having removed photoresist, upper electrode fabrication can complete.Being above each process sequence and parameter, its process sequence then can not become, and technological parameter can with fitness of environment adjustment.
7. leakage tests
Electric performance test after bottom electrode, scribing process, adds under the reverse voltage condition of 4V, and its reverse leakage current is down to 0.0002 μ A.
The present embodiment is in order to reduce edge current leakage, in structural design, have employed the structural design of electrode local complexity, purpose is the connection having blocked upper electrode by silicon chip edge with lower surface electrode, namely the probability of physics short circuit between upper/lower electrode is greatly reduced, the design of this upper electrode arrangement and use so that reverse leakage current index reduces substantially, and its good effect is notable.
Claims (5)
1. a preparation method for electrode on bypass diode, is characterized in that: on bypass diode, electrode adopts photoetching technique, and the aurora that will power on carve figure, then the upper electrode of evaporation, and preparation process comprises the following steps that:
(1) gluing
Adopting the silicon substrate having finished boron, phosphorus diffusion, be placed on sol evenning machine by silicon chip, be coated with BP218 photoresist, spin coating time is 15s～20s；
(2) drying glue
Under 88-93 DEG C of condition, dry 19-22min；
(4) exposure
Connect litho machine, intensity monitor light intensity 15mw/cm2～20mw/cm2, to put reticle well, make reticle figure in wafer-supporting platform center, reticle chromium is facing to silicon chip spin coating face, after Exposing Lamp stabilized intensity, is loaded by silicon chip on the wafer-supporting platform of litho machine, exposes 16s～20s；
(5) development
Being loaded in silicon wafer carrier by silicon chip after exposure, put in developer solution, developing time is 30s～40s；
(6) upper electrode evaporation
Being placed on mould by silicon chip, phosphorus extended surface down, loads in vacuum chamber, titanium, palladium, silverskin material is respectively put in corresponding crucible, vacuum coating equipment carries out electrode evaporation, upper electrode evaporation titanium layer, palladium layers and silver layer；
(7) remove photoresist
Cell piece is immersed in acetone soln, the photoresist on its surface is removed, completes electrode fabrication.
2. the preparation method of electrode on bypass diode according to claim 1, is characterized in that: the design electrode pattern edge of reticle and silicon chip edge distance are 600 μm.
3. the preparation method of electrode on bypass diode according to claim 1 and 2, is characterized in that: the titanium film layer thickness of upper electrode evaporation isPalladium thicknesses of layers isSilver film gross thickness is
4. the preparation method of electrode on bypass diode according to claim 3, is characterized in that: during upper electrode evaporation, initial vacuum is not less than 3 × 10-4Pa。
5. the preparation method of electrode on bypass diode according to claim 1, is characterized in that: when removing photoresist, and it is 25-40min that cell piece is immersed in the acetone soln time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410798461.8A CN105789034A (en) | 2014-12-19 | 2014-12-19 | Preparing method of top electrode of bypass diode |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410798461.8A CN105789034A (en) | 2014-12-19 | 2014-12-19 | Preparing method of top electrode of bypass diode |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106324566A (en) * | 2016-08-01 | 2017-01-11 | 安徽贝莱电子科技有限公司 | Radar sensor chip manufacturing technology |
| CN108807167B (en) * | 2018-06-05 | 2020-11-10 | 深圳市信展通电子有限公司 | Production and manufacturing method of diode electrode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752302A (en) * | 2008-12-04 | 2010-06-23 | 上海空间电源研究所 | Manufacturing method of new round-angle integrated bypass diode for high-efficiency solar batteries |
| US20100326492A1 (en) * | 2009-06-30 | 2010-12-30 | Solarmation, Inc. | Photovoltaic Cell Support Structure Assembly |
| CN203434160U (en) * | 2013-07-22 | 2014-02-12 | 天津恒电空间电源有限公司 | Large-area silicon bypass diode for solar cell array |
-
2014
- 2014-12-19 CN CN201410798461.8A patent/CN105789034A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752302A (en) * | 2008-12-04 | 2010-06-23 | 上海空间电源研究所 | Manufacturing method of new round-angle integrated bypass diode for high-efficiency solar batteries |
| US20100326492A1 (en) * | 2009-06-30 | 2010-12-30 | Solarmation, Inc. | Photovoltaic Cell Support Structure Assembly |
| CN203434160U (en) * | 2013-07-22 | 2014-02-12 | 天津恒电空间电源有限公司 | Large-area silicon bypass diode for solar cell array |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106324566A (en) * | 2016-08-01 | 2017-01-11 | 安徽贝莱电子科技有限公司 | Radar sensor chip manufacturing technology |
| CN108807167B (en) * | 2018-06-05 | 2020-11-10 | 深圳市信展通电子有限公司 | Production and manufacturing method of diode electrode |
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