CN105763047B - A kind of all-wave inductive current sample circuit - Google Patents
A kind of all-wave inductive current sample circuit Download PDFInfo
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- CN105763047B CN105763047B CN201610131510.1A CN201610131510A CN105763047B CN 105763047 B CN105763047 B CN 105763047B CN 201610131510 A CN201610131510 A CN 201610131510A CN 105763047 B CN105763047 B CN 105763047B
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- 230000001939 inductive effect Effects 0.000 title claims abstract description 37
- 238000005070 sampling Methods 0.000 claims abstract description 75
- 230000010354 integration Effects 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 230000005611 electricity Effects 0.000 claims description 18
- 239000002131 composite material Substances 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000007600 charging Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 241001168730 Simo Species 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- HODRFAVLXIFVTR-RKDXNWHRSA-N tevenel Chemical compound NS(=O)(=O)C1=CC=C([C@@H](O)[C@@H](CO)NC(=O)C(Cl)Cl)C=C1 HODRFAVLXIFVTR-RKDXNWHRSA-N 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a kind of all-wave inductive current sample circuits, turn electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit including system power grade circuit, ratio metal-oxide-semiconductor current sampling circuit, voltage, first output end of the system power grade circuit is connected to the first input end of the correction of sampling direct current and sample integration circuit by ratio metal-oxide-semiconductor current sampling circuit, and the second output terminal of the system power grade circuit is connected to the second input terminal of the correction of sampling direct current and sample integration circuit by voltage turns electric current and electric current summing circuit.The present invention turns electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit by system power grade circuit, ratio metal-oxide-semiconductor current sampling circuit, voltage can realize that accurate all-wave inductive current samples, and it is continuous to obtain sampled signal, effectively prevents the problem of burr occur.It the composite can be widely applied in electronic circuit field.
Description
Technical field
The present invention relates to electronic circuit technology field more particularly to a kind of all-wave inductive current sample circuits.
Background technology
Single inductance multi output (Single-Inductor Multiple-Output, SIMO) DC-DC converter is a kind of incites somebody to action
The novel DC-DC converter structure of inductance time-sharing multiplex, system only need an inductance, provide for the independent output of multichannel.
Therefore the number for greatly reducing piece external inductance, reduces the volume of converter, to reduce cost.It is proposed in recent years from
Dynamic buck-boost type list inductance multi output DC-DC converter is even more to have expanded the application range of such converter.
The power stage circuit of automatic lifting type list inductance multi output DC-DC converter is as shown in Figure 1, the power stage circuit packet
Input stage switch group and output stage switch group are included, wherein input stage switch group includes a PMOS tube MipWith a NMOS tube Min,
Output stage switch group includes a NMOS tube MonWith n PMOS tube Mop1~Mopn.When converter works, signal G is controlledo1~Gon
Control output stage switch group sequentially turns on, and will not there is a situation where simultaneously turn on.
The control method of single inductance multi output DC-DC converter the most widely used at present is sequentially to energize control methods
(Ordered Power Distributive Control, OPDC), i.e., within a cycle, once fill inductance
Then electricity discharges according to certain sequence to each output channel.In order to realize current-mode control, overcurrent protection and detection not
Continuous conduction mode (Discontinuous Conduction Mode, DCM), we must be accurate within the entire work period
Detect inductive current.Current more commonly used, the higher inductive current sample circuit of sampling precision is ratio metal-oxide-semiconductor inductive current
Sample circuit.
Shown in Fig. 2 is half-wave ratio metal-oxide-semiconductor inductive current sample circuit, wherein power switch tube MipBreadth length ratio be to adopt
Sample pipe MpsenK times of breadth length ratio.In power switch tube Mip(i.e. power switch tube M is connectedinCut-off) when, switch S1It disconnects, opens
Close S2It is closed, VX1It is connected to the inverting input of amplifier Amp1, amplifier Amp1 and adjustment pipe MnSo that the in-phase input end of amplifier
It is equal with anti-phase input terminal potential, there is power switch tube M at this timeipWith sampling pipe MpsenGrid, source electrode, drain potential all divide
It is inequal, and power switch tube MipBreadth length ratio be sampling pipe MpsenK times of breadth length ratio, therefore flow through sampling pipe MpsenElectricity
Stream is power switch tube MipThe 1/K of electric current (being equal to inductive current during this period), then passes through sampling resistor R againsenIt will sampling
Electric current is converted into voltage Vsen.Relationship between them isIn power switch tube Min(i.e. power switch is connected
Pipe MipCut-off) when, switch S2It disconnects, switch S1It is closed, VinIt is connected to the inverting input of amplifier Amp1, therefore the output of amplifier
It is pulled low, adjustment pipe MnCut-off, VsenIt is 0, inductive current information can not be detected at this time, therefore sample for half-wave inductive current.This
The advantages of kind ratio metal-oxide-semiconductor current sampling circuit is that circuit structure is simple, and sampling precision is high, and power consumption is relatively small, can be operated in
In the switching frequency circuit of 10MHz or more；The disadvantage is that can only half-wave inductive current sampling, automatic lifting die mould list can not be applied to
In inductance multi output DC-DC converter.
Shown in Fig. 3 is all-wave ratio metal-oxide-semiconductor inductive current sample circuit, and the essence of the circuit is to sample two half-waves
Circuit is combined, and two half-wave sample circuits separately detect power switch tube MipDuring conducting and power switch tube MinThe conducting phase
Between inductive current, the electric current detected is then passed through into the same sampling resistor RsenSample rate current is converted into voltage Vsen。
Although what this method obtained is all-wave inductive current information, many disadvantages are still had.First, due in power switch
Pipe MipConducting and power switch tube MinThere are dead time and switch S between conducting1~S4Action, leads to the electric current detected
There are many burrs in switching for waveform, as shown in figure 4, this can cause system false triggering.Second, since there are circuit mismatches
The problem of, causing the current waveform detected that can mutate in switching, (as shown in the dotted ellipse in Fig. 4, sampling is electric
Press VsenMutate), and actually inductive current is impossible to mutate, this mutation may cause system not
Stablize.
Invention content
In order to solve the above-mentioned technical problem, the object of the present invention is to provide a kind of energy continuous samplings, and sampling precision is higher
A kind of all-wave inductive current sample circuit.
The technical solution used in the present invention is：
A kind of all-wave inductive current sample circuit, including system power grade circuit, ratio metal-oxide-semiconductor current sampling circuit, electricity
Pressure turns electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit, the first of the system power grade circuit are defeated
Outlet is connected to the correction of sampling direct current and the first input of sample integration circuit by ratio metal-oxide-semiconductor current sampling circuit
The second output terminal at end, the system power grade circuit is connected to sampling directly by voltage turns electric current and electric current summing circuit
Second input terminal of stream correction and sample integration circuit.
As a further improvement on the present invention, the system power grade circuit includes the first PMOS tube, the first NMOS tube, the
Two NMOS tubes and inductance, the source electrode of first PMOS tube input terminal and voltage with ratio metal-oxide-semiconductor current sampling circuit respectively
Input terminal connect, first PMOS tube drain electrode respectively with the second input terminal of ratio metal-oxide-semiconductor current sampling circuit, first
The input terminal that the drain electrode of NMOS tube turns electric current and electric current summing circuit with voltage connects, and the drain electrode of first PMOS tube passes through electricity
Sense is connected to the drain electrode of the second NMOS tube, and drain electrode and the voltage of second NMOS tube turn the third of electric current and electric current summing circuit
Input terminal is connected.
As a further improvement on the present invention, it includes the second PMOS tube, that the voltage, which turns electric current and electric current summing circuit,
Three PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube,
One resistance, second resistance, the first operational amplifier and second operational amplifier, source electrode, the 3rd PMOS of second PMOS tube
The source electrode of the source electrode of pipe, the source electrode of the 4th PMOS tube and the 5th PMOS tube is connected to power end, the grid of second PMOS tube
Pole is connect with the grid of the drain electrode of the second PMOS tube, the drain electrode of third NMOS tube and third PMOS tube respectively, the 5th PMOS
The grid of pipe is connect with the drain electrode of the 5th PMOS tube, the drain electrode of the 4th NMOS tube and the grid of the 4th PMOS tube respectively, and described
The drain electrode of three PMOS tube is corrected respectively with sampling direct current and the drain electrode of the second input terminal and the 5th NMOS tube of sample integration circuit
Connection, the 4th PMOS tube drain electrode respectively with the drain electrode of the 6th NMOS tube, the grid and the 5th NMOS tube of the 6th NMOS tube
Grid connection, the grid of the third NMOS tube connect with the output end of the first operational amplifier, the third NMOS tube
Source electrode is connect with the inverting input of the first end of first resistor and first arithmetic device respectively, the first arithmetic device it is same mutually defeated
Entering end to connect with the drain electrode of the first PMOS tube, the grid of the 4th NMOS tube and the output end of second operational amplifier connect,
The source electrode of 4th NMOS tube is connect with the inverting input of the first end of second resistance and second arithmetic device respectively, and described
The in-phase input end of two arithmetic units is connect with the drain electrode of the second NMOS tube.
As a further improvement on the present invention, the sampling direct current correction and sample integration circuit include buffer, switch
With sample integration capacitance, the output end of the ratio metal-oxide-semiconductor current sampling circuit and the input terminal of buffer connect, the buffering
The output end of device is connected to the first end of sample integration capacitance by switch, and the first end of the sample integration capacitance is connected to the
The drain electrode of three PMOS tube.
As a further improvement on the present invention, the sampling direct current correction and sample integration circuit include third operation amplifier
Device, sample integration capacitance, the first capacitance, the second capacitance, 3rd resistor, the 4th resistance, the 6th PMOS tube, the 7th PMOS tube,
Eight PMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth NMOS tube and the 11st NMOS tube, the ratio
The output end of metal-oxide-semiconductor current sampling circuit is connected to the inverting input of third operational amplifier, the third operational amplifier
Output end connect respectively with the grid of the first end of the first capacitance and the 7th NMOS tube, the output of the third operational amplifier
End is connected to the first end of the second capacitance by 3rd resistor, the source electrode of the 6th PMOS tube, the source electrode of the 7th PMOS tube and
The source electrode of 8th PMOS tube is connected to power end, the grid of the 6th PMOS tube respectively with the drain electrode of the 6th PMOS tube and
The drain electrodes of seven NMOS tubes connects, the grid of the 7th PMOS tube respectively with the drain electrode of the 7th PMOS tube, the grid of the 8th PMOS tube
Pole is connected with the drain electrode of the 8th NMOS tube, the source electrode of the 7th NMOS tube first end and the 9th with the 4th resistance respectively
The drain electrode of NMOS tube connects, the source electrode drain electrode with the second end and the tenth NMOS tube of the 4th resistance respectively of the 8th NMOS tube
Connection, grid, the grid of the tenth NMOS tube and the grid of the 11st NMOS tube of the 9th NMOS tube are connected to biased electrical
Pressure side, the in-phase input end of the third operational amplifier respectively with the drain electrode of the 8th PMOS tube, the drain electrode of the 11st NMOS tube,
The first end of sample integration capacitance is connected with the drain electrode of third PMOS tube.
The beneficial effects of the invention are as follows：
A kind of all-wave inductive current sample circuit of the present invention passes through system power grade circuit, ratio metal-oxide-semiconductor current sample electricity
Road, voltage, which turn electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit, can realize accurate all-wave inductance electricity
Stream sampling, and it is continuous to obtain sampled signal, effectively prevents the problem of burr occur, can be used for single inductance multi-output dc-
Accurately controlling in DC converters and overcurrent protection, discontinuous inductive current mode detection etc..
Description of the drawings
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is a kind of power stage circuit figure of automatic lifting type list inductance multi output DC-DC converter；
Fig. 2 is half-wave ratio metal-oxide-semiconductor inductive current sample circuit schematic diagram；
Fig. 3 is all-wave ratio metal-oxide-semiconductor inductive current sample circuit schematic diagram；
Fig. 4 is the typical sample waveform figure of all-wave ratio metal-oxide-semiconductor inductive current sample circuit；
Fig. 5 is a kind of functional-block diagram of all-wave inductive current sample circuit of the present invention；
Fig. 6 is a kind of circuit diagram of all-wave inductive current sampling circuit embodiment 1 of the invention；
Fig. 7 is a kind of circuit diagram of all-wave inductive current sampling circuit embodiment 2 of the invention.
Specific implementation mode
With reference to figure 5, a kind of all-wave inductive current sample circuit of the present invention, including system power grade circuit, ratio metal-oxide-semiconductor electricity
Stream sample circuit, voltage turn electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit, the system power
First output end of grade circuit is connected to the correction of sampling direct current and sample integration electricity by ratio metal-oxide-semiconductor current sampling circuit
The first input end on road, the second output terminal of the system power grade circuit is by voltage turns electric current and electric current summing circuit
It is connected to the second input terminal of the correction of sampling direct current and sample integration circuit.
It is further used as preferred embodiment, the system power grade circuit includes the first PMOS tube M1, the first NMOS
The source electrode of pipe N1, the second NMOS tube N2 and inductance L, the first PMOS tube M1 respectively with ratio metal-oxide-semiconductor current sampling circuit
Input terminal is connected with voltage input end, the drain electrode of the first PMOS tube M1 respectively with ratio metal-oxide-semiconductor current sampling circuit the
Two input terminals, the first NMOS tube N1 drain electrode and voltage turn electric current and the input terminal of electric current summing circuit connects, described first
The drain electrode of PMOS tube M1 is connected to the drain electrode of the second NMOS tube N2, the drain electrode of the second NMOS tube N2 and voltage by inductance L
The third input terminal for turning electric current and electric current summing circuit is connected.
In the embodiment of the present invention, the voltage turns electric current and electric current summing circuit includes two Voltage-current conversion circuits and one
A electric current summing circuit.Two Voltage-current conversion circuits are respectively by the voltage V at the both ends inductance LX1And VX2It is converted into electric current, then
Two-way electric current is subtracted each other, the electric current after subtracting each other charges for sampling capacitance, and the voltage at sampling capacitance both ends is to sample letter
Number.Due to the influence of the D.C. resistance DCR of non-ideal factor such as inductance L, cause the DC values of sampled signal to have offset, therefore needs
A sampling direct current correcting circuit is wanted to carry out direct current correction.In correction course, need with traditional ratio metal-oxide-semiconductor sampling side
Method obtains a reference signal.
In the ideal case, i.e., the influence for not considering the D.C. resistance DCR of inductance L, according to electricity
L electric currents are felt with inductance L both end voltages relationship it is recognised that a certain moment inductance L size of current is：Assuming that the gain of two Voltage-current conversion circuits is gm,
So voltage V at the both ends inductance LX1(τ) and VX2(τ) is respectively g after being converted into electric currentm*VX1(τ) and gm*VX2(τ), two electricity
Stream subtract each other after for sampling capacitance charge, according to the relationship between the voltage and capacitance charging current at capacitance both ends it is recognised that
The voltage swing at a certain moment capacitance both ends is：Thus
It obtains：OrAs can be seen that the voltage u at a certain moment capacitance both endsC(t) and electricity is flowed through
Feel the electric current i of LL(t) it is proportional, and proportionality coefficient gmL/C is a fixed value, it can be said that the electricity at capacitance both ends
Press uC(t) be inductance L electric current iL(t) sampled value.
But in a practical situation, there are D.C. resistance DCR by inductance L, therefore will have a direct current voltage error uDC
(t)=iL(t) * DCR, in this case, a certain moment inductance L size of current is：
And the voltage swing at capacitance both ends remains as：Thus it obtains：Since the inductance L electric currents in DC-DC cannot be flow backwards, i.e. iL, therefore u (t) >=0DC(t)≥
0.It can be seen that the voltage u at a certain moment capacitance both endsC(t) with flow through the electric current i of inductance LL(t) no longer it is proportional
, but there are an errorsAnd this error over time can be increasing, and capacitance is caused to be adopted
There are a DC deviations for the inductance L current values that sample obtains, it is therefore desirable to sample direct current correction and sample integration circuit to carry out
Direct current corrects.In correction course, need to obtain a reference signal with traditional ratio metal-oxide-semiconductor method of sampling.
With reference to figure 6, in the embodiment of the present invention 1, the voltage turn electric current and electric current summing circuit include the second PMOS tube M2,
Third PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS tube M5, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube
N5, the 6th NMOS tube N6, first resistor R1, second resistance R2, the first operational amplifier A mp1 and second operational amplifier Amp2,
The source electrode of the second PMOS tube M2, the source electrode of third PMOS tube M3, the source electrode of the 4th PMOS tube M4 and the 5th PMOS tube M5
Source electrode is connected to power end, the grid of the second PMOS tube M2 respectively with the drain electrode of the second PMOS tube M2, third NMOS tube
The drain electrode of N3 is connected with the grid of third PMOS tube M3, the grid leakage with the 5th PMOS tube M5 respectively of the 5th PMOS tube M5
The drain electrode of pole, the 4th NMOS tube N4 is connected with the grid of the 4th PMOS tube M4, the drain electrode of the third PMOS tube M3 respectively with adopt
Sample direct current corrects and the drain electrode of the input terminal of sample integration circuit and the 5th NMOS tube N5 connection, the leakage of the 4th PMOS tube M4
Pole is connect with the drain electrode of the 6th NMOS tube N6, the grid of the 6th NMOS tube N6 and the grid of the 5th NMOS tube N5 respectively, and described
The grid of three NMOS tube N3 is connect with the output end of the first operational amplifier A mp1, the source electrode of the third NMOS tube N3 respectively with
The first end of first resistor R1 is connected with the inverting input of first arithmetic device, the in-phase input end of the first arithmetic device and
The drain electrode of one PMOS tube M1 connects, and the grid of the 4th NMOS tube N4 is connect with the output end of second operational amplifier Amp2,
The source electrode of the 4th NMOS tube N4 is connect with the inverting input of the first end of second resistance R2 and second arithmetic device respectively, institute
The in-phase input end for stating second arithmetic device is connect with the drain electrode of the second NMOS tube N2.The sampling direct current correction and sample integration electricity
Road includes buffer Buffer, switch S and sample integration capacitance C, the output end of the ratio metal-oxide-semiconductor current sampling circuit with it is slow
The input terminal connection of device Buffer is rushed, the output end of the buffer Buffer is connected to sample integration capacitance C's by switch S
The first end of first end, the sample integration capacitance C is connected to the drain electrode of third PMOS tube M3.
Wherein, the system power grade circuit is discussed in detail referring to Fig. 1.The ratio metal-oxide-semiconductor current sampling circuit was both
The half-wave ratio metal-oxide-semiconductor inductive current sample circuit in Fig. 2 may be used, the all-wave ratio metal-oxide-semiconductor electricity in Fig. 3 can also be used
Inducing current sample circuit is discussed in detail as circuit inside, referring to background of technology.Voltage turns electric current and electric current summing circuit
In the Voltage-current conversion circuit 1 that is made of the first operational amplifier A mp1, third NMOS tube N3, first resistor R1, by the second fortune
The Voltage-current conversion circuit 2 for calculating amplifier Amp2, the 4th NMOS tube N4, second resistance R2 compositions, by the second PMOS tube M2 and the
Three pairs of electricity of three PMOS tube M3, the 4th PMOS tube M4 and the 5th PMOS tube M5, the 5th NMOS tube N5 and the 6th NMOS tube N6 compositions
Flow mirror.Voltage-current conversion circuit 1 is by VX1The voltage at place is converted into electric current, then passes through the second PMOS tube M2 and third PMOS tube M3
The current mirror of composition replicates current mirror, then to VsenseNode pours into electric current；Voltage-current conversion circuit 2 is by VX2The electricity at place
Pressure is converted into electric current, then passes through the 5th PMOS tube M5 and the 4th PMOS tube M4, the 5th NMOS tube N5 and the 6th NMOS tube N6 groups
At current mirror current mirror is replicated, then from VsenseNode pulls out electric current, to realize current subtraction at the node,
Electric current after subtracting each other is from VsenseNode flows out, and is the C chargings of sample integration capacitance.It is finally sampling direct current correcting circuit and sampling
Integrating capacitor C modules, the module include an a buffer Buffer and switch S and sample integration capacitance C.The buffering
The input of device Buffer is connected to the V of ratio metal-oxide-semiconductor current sampling circuitsenOutput is stablized in ratio metal-oxide-semiconductor current sampling circuit
When work, V is exportedsenIt is more accurate, therefore switch S can be closed a bit of time at this moment, forces sample integration
The voltage of capacitance C is equal to the output V of ratio metal-oxide-semiconductor current sampling circuitsen, reset correction to realize.It analyzes front
Go out, error signal size isIf switch S is closed one within each work period of SIMO DC-DC
Short time, realize it is primary reset, then since the error accumulation time is short, the error very little generated, above sampling capacitance
Obtained sampled voltage can accurately reflect inductive current information.
With reference to figure 7, in the embodiment of the present invention 2, the voltage turn electric current and electric current summing circuit include the second PMOS tube M2,
Third PMOS tube M3, the 4th PMOS tube M4, the 5th PMOS tube M5, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube
N5, the 6th NMOS tube N6, first resistor R1, second resistance R2, the first operational amplifier A mp1 and second operational amplifier Amp2,
The source electrode of the second PMOS tube M2, the source electrode of third PMOS tube M3, the source electrode of the 4th PMOS tube M4 and the 5th PMOS tube M5
Source electrode is connected to power end, the grid of the second PMOS tube M2 respectively with the drain electrode of the second PMOS tube M2, third NMOS tube
The drain electrode of N3 is connected with the grid of third PMOS tube M3, the grid leakage with the 5th PMOS tube M5 respectively of the 5th PMOS tube M5
The drain electrode of pole, the 4th NMOS tube N4 is connected with the grid of the 4th PMOS tube M4, the drain electrode of the third PMOS tube M3 respectively with adopt
Sample direct current corrects and the drain electrode of the input terminal of sample integration circuit and the 5th NMOS tube N5 connection, the leakage of the 4th PMOS tube M4
Pole is connect with the drain electrode of the 6th NMOS tube N6, the grid of the 6th NMOS tube N6 and the grid of the 5th NMOS tube N5 respectively, and described
The grid of three NMOS tube N3 is connect with the output end of the first operational amplifier A mp1, the source electrode of the third NMOS tube N3 respectively with
The first end of first resistor R1 is connected with the inverting input of first arithmetic device, the in-phase input end of the first arithmetic device and
The drain electrode of one PMOS tube M1 connects, and the grid of the 4th NMOS tube N4 is connect with the output end of second operational amplifier Amp2,
The source electrode of the 4th NMOS tube N4 is connect with the inverting input of the first end of second resistance R2 and second arithmetic device respectively, institute
The in-phase input end for stating second arithmetic device is connect with the drain electrode of the second NMOS tube N2.The sampling direct current correction and sample integration electricity
Road includes third operational amplifier A mp3, sample integration capacitance C, the first capacitance C1, the second capacitance C2,3rd resistor R3, the 4th
Resistance R4, the 6th PMOS tube M6, the 7th PMOS tube M7, the 8th PMOS tube M8, the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th
NMOS tube N9, the tenth NMOS tube N10 and the 11st NMOS tube N11, the output end connection of the ratio metal-oxide-semiconductor current sampling circuit
To the inverting input of third operational amplifier A mp3, the output end of the third operational amplifier A mp3 respectively with the first capacitance
The first end of C1 is connected with the grid of the 7th NMOS tube N7, and the output end of the third operational amplifier A mp3 passes through 3rd resistor
R3 is connected to the first end of the second capacitance C2, the source electrode of the 6th PMOS tube M6, the source electrode and the 8th of the 7th PMOS tube M7
The source electrode of PMOS tube M8 is connected to power end, the grid of the 6th PMOS tube M6 respectively with the drain electrode of the 6th PMOS tube M6 and
The drain electrode of 7th NMOS tube N7 connects, the grid of the 7th PMOS tube M7 respectively with the drain electrode of the 7th PMOS tube M7, the 8th
The drain electrode of the grid of PMOS tube M8 and the 8th NMOS tube N8 is connected, the source electrode of the 7th NMOS tube N7 respectively with the 4th resistance
The first end of R4 is connected with the drain electrode of the 9th NMOS tube N9, the source electrode of the 8th NMOS tube N8 respectively with the 4th resistance R4
Two ends are connected with the drain electrode of the tenth NMOS tube N10, the grid of the 9th NMOS tube N9, the grid of the tenth NMOS tube N10 and
The grid of 11 NMOS tube N11 is connected to biased electrical pressure side, the in-phase input end difference of the third operational amplifier A mp3
The drain electrode of drain electrode, the 11st NMOS tube N11 with the 8th PMOS tube M8, the first end and third PMOS tube of sample integration capacitance C
The drain electrode of M3 is connected.
Wherein, the system power grade circuit is discussed in detail referring to Fig. 1.The ratio metal-oxide-semiconductor current sampling circuit is
For the all-wave ratio metal-oxide-semiconductor inductive current sample circuit in Fig. 3, the introduction to Fig. 3 referring to background of technology is discussed in detail.
Voltage-current conversion circuit and electric current summing circuit module are same as Example 1, and the electric current after subtracting each other is from VsenseNode flows out, to adopt
The C chargings of sample integrating capacitor.It is finally that sampling direct current corrects and sample integration circuit, the circuit module include by third operation amplifier
Device Amp3, the first capacitance C1, the second capacitance C2,3rd resistor R3 composition proportional integrator (in Fig. 7 in dashed rectangle) and
By the 7th NMOS tube N7, the 8th NMOS tube N8, the 9th NMOS tube N9, the tenth NMOS tube N10, the 11st NMOS tube N11 and the 4th
The current subtraction circuit of resistance R4 compositions.Adopting on the homophase input termination sample integration capacitance C of third operational amplifier A mp3
Sample voltage Vsense, the sampled voltage V of anti-phase input termination ratio metal-oxide-semiconductor current sampling circuitsen, after proportional integrator,
The grid of the 7th NMOS tube N7 of output termination of proportional integrator.The 9th NMOS tube N9, the tenth NMOS tube N10 and the 11st
NMOS tube N11 is by the same fixed voltage VbiasBiasing, therefore the 9th NMOS tube N9, the tenth NMOS tube N10 and the 11st NMOS
Pipe N11 is equivalent to three constant-current sources, and electric current is equal.
As the input V of proportional integratorsenseWith VsenWhen equal, the output of proportional integrator is the common mode output of amplifier,
Value is about VCC/ 2, at this point, the 7th NMOS tube N7 is identical as the bias conditions of the 8th NMOS tube N8, therefore flow through metal-oxide-semiconductor N7 and N8
Electric current it is equal, and be equal to the constant current that metal-oxide-semiconductor N9, N10 and N11 is provided.Due to the 7th NMOS tube N7 and the 8th NMOS
Pipe N8 forms current mirror, therefore the electric current for flowing through the 8th PMOS tube M8 is equal to the electric current for flowing through the 7th PMOS tube M7, is also equal to the
The constant current that nine NMOS tube N9, the tenth NMOS tube N10 and the 11st NMOS tube N11 are provided, therefore direct current correcting circuit exists
VsenseThe output current of node is 0, and the electric current for flowing through the 4th resistance R4 is also 0, is not necessarily to correction at this time.
As the V of the input of proportional integratorsenseMore than VsenWhen, the output of proportional integrator increases, therefore flows through the 7th
The electric current of NMOS tube N7 increases, and the electric current for flowing through the 9th NMOS tube N9, the tenth NMOS tube N10 and the 11st NMOS tube N11 is
Steady state value, therefore extra electric current flows to the tenth NMOS tube N10 by the 4th resistance R4, and flow through the electric current of the 8th NMOS tube N8
Reduce, therefore the electric current for flowing through the 7th PMOS tube M7 and the 8th PMOS tube M8 reduces.At this point, for VsenseFor node, pass through
The electric current that 8th PMOS tube M8 is poured into is less than the electric current pulled out by the 11st NMOS tube N11, therefore sample integration capacitance C can quilt
Sample direct current correction and sample integration circuit discharging, node VsenseVoltage can reduce, until VsenseWith VsenIt is equal therefore real
Now correct.
As the input V of proportional integratorsenseLess than VsenWhen, the output of proportional integrator reduces, therefore flows through the 7th NMOS
The electric current of pipe N7 reduces, and the electric current for flowing through the 9th NMOS tube N9, the tenth NMOS tube N10 and the 11st NMOS tube N11 is constant
Value, therefore insufficient electric current is provided by the 8th NMOS tube N8 by the 4th resistance R4, therefore flow through the electric current of the 8th NMOS tube N8
Increase, therefore the electric current for flowing through the 7th PMOS tube M7 and the 8th PMOS tube M8 also increases.At this point, for VsenseFor node, pass through
The electric current that 8th PMOS tube M8 is poured into is more than the electric current pulled out by the 11st NMOS tube N11, therefore sample integration capacitance C can quilt
Sample the charging of direct current correcting circuit, node VsenseVoltage will increase, until VsenseWith VsenIt is equal, therefore realize correction.
Pass through the sampled voltage V on the sample integration capacitance C after correctionsenseIt is sampled with ratio metal-oxide-semiconductor current sampling circuit
Obtained voltage VsenIt is equal, the accurate sampling of inductance L electric currents had not only been realized in this way, but also be continuous wave, and cut in circuit state
Not will produce burr when changing, thus can be used for automatic lifting die mould list inductance L multi output DC-DC converters accurately control and
Overcurrent protection, the detection of discontinuous inductance L current-modes (DCM) etc..Be not in false triggering, system will not be caused unstable.
It is to be illustrated to the preferable implementation of the present invention, but the invention is not limited to the implementation above
Example, those skilled in the art can also make various equivalent variations or be replaced under the premise of without prejudice to spirit of that invention
It changes, these equivalent deformations or replacement are all contained in the application claim limited range.
Claims (5)
1. a kind of all-wave inductive current sample circuit, it is characterised in that：It is adopted including system power grade circuit, ratio metal-oxide-semiconductor electric current
Sample circuit, voltage turn electric current and electric current summing circuit and the correction of sampling direct current and sample integration circuit, the system power grade electricity
First output end on road is connected to by ratio metal-oxide-semiconductor current sampling circuit the correction of sampling direct current and sample integration circuit
The second output terminal of first input end, the system power grade circuit connects by voltage turns electric current and electric current summing circuit
To the correction of sampling direct current and the second input terminal of sample integration circuit.
2. a kind of all-wave inductive current sample circuit according to claim 1, it is characterised in that：The system power grade electricity
Road includes the first PMOS tube, the first NMOS tube, the second NMOS tube and inductance, the source electrode of first PMOS tube respectively with ratio
The input terminal of metal-oxide-semiconductor current sampling circuit is connected with voltage input end, the drain electrode of first PMOS tube respectively with ratio metal-oxide-semiconductor
Second input terminal of current sampling circuit, the drain electrode of the first NMOS tube and voltage turn electric current and the input terminal of electric current summing circuit connects
Connect, first PMOS tube drain electrode by inductance connection to the second NMOS tube drain electrode, the drain electrode of second NMOS tube with
Voltage turns electric current and the third input terminal of electric current summing circuit is connected.
3. a kind of all-wave inductive current sample circuit according to claim 2, it is characterised in that：The voltage turn electric current and
Electric current summing circuit includes the second PMOS tube, third PMOS tube, the 4th PMOS tube, the 5th PMOS tube, third NMOS tube, the 4th
NMOS tube, the 5th NMOS tube, the 6th NMOS tube, first resistor, second resistance, the first operational amplifier and the second operation amplifier
Device, the source electrode of second PMOS tube, the source electrode of third PMOS tube, the source electrode of the source electrode of the 4th PMOS tube and the 5th PMOS tube are equal
Be connected to power end, the grid of second PMOS tube respectively with the drain electrode of the second PMOS tube, the drain electrode of third NMOS tube and
The grids of three PMOS tube connects, the grid of the 5th PMOS tube respectively with the drain electrode of the 5th PMOS tube, the leakage of the 4th NMOS tube
Pole is connected with the grid of the 4th PMOS tube, and the drain electrode of the third PMOS tube is corrected respectively with sampling direct current and sample integration circuit
The second input terminal and the 5th NMOS tube drain electrode connection, the drain electrode leakage with the 6th NMOS tube respectively of the 4th PMOS tube
The grid of pole, the grid of the 6th NMOS tube and the 5th NMOS tube connects, the grid and the first operation amplifier of the third NMOS tube
The output end of device connects, and the source electrode of the third NMOS tube is defeated with the reverse phase of the first end of first resistor and first arithmetic device respectively
Enter end connection, the in-phase input end of the first arithmetic device is connect with the drain electrode of the first PMOS tube, the grid of the 4th NMOS tube
The output end of pole and second operational amplifier connects, the source electrode of the 4th NMOS tube respectively with the first end of second resistance and the
The inverting input of two arithmetic units connects, and the in-phase input end of the second arithmetic device is connect with the drain electrode of the second NMOS tube.
4. a kind of all-wave inductive current sample circuit according to claim 3, it is characterised in that：The sampling direct current correction
And sample integration circuit includes buffer, switch and sample integration capacitance, the output end of the ratio metal-oxide-semiconductor current sampling circuit
It is connect with the input terminal of buffer, the output end of the buffer is connected to the first end of sample integration capacitance, institute by switch
The first end for stating sample integration capacitance is connected to the drain electrode of third PMOS tube.
5. a kind of all-wave inductive current sample circuit according to claim 3, it is characterised in that：The sampling direct current correction
And sample integration circuit includes third operational amplifier, sample integration capacitance, the first capacitance, the second capacitance, 3rd resistor, the 4th
Resistance, the 6th PMOS tube, the 7th PMOS tube, the 8th PMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the tenth
The output end of NMOS tube and the 11st NMOS tube, the ratio metal-oxide-semiconductor current sampling circuit is connected to third operational amplifier
Inverting input, the output end of the third operational amplifier grid with the first end of the first capacitance and the 7th NMOS tube respectively
Connection, the output end of the third operational amplifier are connected to the first end of the second capacitance by 3rd resistor, and the described 6th
The source electrode of the source electrode of PMOS tube, the source electrode of the 7th PMOS tube and the 8th PMOS tube is connected to power end, the 6th PMOS tube
Grid connect respectively with the drain electrode and the drain electrode of the 7th NMOS tube of the 6th PMOS tube, the grid of the 7th PMOS tube respectively with
The drain electrode of 7th PMOS tube, the drain electrode of the grid and the 8th NMOS tube of the 8th PMOS tube are connected, the source of the 7th NMOS tube
Pole is connect with the drain electrode of the first end and the 9th NMOS tube of the 4th resistance respectively, and the source electrode of the 8th NMOS tube is respectively with the 4th
The second end of resistance is connected with the drain electrode of the tenth NMOS tube, the grid of the 9th NMOS tube, the grid of the tenth NMOS tube and
The grid of 11 NMOS tubes is connected to biased electrical pressure side, and the in-phase input end of the third operational amplifier is respectively with the 8th
The drain electrode of PMOS tube, the drain electrode of the 11st NMOS tube, sample integration capacitance first end be connected with the drain electrode of third PMOS tube.
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| CN113037061B (en) * | 2021-03-10 | 2022-04-15 | 杰华特微电子股份有限公司 | Inductive current detection circuit and switching power supply using same |
| CN113252949B (en) | 2021-05-13 | 2021-11-05 | 北京芯格诺微电子有限公司 | High-precision current sampling circuit with on-chip real-time calibration |
| CN114994392B (en) * | 2022-07-19 | 2022-11-01 | 成都市易冲半导体有限公司 | High-precision current sampling circuit and method with nearly lossless chip interior |
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Effective date of registration: 20211229 Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: XI'AN TUOER MICROELECTRONICS Co.,Ltd. Address before: 510275 No. 135 West Xingang Road, Guangzhou, Guangdong, Haizhuqu District Patentee before: SUN YAT-SEN University |
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Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: Xi'an Tuoer Microelectronics Co.,Ltd. Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Xi'an Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: XI'AN TUOER MICROELECTRONICS Co.,Ltd. |