CN109039070B - BUCK type DCDC output constant current detection control circuit and method - Google Patents

BUCK type DCDC output constant current detection control circuit and method Download PDF

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CN109039070B
CN109039070B CN201810894091.6A CN201810894091A CN109039070B CN 109039070 B CN109039070 B CN 109039070B CN 201810894091 A CN201810894091 A CN 201810894091A CN 109039070 B CN109039070 B CN 109039070B
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CN109039070A (en
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郑志威
欧阳振华
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Guangdong Desai Group Co ltd
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Shenzhen Desay Microelectronic Technology Co ltd
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/08Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

Abstract

The invention relates to the technical field of constant current detection control, and particularly discloses a BUCK type DCDC output constant current detection control circuit and a method, wherein the BUCK type DCDC output constant current detection control circuit comprises an input voltage compensation network, an output voltage division network, an input current sampling network, a loop control circuit and a voltage reduction type circuit; the input voltage compensation network is connected with the output voltage division network, the output voltage division network and the input current sampling network are connected with the loop control circuit, and the voltage reduction type circuit is connected with the input current sampling network and the loop control circuit.

Description

BUCK type DCDC output constant current detection control circuit and method
Technical Field
The invention relates to the technical field of constant current detection control, and particularly discloses a BUCK type DCDC output constant current detection control circuit and method.
Background
In the prior art, in terms of the control of the constant current detection of the BUCK-type DCDC output, there are generally two ways: firstly, the high-precision sampling resistor is connected in series outside the chip, the voltage at two ends of the resistor is detected, the average value of the voltage is obtained after amplification and filtering, the loop error comparison is carried out on the average value and the reference voltage, the constant current control is realized, the high-precision sampling resistor needs to be added in the mode, the cost is improved, and meanwhile, the power consumption can be generated by the off-chip sampling resistor; and secondly, a sampling resistor is not needed, the current flowing through an upper tube is detected, meanwhile, the load compensation current is introduced, then, a feedback current signal is generated through a sampling hold circuit and a low-pass filter, the load current feedback signal is simulated, the value is compared with the reference voltage by loop error, and the constant current control is realized.
Disclosure of Invention
Aiming at the technical problems, the invention provides the BUCK type DCDC output constant current detection control circuit and the method, which have the advantages of simple structure, no additional control logic and no sampling and holding circuit and high precision.
In order to solve the technical problems, the invention provides the following specific scheme: a BUCK type DCDC output constant current detection control circuit comprises an input voltage compensation network, an output voltage division network, an input current sampling network, a loop control circuit and a voltage reduction type circuit; the input voltage compensation network is connected with the output voltage dividing network, the output voltage dividing network and the input current sampling network are connected with the loop control circuit, and the voltage reduction type circuit is connected with the input current sampling network and the loop control circuit.
Preferably, the input voltage compensation network includes resistors R4 and R5 and a transconductance amplifier, one end of the resistor R4 introduces a voltage error amount Δ VIN, the other end of the resistor R5 is connected to the negative terminal of the transconductance amplifier, the other end of the resistor R5 and the positive terminal of the transconductance amplifier are grounded, respectively, and the output terminal of the transconductance amplifier is connected to the output voltage divider network; the transconductance amplifier comprises a resistor R6.
Preferably, the output voltage divider network includes resistors R1, R2 and R3, an output voltage is introduced into one end of the resistor R1, the other end of the resistor R1 is connected to the resistor R2, the other end of the resistor R2 is connected to the resistor R3, the other end of the resistor R3 is grounded, and the output end of the transconductance amplifier is connected between the resistors R1 and R2.
Preferably, the loop control circuit comprises an error amplifier, a PWM comparator and a driving circuit; the negative pole end of the error amplifier is connected with the input current sampling network, the positive pole end of the error amplifier is connected between the resistors R2 and R3, the output end of the error amplifier is connected with the negative pole end of the PWM comparator, the positive pole end of the PWM comparator introduces a ramp signal VRAMP, the output end of the PWM comparator is connected with the driving circuit, and the driving circuit is connected with the voltage reduction type circuit.
Preferably, the buck circuit comprises an upper tube M1, a lower tube M2, an inductor L, an output capacitor C1 and a load resistor RL, one end of the inductor L is connected to the upper tube M1 and the lower tube M2 respectively, the other end of the inductor L is connected to the output capacitor C1 and the load resistor RL respectively, and the other ends of the output capacitor C1 and the load resistor RL are connected to the other end of the lower tube M2 respectively.
Preferably, the input current sampling network comprises a current amplifier and a resistor Rs, an output end of the current amplifier is respectively connected with the resistor Rs and a negative end of the error amplifier, and the other end of the resistor Rs is grounded; the positive end and the negative end of the current amplifier are connected with the D end and the S end of the upper tube M1, the current of the upper tube M1 is sampled, the input current Iin is introduced, the mirror image tube arranged in the current amplifier samples the upper tube M1 in an equal proportion, the current of the upper tube M1 is sampled, and the input current Iin is introduced.
The invention also provides a BUCK type DCDC output constant current detection control method, which comprises the following steps:
s1, sampling an input voltage error amount delta VIN by the input voltage compensation network, and generating an output compensation current Ic through the input voltage compensation network;
s2, sampling the output voltage VOUT and the compensation current Ic by the output voltage divider network to obtain a compensation voltage V2;
s3, sampling the input current Iin by the input current sampling network, and generating a sampling voltage Vs proportional to the input current Iin through the input current sampling network;
s4, comparing the difference between the sampling voltage Vs and the compensation voltage V2 by the loop control circuit, and generating a control driving signal after amplification and comparison;
and S5, the voltage reduction type circuit receives the driving signal to realize constant current control.
Preferably, the input voltage error amount Δ VIN is a difference between the actual input voltage VINact and the ideal input voltage VINideal.
Preferably, the step S1 specifically includes the following steps: the input voltage compensation network samples an input voltage error amount delta VIN, the input voltage error amount delta VIN passes through a voltage division network consisting of resistors R4 and R5 to obtain delta VIN multiplied by beta, and the delta VIN multiplied by beta is sent to the transconductance amplifier, and an output compensation current Ic = ± (delta VIN multiplied by beta)/R6 is output, wherein beta is a voltage division coefficient of the resistors R4 and R5.
Preferably, the operation formula of the compensation voltage V2 in the step S2 is V2= α VOUT ± Ic × R1, where α is a voltage division coefficient of the resistors R1, R2, and R3.
Preferably, the step S3 specifically includes the following steps: the input current sampling network samples an input current Iin, and the input current Iin flows into an Rs resistor after being reduced by K times through a current amplifier to generate a sampling voltage Vs which is proportional to the input current Iin, wherein Vs = Iin/K × Rs.
Preferably, the step S4 specifically includes the following steps: after the control circuit works stably, the sampling voltage Vs and the compensation voltage V2 at two ends of an error amplifier in the loop control circuit are equal, namely Iin/K × Rs = alpha VOUT + -Ic × R1, and the sampling voltage is substituted into an energy conservation formula (VINIDeal + delta VIN) × Iin × η = VOUT × Io, so that Io =can be obtained
Figure DEST_PATH_IMAGE001
Where Io is the output current, η is the system efficiency, and D is the duty cycle = VOUT/VIN.
Compared with the prior art, the invention has the beneficial effects that: 1. the invention realizes the output constant current control by detecting the input current and simultaneously introducing the input voltage compensation network, introduces the compensation to the input voltage and the output voltage, has no influence of offset factors such as inductance value, sample hold, capacitance, charge injection, buffer operational amplifier and the like, has simple structure, does not have additional control logic and sample hold circuit, and has high precision;
2. because the efficiency eta of the DCDC can be approximately constant under the full load condition, the input current Iin can be realized by the sampling circuit, and the actual output current Io is greatly influenced by the input voltage and the output voltage, the invention eliminates the influence of the input voltage and the output voltage on Io by introducing compensation quantity, thereby realizing constant current control.
Drawings
Fig. 1 is a specific circuit connection diagram according to a first embodiment of the invention.
Detailed Description
In order to explain the technical solution of the present invention in detail, the technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiment of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
The first embodiment is as follows:
referring to fig. 1, the present embodiment provides a BUCK-type DCDC output constant current detection control circuit, which includes an input voltage compensation network, an output voltage divider network, an input current sampling network, a loop control circuit, and a BUCK-type circuit; the input voltage compensation network is connected with the output voltage division network, the output voltage division network and the input current sampling network are connected with the loop control circuit, and the voltage reduction type circuit is connected with the input current sampling network and the loop control circuit.
Specifically, the input voltage compensation network samples the input voltage error amount Δ VIN to generate an output compensation current Ic, the output voltage divider network samples the output voltage VOUT and the compensation current Ic to obtain a compensation voltage V2, the input current sampling network samples the input current Iin, and the input current sampling network generates a sampling voltage Vs proportional to the input current Iin; the loop control circuit compares the difference between the sampling voltage Vs and the compensation voltage V2, and generates a control driving signal after amplification and comparison; the voltage reduction type circuit receives a driving signal to realize constant current control.
The input voltage compensation network comprises resistors R4 and R5 and a transconductance amplifier, wherein one end of the resistor R4 introduces a voltage error amount delta VIN, the other end of the resistor R5 is connected with the negative electrode end of the transconductance amplifier, the other end of the resistor R5 and the positive electrode end of the transconductance amplifier are respectively grounded, and the output end of the transconductance amplifier is connected with an output voltage divider network; the transconductance amplifier includes a resistor R6, and specifically, the input voltage compensation network samples an input voltage error amount Δ VIN, the input voltage error amount Δ VIN passes through a voltage division network formed by resistors R4 and R5 to obtain Δ VIN × β, and the Δ VIN × β is fed into the transconductance amplifier, and outputs a compensation current Ic = ± (Δ VIN × β)/R6, where β is a voltage division coefficient of resistors R4 and R5.
The output voltage divider network comprises resistors R1, R2 and R3, output voltage is introduced into one end of the resistor R1, the other end of the resistor R1 is connected with the resistor R2, the other end of the resistor R2 is connected with the resistor R3, the other end of the resistor R3 is grounded, and the output end of the transconductance amplifier is connected between the resistors R1 and R2.
The loop control circuit comprises an error amplifier, a PWM comparator and a driving circuit; the negative pole end of the error amplifier is connected with the input current sampling network, the positive pole end of the error amplifier is connected between the resistors R2 and R3, the output end of the error amplifier is connected with the negative pole end of the PWM comparator, the positive pole end of the PWM comparator introduces the ramp signal VRAMP, the output end of the PWM comparator is connected with the driving circuit, and the driving circuit is connected with the voltage reduction type circuit.
The output voltage divider network samples the output voltage VOUT and the compensation current Ic to obtain a compensation voltage V2, V2= α VOUT ± Ic × R1, where α is a voltage division coefficient of resistors R1, R2, and R3.
The buck circuit comprises an upper tube M1, a lower tube M2, an inductor L, an output capacitor C1 and a load resistor RL, wherein one end of the inductor L is connected with the upper tube M1 and the lower tube M2 respectively, the other end of the inductor L is connected with an output capacitor C1 and the load resistor RL respectively, and the other ends of the output capacitor C1 and the load resistor RL are connected with the other end of the lower tube M2 respectively.
The input current sampling network comprises a current amplifier and a resistor Rs, the output end of the current amplifier is respectively connected with the resistor Rs and the negative end of the error amplifier, the other end of the resistor Rs is grounded, the positive end and the negative end of the current amplifier are connected with the D end and the S end of the upper tube M1, a mirror image tube is arranged in the current amplifier to sample the upper tube M1 in an equal proportion, the current of the upper tube M1 is sampled, and the input current Iin is introduced.
An input current sampling network samples an input current Iin, the input current Iin flows into an Rs resistor after being reduced by K times through a current amplifier to generate a sampling voltage Vs which is proportional to the input current Iin, the sampling voltage Vs = Iin/KxRs, after a control circuit works stably, the sampling voltage Vs at two ends of an error amplifier in a loop control circuit is equal to a compensation voltage V2, namely Iin/KxRs = alpha VOUT +/-Ic multiplied by R1, the sampling voltage Vs is substituted into an energy conservation formula (VINIDeal + delta VIN) multiplied by Iin multiplied by eta = VOUT multiplied by Io, and Io = can be obtained
Figure 73310DEST_PATH_IMAGE001
Wherein Io is an output current, η is a system efficiency, D is a duty ratio = VOUT/VIN, and as can be known from an energy conservation formula, the output current Io is related to an input voltage VIN, the output voltage VOUT, the system efficiency η and the input current Iin, since the DCDC works under a full load condition, the efficiency η can be approximated as a constant, and the derivation process is that the efficiency η = 1-loss, loss = Io 2 RON, Io is determined when applied, that is, is constant when the DCDC is under the full load condition; RON is the on-resistance of upper tube M1 and lower tube M2: the upper tube M1 and the lower tube M2 determine RON, so η can be approximately constant, the input current Iin can be realized through a sampling circuit, and the present embodiment eliminates the influence of the input voltage VIN and the output voltage VOUT on the output current Io by introducing a compensation amount, so as to realize constant current control.
As can be seen from the above, the output current Io is independent of the output voltage VOUT, and the input voltage compensation can be realized by reducing the error term coefficient α + (γ × β)/D in this embodiment, so that the circuit is not affected by offset factors such as inductance, sample-and-hold, capacitance, charge injection, and buffer operational amplifier, and has high control accuracy.
Example two:
the embodiment provides a BUCK type DCDC output constant current detection control method, which comprises the following steps:
s1, the input voltage compensation network samples the input voltage error amount delta VIN and generates the output compensation current Ic through the input voltage compensation network.
The input voltage error Δ VIN is a difference between the actual input voltage VINact and the ideal input voltage VINideal, and specifically, the step S1 specifically includes the following steps: the input voltage compensation network samples an input voltage error amount delta VIN, the input voltage error amount delta VIN passes through a voltage division network consisting of resistors R4 and R5 to obtain delta VIN multiplied by beta, and the delta VIN multiplied by beta is sent to the transconductance amplifier, and an output compensation current Ic = ± (delta VIN multiplied by beta)/R6 is output, wherein beta is a voltage division coefficient of the resistors R4 and R5.
S2, sampling the output voltage VOUT and the compensation current Ic by the output voltage dividing network to obtain a compensation voltage V2, wherein the operation formula of the compensation voltage V2 is V2= alpha VOUT +/-Ic multiplied by R1, and alpha is the dividing coefficient of resistors R1, R2 and R3.
S3, sampling the input current Iin by the input current sampling network, and generating a sampling voltage Vs proportional to the input current Iin through the input current sampling network; specifically, an input current sampling network samples an input current Iin, and the input current Iin is reduced by K times through a current amplifier and flows into an Rs resistor to generate a sampling voltage Vs proportional to the input current Iin, wherein Vs = Iin/K × Rs.
S4, comparing the difference between the sampling voltage Vs and the compensation voltage V2 by the loop control circuit, generating a control driving signal after amplification and comparison, wherein after the control circuit works stably, the sampling voltage Vs and the compensation voltage V2 at two ends of an error amplifier in the loop control circuit are equal, namely Iin/KxRs = alpha VOUT +/-Ic multiplied by R1, and substituting the Iin/for an energy conservation formula (VINIDeal + delta VIN) multiplied by Iin multiplied by eta = VOUT multiplied by Io, so that Io =can be obtained
Figure 692510DEST_PATH_IMAGE001
Where Io is the output current, η is the system efficiency, and D is the duty cycle = VOUT/VIN.
And S5, the voltage reduction type circuit receives the driving signal to realize constant current control.
From the above, the general calculation process is: the output voltage divider network receives the output voltage VOUT and the compensation current Ic = ± (Δ VIN × β)/R6, and generates the compensation voltage V2= α VOUT ± Ic × R1= α × VOUT ± γ × β × (Δ VIN), which is given by the formula of (i);
an input current sampling network samples an input current Iin and generates a sampling voltage Vs = Iin/K multiplied by Rs which is in direct proportion to the input current Iin, and the formula is set as 2;
after the system works stably, the input voltages V2 and Vs at two ends of an error amplifier in the loop control circuit are equal, namely V2= Vs, Iin/K × Rs = alpha VOUT + -Ic × R1, and the formula is defined as (c);
substituting the first and the second into the third to obtain Iin = K/Rs x (alpha x VOUT +/-gamma x beta x delta VIN), and setting the formula as the fourth;
from the energy conservation, (VINideal + DELTA VIN) x Iin x eta = VOUT x Io, the formula is given as (v);
substituting the four into the five to obtain Io =
Figure 366068DEST_PATH_IMAGE001
As can be seen from the above equation, the output current Io is independent of the output voltage VOUT; the input voltage compensation can be realized by reducing the error term coefficient alpha + (gamma multiplied by beta)/D, and the influence of the input voltage VIN and the output voltage VOUT on the output current Io is eliminated, so that the constant current control is realized.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (9)

1. The utility model provides a BUCK type DCDC output constant current detection control circuit which characterized in that: the circuit comprises an input voltage compensation network, an output voltage divider network, an input current sampling network, a loop control circuit and a voltage reduction type circuit; the input voltage compensation network is connected with an output voltage divider network, the output voltage divider network and the input current sampling network are connected with a loop control circuit, and the voltage reduction type circuit is connected with the input current sampling network and the loop control circuit;
the input voltage compensation network comprises resistors R4 and R5 and a transconductance amplifier, wherein a voltage error amount delta VIN is introduced into one end of the resistor R4, the other end of the resistor R5 is connected with the negative electrode end of the transconductance amplifier, the other end of the resistor R5 and the positive electrode end of the transconductance amplifier are respectively grounded, and the output end of the transconductance amplifier is connected with an output voltage divider network; the transconductance amplifier comprises a resistor R6;
the output voltage divider network comprises resistors R1, R2 and R3, an output voltage is introduced into one end of the resistor R1, the other end of the resistor R1 is connected with the resistor R2, the other end of the resistor R2 is connected with the resistor R3, the other end of the resistor R3 is grounded, and the output end of the transconductance amplifier is connected between the resistors R1 and R2;
the loop control circuit comprises an error amplifier, a PWM comparator and a driving circuit; the negative pole end of the error amplifier is connected with the input current sampling network, the positive pole end of the error amplifier is connected between the resistors R2 and R3, the output end of the error amplifier is connected with the negative pole end of the PWM comparator, the positive pole end of the PWM comparator introduces a ramp signal VRAMP, the output end of the PWM comparator is connected with the driving circuit, and the driving circuit is connected with the voltage reduction type circuit.
2. The BUCK-type DCDC output constant current detection control circuit according to claim 1, wherein: the buck circuit comprises an upper tube M1, a lower tube M2, an inductor L, an output capacitor C1 and a load resistor RL, wherein one end of the inductor L is connected with the upper tube M1 and the lower tube M2 respectively, the other end of the inductor L is connected with the output capacitor C1 and the load resistor RL respectively, and the other ends of the output capacitor C1 and the load resistor RL are connected with the other end of the lower tube M2 respectively.
3. The BUCK-type DCDC output constant current detection control circuit according to claim 2, wherein: the input current sampling network comprises a current amplifier and a resistor Rs, the output end of the current amplifier is respectively connected with the resistor Rs and the negative end of the error amplifier, and the other end of the resistor Rs is grounded; the positive end and the negative end of the current amplifier are connected with the D end and the S end of the upper tube M1, the current of the upper tube M1 is sampled, and the input current Iin is introduced.
4. The control method of the BUCK-type DCDC output constant current detection control circuit according to claim 3, comprising the steps of:
s1, sampling an input voltage error amount delta VIN by the input voltage compensation network, and generating an output compensation current Ic through the input voltage compensation network;
s2, sampling the output voltage VOUT and the compensation current Ic by the output voltage divider network to obtain a compensation voltage V2;
s3, sampling the input current Iin by the input current sampling network, and generating a sampling voltage Vs proportional to the input current Iin through the input current sampling network;
s4, comparing the difference between the sampling voltage Vs and the compensation voltage V2 by the loop control circuit, and generating a control driving signal after amplification and comparison;
and S5, the voltage reduction type circuit receives the driving signal to realize constant current control.
5. The control method of the BUCK-type DCDC output constant current detection control circuit according to claim 4, wherein: the input voltage error amount Δ VIN is a difference between the actual input voltage VINact and the ideal input voltage VINideal.
6. The method for controlling the BUCK-type DCDC output constant current detection control circuit according to claim 5, wherein the step S1 specifically includes the following steps: the input voltage compensation network samples an input voltage error amount delta VIN, the input voltage error amount delta VIN passes through a voltage division network consisting of resistors R4 and R5 to obtain delta VIN multiplied by beta, and the delta VIN multiplied by beta is sent to the transconductance amplifier, and an output compensation current Ic is +/-minus or plus (delta VIN multiplied by beta)/R6, wherein beta is a resistor.
7. The control method of the BUCK-type DCDC output constant current detection control circuit according to claim 6, wherein: the operation formula of the compensation voltage V2 in step S2 is V2 ═ α VOUT ± Ic × R1, where α is the voltage division coefficient of the resistors R1, R2, and R3.
8. The method for controlling the BUCK-type DCDC output constant current detection control circuit according to claim 7, wherein the step S3 specifically includes the following steps: the input current sampling network samples the input current Iin, and the input current Iin is reduced by K times through the current amplifier and flows into the Rs resistor to generate a sampling voltage Vs which is proportional to the input current Iin and is Iin/K multiplied by Rs.
9. The method for controlling the BUCK-type DCDC output constant current detection control circuit according to claim 8, wherein the step S4 specifically includes the following steps: after the control circuit works stably, the sampling voltage Vs and the compensation voltage V2 at two ends of the error amplifier in the loop control circuit are equal, that is, Iin/K × Rs ═ α VOUT ± Ic × R1 is substituted into the energy conservation formula (VINideal + Δ VIN) × Iin × η ═ VOUT × Io, and the obtained product can be obtained
Figure FDA0002678434730000021
Figure FDA0002678434730000022
Where Io is the output current, η is the system efficiency, and D is the duty cycle VOUT/VIN.
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