CN112162590A - Analog voltage subtracter circuit - Google Patents
Analog voltage subtracter circuit Download PDFInfo
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- CN112162590A CN112162590A CN202010995287.1A CN202010995287A CN112162590A CN 112162590 A CN112162590 A CN 112162590A CN 202010995287 A CN202010995287 A CN 202010995287A CN 112162590 A CN112162590 A CN 112162590A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Abstract
The invention discloses an analog voltage subtracter circuit. The voltage subtracter circuit comprises a first voltage-to-current circuit, a second voltage-to-current circuit, a current mirror circuit and an output load circuit. The first voltage-to-current circuit converts the voltage V1 into the current I1, the second voltage-to-current circuit converts the voltage V2 into the current I2, and the current mirror circuit flows the difference current I3 between the current I1 and the current I2 into the output load circuit to generate the output voltage, so that the voltage-current-voltage conversion is realized, and the subtraction operation of the voltage V1 and the voltage V2 is completed.
Description
Technical Field
The invention relates to an analog voltage subtractor circuit, in particular to an analog voltage subtractor circuit used in a switching power supply, which is used for sampling and holding a current reflected on an exciting inductive current after an external Rcs resistor is converted into voltage and then carrying out subtraction operation.
Background
In a switching power supply circuit, a sampling and holding operation is often performed after a current external Rcs resistor reflected on an excitation inductor is converted into a voltage. The invention provides an analog voltage subtractor circuit for a switching power supply based on the fact that peak current and valley current exist in exciting inductance current, and subtraction operation is often required to be carried out on sampled peak voltage and valley voltage.
Fig. 1 shows an asymmetric half-bridge flyback converter switching power supply topology, in which the voltage across the Rcs resistor reflects the current change across the excitation inductor. The excitation inductor current changes in a triangular wave pattern as shown in fig. 2. FIG. 2 is a waveform of voltage over time on the Rcs resistor. In a switching power supply circuit, it is often necessary to perform subtraction after level shifting of sampled peak voltage and sampled valley voltage. When the switch tube Q1 is turned on, the voltage across the Rcs resistor is sampled at the rising edge of the switch tube Q1 to obtain a valley voltage, and when the switch tube Q1 is turned off, the voltage across the Rcs resistor is sampled at the falling edge of the switch tube Q1 to obtain a peak voltage. Since the valley current is usually a negative current, it is usually necessary to shift the peak voltage and the valley voltage by the same voltage and then perform a sample-and-hold operation, and then subtract the voltage obtained by the sample-and-hold operation. Wherein the switch Q1 and the switch Q2 are complementary switches in fig. 2.
Fig. 3 shows a conventional analog subtractor circuit configuration. Since the amplifier EA is an NMOS transistor input type operational amplifier or a PMOS transistor input type operational amplifier, the ranges of the first input voltage and the second input voltage are very limited. When the amplifier EA is an NMOS transistor input type operational amplifier, a second input voltage having a smaller voltage of the first input voltage and the second input voltage may not satisfy an input range of the operational amplifier EA, so that the NMOS transistor at an input end of the second input voltage is in a linear region, and the operational amplifier EA loses an amplification function; when the amplifier EA is a PMOS transistor input type operational amplifier, the first input voltage with a larger voltage of the first input voltage and the second input voltage may not satisfy the input range of the operational amplifier EA, so that the PMOS transistor at the input end of the first input voltage is in a linear region, and the operational amplifier EA loses the amplification function. It can be seen that the conventional analog voltage subtractor circuit cannot meet the design requirements.
Disclosure of Invention
In view of the limitations of the conventional analog voltage subtractor circuit, the present invention provides a novel analog voltage subtractor circuit, which solves the problem that the operational amplifier loses the amplification function under the condition that the difference between the first input voltage and the second input voltage is relatively large.
To solve the above problem, the present invention provides an analog voltage subtractor circuit, comprising: the circuit comprises a first voltage-to-current circuit, a second voltage-to-current circuit, a current mirror circuit and an output load circuit;
the first voltage-to-current circuit is provided with a first error amplifier, a first NMOS (N-channel metal oxide semiconductor) tube and a first resistor, wherein the positive input end of the first error amplifier is connected with a first input voltage, the negative input end of the first error amplifier is connected with the source electrode of the first NMOS tube and one end of the first resistor, the output end of the first error amplifier is connected with the grid electrode of the first NMOS tube, the other end of the first resistor is connected with the ground, and first currents are generated at two ends of the first resistor;
the second voltage-to-current circuit is provided with a second error amplifier, a second NMOS (N-channel metal oxide semiconductor) tube and a second resistor, wherein the positive input end of the second error amplifier is connected with a second input voltage, the negative input end of the second error amplifier is connected with the source electrode of the second NMOS tube and one end of the second resistor, the output end of the second error amplifier is connected with the grid electrode of the second NMOS tube, the other end of the second resistor is connected with the ground, and second current is generated at two ends of the second resistor;
the current mirror circuit is provided with a first PMOS tube and a second PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube is connected with the power supply; the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the connection point of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube is used as an output port of difference current between the first current and the second current;
the output load circuit is composed of a third resistor, one end of the third resistor is connected with the output port, the other end of the third resistor is connected with the ground, and the third resistor is used for converting the difference current into output voltage.
In one embodiment, the analog voltage subtractor circuit is further provided with a differential current mirror circuit, the differential current mirror circuit is connected between the output port and the third resistor, the differential current mirror circuit includes a first mirror circuit formed by a third NMOS transistor and a fourth NMOS transistor and a second mirror circuit formed by a third PMOS transistor and a fourth PMOS transistor, currents flowing through the third NMOS transistor, the fourth NMOS transistor, the third PMOS transistor and the fourth PMOS transistor are the same, and the current flowing through the third NMOS transistor is the differential current.
In one embodiment, the current flowing through the first PMOS transistor of the current mirror circuit is the same as the current flowing through the second PMOS transistor.
In one embodiment, the first resistor has a resistance of R1, the second resistor has a resistance of R2, and R1 is R2; the third resistor has a resistance value of R3, R3 ═ k × R1, R3 ═ k × R2, and k is a real number greater than 0.
In one embodiment, the first current is I1, I1 ═ V1/R1, where V1 is the first input voltage; the second current is I2, I2 ═ V2/R2, and V2 is the second input voltage; the difference current is I3, I3 ═ I1-I2.
In one embodiment, the output voltage is VOUT, VOUT is I3 × R3 (I1-I2) × R3 (V1/R1-V2/R2) × R3 (R3/R1) (V1-V2) × k × (V1-V2).
In one embodiment, the output voltage VOUT satisfies the relationship: VOUT is V2+ Vds, and Vds is the source-drain voltage of the second NMOS transistor.
In one embodiment, the first input voltage is V1 and the second input voltage is V2, V1 is (1+1/k) × V2+ (1/k) × Vds, k is a real number greater than 0, and Vds is a source-drain voltage of the second NMOS transistor.
Compared with the prior art, the invention has the beneficial effects that:
(1) the analog voltage subtractor circuit adopts a voltage modulator structure, converts input voltage into current by using an error amplifier and a resistor, and can accurately complete subtraction operation of two input voltages;
(2) the adjusting tubes adopted in the first voltage-to-current circuit and the second voltage-to-current circuit are NMOS tubes, namely source follower circuits, compared with circuits using PMOS tubes as common source stages, the compensation is easier, and the loop stability is better;
(3) the current mirror image circuit is used for multiple times in the circuit, so that the current can be accurately copied; meanwhile, the difference current can accurately reflect the difference between the two currents;
(4) due to the adoption of the current mirror circuit, the relation between the first input voltage V1 and the first input voltage V2 is not bound, and even if the difference value between the first input voltage V1 and the second input voltage V2 is large, the most basic relation between the first input voltage V1 and the first input voltage V2 is only required to be satisfied: v1> V2, the analog voltage subtracter circuit can work normally.
Drawings
Fig. 1 is a schematic diagram of a switching power supply topology of a conventional asymmetric half-bridge flyback converter;
FIG. 2 is a graph showing the variation of voltage on Rcs with time;
FIG. 3 is a schematic diagram of a conventional analog voltage subtractor;
FIG. 4 is a schematic diagram of an analog voltage subtractor circuit according to a first embodiment of the invention;
FIG. 5 is a diagram of an analog voltage subtractor circuit according to a second embodiment of the invention.
Detailed Description
First embodiment
Referring to fig. 4, an analog voltage subtractor circuit includes a first voltage-to-current circuit connected to a first input voltage V1, a second voltage-to-current circuit connected to a second input voltage V2, a current mirror circuit, and an output load circuit. The first input voltage V1 the second input voltage V2 is the voltage across the Rcs resistor connected to one end of the exciting inductor of the switching power supply circuit, and the first voltage V1 is greater than the second input voltage V2.
The first voltage-to-current circuit is used for converting a first input voltage V1 into a first current I1.
The first voltage-to-current circuit is composed of a first error amplifier EA1, a first NMOS transistor N1 and a first resistor R1, the first error amplifier EA1 is an NMOS transistor input type error amplifier, a positive input end of the first error amplifier EA1 is connected with a first input voltage V1, a negative input end of the first error amplifier EA1 is connected with a source electrode of the first NMOS transistor N1 and one end of the first resistor R1, an output end of the first error amplifier EA1 is connected with a gate electrode of the first NMOS transistor N1, and the other end of the first resistor R1 is connected with the ground. The voltage of the end of the first resistor R1 connected to the first NMOS transistor N1 is clamped to the same value as the first input voltage V1 due to the action of the first error amplifier EA1, and the voltage across the first resistor R1 is equal to the first input voltage V1 due to the grounding of the other segment of the first resistor R1. At this time, the first current I1 flowing through the first resistor R1 satisfies the following relation: i1 ═ V1/R1, V1 first input voltage, and R1 is the resistance of the first resistor R1.
The second voltage-to-current circuit is used for converting the second input voltage V2 into a second current I2.
The second voltage-to-current circuit is composed of a second error amplifier EA2, a second NMOS tube N2 and a second resistor R2, the second error amplifier EA2 is a PMOS tube input type error amplifier, a positive input end of the second error amplifier EA2 is connected with the first input voltage V2, a negative input end of the second error amplifier EA2 is connected with a source electrode of the second NMOS tube N2 and one end of the second resistor R2, an output end of the second error amplifier EA2 is connected with a gate electrode of the second NMOS tube N2, and the other end of the second resistor R2 is connected with the ground.
Due to the action of the second error amplifier EA2, the voltage at the end of the second resistor R2 connected to the second NMOS transistor N2 is clamped to the same value as the first input voltage V2, and since the lower end of the second resistor R2 is grounded, the voltage at the two ends of the second resistor R2 is equal to the first input voltage V2, and the second current I2 flowing through the second resistor R2 satisfies the following relation: i2 ═ V2/R2, V2 is the second input voltage V2, and R2 is the resistance of the second resistor. Since the second resistor R2 and the second NMOS transistor N2 are in the same branch, the current flowing through the second NMOS transistor N2 is the same as the second current I2 flowing through the second resistor R2, as can be seen from the continuity of the current.
The current mirror circuit is used for generating a difference current I3 between the first current and the second current.
The current mirror circuit consists of a first PMOS tube P1 and a second PMOS tube P2, the drain electrode of the first PMOS tube P1 is connected with the drain electrode of a first NMOS tube N1, the grid electrode of the first PMOS tube P1 is connected with the drain electrode of a first NMOS tube N1, and the source electrode of the first PMOS tube P1 is connected with a power supply; the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the first PMOS tube P1, the source electrode of the second PMOS tube P2 is connected with a power supply, the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the second NMOS tube N2, and the connection point of the drain electrode of the second PMOS tube P2 and the drain electrode N2 of the second NMOS tube is used as an output port of a difference current I3 between the first current I1 and the second current I2. Since the first resistor R1 is in the same branch as the first NMOS transistor and the first PMOS transistor P1, the current flowing through the first NMOS transistor N1 and the first PMOS transistor P1 is the same as the first current I1 flowing through the first resistor R1, respectively, as can be seen from the continuity of the current. Since the first PMOS transistor P1 and the second PMOS transistor P2 constitute a current mirror circuit, the current flowing through the second PMOS transistor P2 is the same as the first current I1 flowing through the first resistor R1.
The output load circuit is composed of a third resistor, one end of the third resistor R3 is connected to the output port, the other end is connected to ground, and the third resistor R3 is used for converting the difference current I3 into the output voltage VOUT.
In the present embodiment, the first resistor R1 is the same as the second resistor R2, and the first current I1 is larger than the second current I2 because the first input voltage V1 is larger than the first input voltage V2. Since the first current I1 and the second current I2 cannot change abruptly, the difference current I3 between the first current I1 and the second current I2 flows into the third resistor R3, and the difference current I3 is I1-I2. From this, the expression of the output voltage VOUT is: VOUT-I3 × R3 ═ (I1-I2) × R3 ═ (V1/R1-V2/R2) × R3 ═ (R3/R1) (V1-V2) × (V1-V2), and k is a real number greater than 0.
Meanwhile, the output expression of the output voltage VOUT can also be expressed as: VOUT is V2+ Vds, where Vds is the source-drain voltage of the second NMOS transistor N2. The relationship between the first input voltage V1 and the first input voltage V2 is: v1 ═ (1+1/k) × V2+ (1/k) × Vds. The relationship between the first input voltage V1 and the first input voltage V2 is influenced by the magnitude of the value k.
Second embodiment
Referring to fig. 5, an analog voltage subtractor circuit includes: the circuit comprises a first voltage-to-current circuit, a second voltage-to-current circuit, a current mirror circuit, an output load circuit, an output end and a difference current mirror circuit. The first voltage-to-current circuit, the second voltage-to-current circuit and the current mirror circuit are the same and will not be described herein.
The second embodiment differs from the first embodiment in that: in the second embodiment, a differential current mirror circuit is added, and the output load circuit and the output terminal are connected to the differential current mirror circuit, respectively. The differential current mirror circuit comprises a first mirror circuit consisting of a third NMOS transistor N3 and a fourth NMOS transistor N4 and a second mirror circuit consisting of a third PMOS transistor P3 and a fourth PMOS transistor P4, wherein the currents flowing through the third NMOS transistor N3, the fourth NMOS transistor N4, the third PMOS transistor P3 and the fourth PMOS transistor P4 are the same, and the current flowing through the third NMOS transistor N3 is differential current I3.
In this embodiment, since the third NMOS transistor N3 and the fourth NMOS transistor N4 are current mirror circuits, the current flowing through the fourth NMOS transistor N4 is also the difference current I3. Since the fourth NMOS transistor N4 and the third PMOS transistor P3 are in the same branch, the current flowing through the third PMOS transistor P3 is also the differential current I3, and meanwhile, the third PMOS transistor P3 and the fourth PMOS transistor P4 form another current mirror circuit, so the current flowing through the fourth PMOS transistor P4 is also the differential current I3, and at this time, the differential current I3 all flows into the output third resistor R3. Wherein the magnitude of the difference current I3 is: i3 ═ I1-I2.
From this, the expression of the output voltage VOUT is: VOUT-I3 × R3 ═ (I1-I2) × R3 ═ (V1/R1-V2/R2) × R3 ═ (R3/R1) (V1-V2) × (V1-V2).
Because the difference current I3 is mirrored twice, rather than being directly connected to the output load at the drains of the second PMOS transistor P2 and the second NMOS transistor N2, the structure of the analog voltage subtractor circuit breaks the relationship between the first input voltage V1 and the first input voltage V2. The most basic relationship between the first input voltage V1 and the first input voltage V2 only needs to be satisfied: v1> V2, the analog voltage subtracter circuit can work normally.
It should be noted that the above preferred embodiments should not be construed as limiting the invention. The protection scope of the present invention shall be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various equivalent substitutions, modifications and additions may be made without departing from the true spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. An analog voltage subtractor circuit, comprising: the circuit comprises a first voltage-to-current circuit, a second voltage-to-current circuit, a current mirror circuit and an output load circuit;
the first voltage-to-current circuit is provided with a first error amplifier, a first NMOS (N-channel metal oxide semiconductor) tube and a first resistor, wherein the positive input end of the first error amplifier is connected with a first input voltage, the negative input end of the first error amplifier is connected with the source electrode of the first NMOS tube and one end of the first resistor, the output end of the first difference amplifier is connected with the grid electrode of the first NMOS tube, the other end of the first resistor is connected with the ground, and first currents are generated at two ends of the first resistor;
the second voltage-to-current circuit is provided with a second error amplifier, a second NMOS (N-channel metal oxide semiconductor) tube and a second resistor, wherein the positive input end of the second error amplifier is connected with a second input voltage, the negative input end of the second error amplifier is connected with the source electrode of the second NMOS tube and one end of the second resistor, the output end of the second error amplifier is connected with the grid electrode of the second NMOS tube, the other end of the second resistor is connected with the ground, and second currents are generated at two ends of the second resistor;
the current mirror circuit is provided with a first PMOS tube and a second PMOS tube, the drain electrode of the first PMOS tube is connected with the drain electrode of a first NMOS tube, the grid electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the source electrode of the first PMOS tube is connected with a power supply; the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the connection point of the drain electrode of the second PMOS tube and the drain electrode of the second NMOS tube is used as an output port of difference current between the first current and the second current;
the output load circuit is composed of a third resistor, one end of the third resistor is connected with the output port, the other end of the third resistor is connected with the ground, and the third resistor is used for converting the differential current into output voltage.
2. The analog voltage subtractor circuit of claim 1 wherein: the differential current mirror circuit is connected between the output port and the third resistor, comprises a first mirror circuit consisting of a third NMOS tube and a fourth NMOS tube and a second mirror circuit consisting of a third PMOS tube and a fourth PMOS tube, and has the same current flowing through the third NMOS tube, the fourth NMOS tube, the third PMOS tube and the fourth PMOS tube, and the current flowing through the third NMOS tube is the differential current.
3. The analog voltage subtractor circuit of claim 1 wherein: the current flowing through the first PMOS tube of the current mirror circuit is the same as the current flowing through the second PMOS tube.
4. The analog voltage subtractor circuit of claim 3 wherein: the resistance value of the first resistor is R1, the resistance value of the second resistor is R2, and R1 is R2; the resistance value of the third resistor is R3, R3 is k × R1, R3 is k × R2, and k is a real number greater than 0.
5. The analog voltage subtractor circuit of claim 4 wherein: the first current is I1, I1 ═ V1/R1, where V1 is the first input voltage; the second current is I2, I2 ═ V2/R2, and V2 is the second input voltage; the difference current is I3, I3 is I1-I2.
6. The analog voltage subtractor circuit of claim 5 wherein:
the output voltage is VOUT，VOUT＝I3×R3＝(I1-I2)×R3＝(V1/R1-V2/R2)×R3＝(R3/R1)(V1-V2)＝k×(V1-V2)。
7. The analog voltage subtractor circuit of claim 5 wherein: the output voltage VOUT satisfies the relation: VOUT is V2+ Vds, and Vds is the source-drain voltage of the second NMOS transistor.
8. The voltage subtractor circuit of claim 1 wherein: the first input voltage is V1, the second input voltage is V2, V1 is (1+1/k) × V2+ (1/k) × Vds, k is a real number greater than 0, and Vds is a source-drain voltage of the second NMOS transistor.
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|---|---|---|---|
| CN202010995287.1A CN112162590A (en) | 2020-09-21 | 2020-09-21 | Analog voltage subtracter circuit |
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| CN202010995287.1A CN112162590A (en) | 2020-09-21 | 2020-09-21 | Analog voltage subtracter circuit |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008016143A (en) * | 2006-07-07 | 2008-01-24 | Sanyo Electric Co Ltd | Subtraction circuit |
| CN103023323A (en) * | 2011-09-20 | 2013-04-03 | 万国半导体(开曼)股份有限公司 | Average inductive current type voltage control method and variable reference voltage generating device used by method |
| TW201547320A (en) * | 2014-06-11 | 2015-12-16 | Richtek Technology Corp | Light emitting device driver circuit and driving method of light emitting device circuit |
| CN105634449A (en) * | 2015-12-30 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Differential voltage absolute value circuit |
| CN105763047A (en) * | 2016-03-08 | 2016-07-13 | 中山大学 | Full wave inductance current sampling circuit |
| CN105866517A (en) * | 2015-01-23 | 2016-08-17 | 联咏科技股份有限公司 | Knee-point voltage detector |
| CN106020307A (en) * | 2016-06-23 | 2016-10-12 | 电子科技大学 | Linear constant-current power supply with constant power consumption |
| CN111488029A (en) * | 2020-04-26 | 2020-08-04 | 重庆理工大学 | Long-channel MOS tube threshold voltage on-chip generation circuit |
-
2020
- 2020-09-21 CN CN202010995287.1A patent/CN112162590A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008016143A (en) * | 2006-07-07 | 2008-01-24 | Sanyo Electric Co Ltd | Subtraction circuit |
| CN103023323A (en) * | 2011-09-20 | 2013-04-03 | 万国半导体(开曼)股份有限公司 | Average inductive current type voltage control method and variable reference voltage generating device used by method |
| TW201547320A (en) * | 2014-06-11 | 2015-12-16 | Richtek Technology Corp | Light emitting device driver circuit and driving method of light emitting device circuit |
| CN105866517A (en) * | 2015-01-23 | 2016-08-17 | 联咏科技股份有限公司 | Knee-point voltage detector |
| CN105634449A (en) * | 2015-12-30 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Differential voltage absolute value circuit |
| CN105763047A (en) * | 2016-03-08 | 2016-07-13 | 中山大学 | Full wave inductance current sampling circuit |
| CN106020307A (en) * | 2016-06-23 | 2016-10-12 | 电子科技大学 | Linear constant-current power supply with constant power consumption |
| CN111488029A (en) * | 2020-04-26 | 2020-08-04 | 重庆理工大学 | Long-channel MOS tube threshold voltage on-chip generation circuit |
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