CN111812382B - DC-DC full wave inductive current sensor - Google Patents

DC-DC full wave inductive current sensor Download PDF

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CN111812382B
CN111812382B CN202010618884.2A CN202010618884A CN111812382B CN 111812382 B CN111812382 B CN 111812382B CN 202010618884 A CN202010618884 A CN 202010618884A CN 111812382 B CN111812382 B CN 111812382B
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mirror image
nmos tube
tube
electrode
drain electrode
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CN111812382A (en
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李斌
刘育洋
吴朝晖
郑彦祺
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South China University of Technology SCUT
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Abstract

The invention discloses a DC-DC full-wave inductive current sensor, which uses a PMOS mirror image module and an NMOS mirror image module to realize large-scale inductive current mirror image proportion by two-stage mirror image, and selectively processes a peak wave signal and a valley wave signal according to a P gate enabling signal, an N gate enabling signal and an inverted N gate enabling signal through an error amplifier, thereby outputting an error amplification signal which is fed back to a circuit to form a feedback loop, and reducing burrs of output mirror image current. Through setting up the two-stage mirror image, obtained the current mirror image proportion bigger than prior art, simultaneously through setting up error amplifier, improved the precision of mirror image current. The invention can be widely applied to the technical field of power management.

Description

DC-DC full wave inductive current sensor
Technical Field
The invention relates to the technical field of power management, in particular to a DC-DC full-wave inductive current sensor.
Background
Current mode DC-DC has many advantages over voltage mode and has been widely used in the field of switched inductor DC-DC, with the most widely used being inductor current mode. In order to realize the inductor current mode control, the inductor current needs to be proportionally sampled and input into a controller, and the conventional method samples the peak value, the valley value or the average value of the inductor current, so that the method not only limits the precise control of the inductor current, such as comparator control, but also is not suitable for the application needing to observe the inductor current in the whole period, such as single-inductor multi-output DC-DC.
The full-wave inductor current sensor samples inductor current in all time and outputs full-wave inductor current sampling signals with equal proportion and smaller amplitude. In the main method for realizing the full-wave inductive current sensor, the inductive current sensor based on the SenseFET utilizes the characteristic that high-side and low-side power tubes connected with an inductive common end VX are conducted in a full-period time-sharing mode, and current images of the high-side and low-side power tubes are combined in a time domain, so that the full-period image of the inductive current is formed, and then a full-wave inductive current sampling signal is output. The method has the advantages of low power consumption and high precision, but the current inductive current sensor based on the SenseFET has lower precision, and the precision is difficult to maintain along with the increase of the mirror ratio.
Disclosure of Invention
In view of the above, the present invention provides a DC-DC full-wave inductor current sensor to improve the inductor current mirror ratio and accuracy.
The technical scheme adopted by the invention is as follows:
a DC-DC full wave inductor current sensor comprising:
the PMOS mirror module is used for outputting a first mirror current according to the inductive current and the error amplification signal input by the inductive common end;
the NMOS mirror image module is used for outputting a second mirror image current according to the inductive current and the error amplification signal input by the inductive common terminal;
the enabling signal generating module is used for outputting an inverted P gate enabling signal according to the P gate enabling signal and outputting an inverted N gate enabling signal according to the N gate enabling signal;
the PMOS switch module is used for selecting a peak wave signal according to the P gate enable signal and the inverted P gate enable signal;
the NMOS switch module is used for selecting a valley wave signal according to the N gate enable signal and the inverted N gate enable signal;
the error amplification module is used for selectively processing the peak wave signal and the valley wave signal according to the P gate enable signal, the N gate enable signal and the reversed phase N gate enable signal and outputting an error amplification signal;
the PMOS mirror module and the NMOS mirror module are both provided with two stages of mirrors, and the first mirror current and the second mirror current jointly form output current.
Compared with the prior art, the invention obtains a larger current mirror ratio compared with the prior art by arranging two stages of mirrors, and improves the precision of mirror current by arranging the error amplifier.
Drawings
FIG. 1 is a circuit diagram of a DC-DC full wave inductor current sensor according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a peak-wave differential level conversion submodule of a DC-DC full-wave inductive current sensor according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a Gilbert amplifier sub-module of a DC-DC full-wave inductor current sensor according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a valley wave differential level conversion submodule of a DC-DC full wave inductor current sensor according to an embodiment of the present invention;
FIG. 5 is a waveform diagram of an output of an enable signal generating module of a DC-DC full-wave inductor current sensor according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of an enable signal generating module of a DC-DC full-wave inductor current sensor according to an embodiment of the present invention;
fig. 7 is a block diagram of an error amplification module of a DC-DC full-wave inductor current sensor according to an embodiment of the present invention.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a DC-DC full-wave inductor current sensor, including:
the PMOS mirror module is used for outputting a first mirror current according to the inductive current and the error amplification signal input by the inductive common terminal VX;
the NMOS mirror image module is used for outputting a second mirror image current according to the inductive current and the error amplification signal input by the inductive common terminal VX;
the enabling signal generating module is used for outputting an inverted P gate enabling signal according to the P gate enabling signal and outputting an inverted N gate enabling signal according to the N gate enabling signal;
the PMOS switch module is used for selecting a peak wave signal according to the P gate enable signal and the inverted P gate enable signal;
the NMOS switch module is used for selecting a valley wave signal according to the N gate enable signal and the inverted N gate enable signal;
the error amplification module is used for selectively processing the peak wave signal and the valley wave signal according to the P gate enable signal, the N gate enable signal and the reversed phase N gate enable signal and outputting an error amplification signal;
the PMOS mirror module and the NMOS mirror module are both provided with two stages of mirrors, and the first mirror current and the second mirror current jointly form output current.
Specifically, the embodiment of the invention realizes large-scale current mirror by arranging two-stage mirror, and the DC-DC full-wave inductance current sensor inputs a P gate enable signal VQPAnd N gate enable signal VQNThe output end outputs a full-wave inductor current sampling signal ILsenAnd a port inductor common terminal VX is an input/output port.
And the PMOS mirror module is used for generating mirror image or symmetry of current by using a PMOS tube.
And the NMOS mirror module is used for generating mirror image or symmetry of current by using an NMOS tube.
And the PMOS switch module is used for controlling the mode switching of peak wave signal sampling.
And the NMOS switch module is used for controlling the mode switching of the valley wave signal sampling.
And the enabling signal generating module is used for generating an enabling signal of the DC-DC full-wave inductance current sensor.
And the error amplification module is used for being connected into a closed loop in the full-wave current sensor to generate depth negative feedback.
Further as a preferred embodiment, referring to fig. 1, the PMOS mirror module includes a first mirror PMOS transistor MP1And a second mirror PMOS transistor MP2And a third mirror PMOS transistor MP3And a fourth mirror PMOS transistor MP4The fifth mirror PMOS transistor MP5And a sixth mirror PMOS transistor MP6And a seventh mirror PMOS transistor MP7；
The first mirror image PMOS tube MP1The source electrode is connected with a power supply, and the first mirror image PMOS tube MP1Drain electrode and inductance common terminal VX, first mirror image NMOS tube MN1Drain electrode of (1) and second mirror image NMOS transistor MN2The drain electrode of the first mirror PMOS transistor M is connectedP1And a P gate enable signal generation module VQPConnecting;
the second mirror image PMOS tube MP2The source electrode of the second mirror PMOS transistor M is connected with a power supplyP2Drain of and fourth mirror NMOS transistor MN4The drain electrode of the second mirror PMOS transistor M is connectedP2The grid of (2) is connected with the ground;
the third mirror PMOS tube MP3The source electrode of the PMOS transistor M is connected with a power supply, and the third mirror image PMOS transistor MP3Drain of and third mirror NMOS transistor MN3Drain electrode of the PMOS transistor S and a fourth switch PMOS transistor SP4The source electrode of the third mirror image PMOS tube M is connectedP3The grid of (2) is connected with the ground;
the fourth mirror PMOS tube MP4The source electrode of the second mirror image PMOS tube M is connected with a power supplyP4Drain electrode of the PMOS transistor M and a fourth mirror imageP4Grid and fifth mirror PMOS transistor MP5Source electrode and sixth mirror image PMOS transistor MP6The gate of (1) is connected;
the fifth mirror PMOS transistor MP5Source electrode and fourth mirror image PMOS transistor MP4The drain electrode of the fifth mirror PMOS transistor M is connected with the grid electrode of the fifth mirror PMOS transistor MP5Drain electrode of the PMOS transistor M and a fifth mirror image PMOS transistor MP5Grid and seventh mirror PMOS transistor MP7Gate of (1) and seventh mirror NMOS transistor MN7Is connected with the drain electrode of the transistor;
the sixth mirror PMOS tube MP6The source electrode of the PMOS transistor M is connected with a power supply, and the sixth mirror image PMOS transistor MP6Drain electrode of the PMOS transistor M and a seventh mirror image PMOS tube MP7The source electrode of the sixth mirror image PMOS tube M is connectedP6Grid and fourth mirror image PMOS transistor MP4The gate of (1) is connected;
the seventh mirror PMOS tube MP7Source electrode and sixth mirror image PMOS transistor MP6Is connected with the drain electrode of the seventh mirror PMOS tube MP7The drain electrode outputs a full-wave inductive current sampling signal ILsenAnd the seventh mirror PMOS transistor MP7Grid and fifth mirror image PMOS transistor MP5Grid and fifth mirror PMOS transistor MP5Drain electrode of (1) and seventh mirror NMOS transistor MN7Is connected with the drain electrode of the transistor;
the first mirror image PMOS tube MP1And a second mirror PMOS transistor MP2And a third mirror PMOS transistor MP3And a fourth mirror PMOS transistor MP4The fifth mirror PMOS transistor MP5And a sixth mirror PMOS transistor MP6And a seventh mirror PMOS transistor MP7The substrate poles are all connected with a power supply;
the NMOS mirror image module comprises a first mirror image NMOS tube MN1A second mirror NMOS transistor MN2And a third mirror NMOS transistor MN3And the fourth mirror NMOS transistor MN4And the fifth mirror NMOS transistor MN5And a sixth mirror NMOS transistor MN6And a seventh mirror NMOS transistor MN7；
The first mirror NMOS tube MN1The source of the first mirror NMOS transistor M is connected with the groundN1Drain electrode and inductance common terminal VX, first mirror image PMOS tube MP1Drain electrode of (1) and second mirror image NMOS transistor MN2The drain electrode of the first mirror NMOS transistor M is connected with the drain electrode of the second mirror NMOS transistorN1Grid and N grid enable signal generation module VQNConnecting;
the second mirror NMOS tube MN2Source and sixth mirror NMOS transistor MN6Source electrode of the NMOS transistor S, and a third switch NMOS transistor SN3Source electrode fourth switch NMOS tube SN4Is connected with the drain electrode of the second mirror image NMOS tube MN2Drain electrode and inductance common terminal VX, first mirror image PMOS tube MP1Drain electrode of (1) and first mirror NMOS transistor MN1Is connected with the drain electrode of the second mirror image NMOS tube MN2Grid and N grid enable signal generation module VQNConnecting;
the third mirror NMOS tube MN3Source electrode of and the fifth mirror NMOS transistor MN5The drain electrode of the third mirror NMOS transistor M is connected with the grid electrode of the third mirror NMOS transistor MN3Drain electrode of the PMOS transistor M and a third mirror imageP3Drain electrode of the PMOS transistor S and a fourth switch PMOS transistor SP4The source electrode of the third mirror NMOS tube M is connectedN3Grid and output end V of error amplification moduleoeaAnd a fourth mirror NMOS transistor MN4The gate of (1) is connected;
the fourth mirror NMOS tube MN4Source and sixth mirror NMOS transistor MN6The drain electrode of the fourth mirror NMOS transistor M is connected with the grid electrode of the fourth mirror NMOS transistor MN4Drain electrode of the PMOS transistor M and the second mirror image PMOS transistor MP2Is connected with the drain electrode of the fourth mirror NMOS tube MN4Grid and output end V of error amplification moduleoeaAnd a third mirror NMOS transistor MN3The gate of (1) is connected;
the fifth mirror NMOS transistor MN5The source of the NMOS transistor M is connected with the ground, and the fifth mirror image NMOS transistor MN5Drain of and the fifth mirror NMOS transistor MN5Grid and third mirror NMOS transistor MN3Source electrode of (1) and seventh mirror NMOS transistor MN7The gate of (1) is connected;
the sixth mirror NMOS tube MN6Source and second mirror NMOS transistor MN2Source electrode of the NMOS transistor S, and a third switch NMOS transistor SN3Source electrode and fourth switch NMOS transistor SN4Is connected with the drain electrode of the sixth mirror NMOS tube MN6Drain of and the sixth mirror NMOS transistor MN6Grid and fourth mirror image NMOS transistor MN4Is connected to the source of (a);
the seventh mirror NMOS transistor MN7The source of the NMOS transistor is connected with the ground, and the seventh mirror image NMOS transistor MN7Drain electrode of the PMOS transistor M and a fifth mirror image PMOS transistor MP5The drain electrode of the seventh mirror NMOS transistor M is connected with the grid electrode of the seventh mirror NMOS transistor MN7Grid and fifth mirror NMOS transistor MN5The drain electrode of (1) is connected with the grid electrode;
the first mirror NMOS tube MN1A second mirror NMOS transistor MN2And a third mirror NMOS transistor MN3And the fourth mirror NMOS transistor MN4And the fifth mirror NMOS transistor MN5And a sixth mirror NMOS transistor MN6And a seventh mirror NMOS transistor MN7The substrate poles of the two-way switch are all connected with the ground;
the PMOS switch module comprises a first switch PMOS tube SP1A second switch PMOS transistor SP2And a third switch PMOS tube SP3And a fourth switch PMOS transistor SP4；
The first switch PMOS tube SP1The source electrode of the first switch PMOS tube S is connected with the inductance common end VXP1Drain electrode of the error amplifying module and peak wave error signal inverting input end V of the error amplifying moduleHMAnd a second switch PMOS transistor SP2The drain electrode of the first switch PMOS tube S is connectedP1And a P gate enable signal generation module VQPConnecting;
the second switch PMOS tube SP2The source electrode of the second switch PMOS tube S is connected with a power supplyP2Drain electrode of the error amplifying module and peak wave error signal inverting input end V of the error amplifying moduleHMAnd a first switch PMOS transistor SP1The drain electrode of the second switch PMOS tube S is connectedP2And an inverted P-gate enable signal terminal of the enable signal generation module
Figure BDA0002562349620000051
Connecting;
the third switch PMOS tube SP3The source electrode of the first switch PMOS tube S is connected with a power supply, and the third switch PMOS tube SP3Drain electrode of the error amplifying module and peak wave error signal in-phase input end V of the error amplifying moduleHPAnd a fourth switch PMOS transistor SP4The drain electrode of the third switch PMOS tube S is connectedP3And an inverted P-gate enable signal terminal of the enable signal generation module
Figure BDA0002562349620000052
Connecting;
the fourth switch PMOS tube SP4Source electrode and third mirror image PMOS transistor MP3Drain electrode of (1) and third mirror NMOS transistor MN3The drain electrode of the fourth switch PMOS tube S is connectedP4Drain electrode of the error amplifying module and peak wave error signal in-phase input end V of the error amplifying moduleHPAnd a third switch PMOS tube SP3The drain electrode of the fourth switch PMOS tube S is connectedP4And a P gate enable signal generation module VQPConnecting;
the first switch PMOS tube SP1A second switch PMOS transistor SP2And a third switch PMOS tube SP3And a fourth switch PMOS transistor SP4The substrate poles are all connected with a power supply;
the NMOS switch module comprises a first switch NMOS tube SN1A second switch NMOS transistor SN2And a third switch NMOS tube SN3And a fourth switch NMOS tube SN4；
The first switch NMOS tube SN1The source of the first switch NMOS tube S is connected with the groundN1Drain electrode of the error amplifying module and valley wave error signal in-phase input end V of the error amplifying moduleLPConnected, the first switch NMOS tube SN1The grid is connected with a power supply;
the second switch NMOS tube SN2The source of the second switch NMOS tube S is connected with the groundN2Drain electrode of the error signal amplifying module and valley wave error signal inverting input end V of the error signal amplifying moduleLMAnd a third switch NMOS transistor SN3The drain electrode of the second switch NMOS tube S is connectedN2And the inverted N-gate enable signal terminal of the enable signal generation module
Figure BDA0002562349620000061
Connecting;
the third switch NMOS tube SN3Source and fourth switch NMOS transistor SN4Drain electrode of (1), sixth mirror NMOS tube MN6Source electrode of and second mirror image NMOS transistor MN2The source electrode of the third switch NMOS tube S is connectedN3Drain electrode of the error amplifying module and valley wave error signal inverting input end V of the error amplifying moduleLMAnd a second switch NMOS transistor SN2The drain electrode of the third switch NMOS tube S is connectedN3Grid and N grid enable signal generation module VQNConnecting;
the fourth switch NMOS tube SN4The source electrode of the fourth switch NMOS tube S is connected with the groundN4Drain of the NMOS transistor S and the third switch NMOS transistor SN3Source electrode of and sixth mirror NMOS transistor MN6Source electrode of and second mirror image NMOS transistor MN2Source electrode of the fourth switch NMOS tube SN4And the inverted N-gate enable signal terminal of the enable signal generation module
Figure BDA0002562349620000062
Connecting;
the first switch NMOS tube SN1A second switchNMOS tube SN2And a third switch NMOS tube SN3And a fourth switch NMOS tube SN4All of the substrate poles of (a) are connected to ground.
Specifically, the first mirror PMOS transistor MP1A high side power tube that is DC-DC; second mirror image PMOS tube MP2Is a first mirror PMOS transistor MP1And a first mirror PMOS transistor MP1Has a proportional relationship of a few thousandths, the proportional relationship of 1/2000 is preferably used in the present embodiment; third mirror image PMOS tube MP3Is also a first mirror image PMOS transistor MP1And a first mirror PMOS transistor MP1Has the same width as the second mirror image PMOS transistor MP2And a first mirror PMOS transistor MP1The widths of the two plates are the same in proportional relation; sixth mirror PMOS transistor MP6Is a fourth mirror image PMOS transistor MP4Mirror image tube of, and fourth mirror image PMOS tube MP4Has a proportional relation of a few tenths, the proportional relation of 1/25 is preferably used in the present embodiment; seventh mirror PMOS transistor MP7Is a fifth mirror PMOS transistor MP5Mirror image tube of, and a fifth mirror image PMOS tube MP5Has the same width as the sixth mirror image PMOS transistor MP6And a fourth mirror image PMOS transistor MP4The widths of the two plates are the same in proportional relation; first mirror NMOS transistor MN1Is a low-side power tube of DC-DC, a second mirror image NMOS tube MN2Is a first mirror NMOS transistor MN1And a first mirror NMOS transistor MN1Has the same width as the second mirror image PMOS transistor MP2And a first mirror PMOS transistor MP1The widths of the two plates are the same in proportional relation; fourth mirror NMOS transistor MN4Is a third mirror NMOS transistor MN3And a third mirror NMOS transistor MN3Has a proportional relationship of 1/1; sixth mirror NMOS transistor MN6Is a fifth mirror NMOS transistor MN5Mirror image tube of, and a fifth mirror image NMOS tube MN5Has a proportional relationship of 1/1; seventh mirror NMOS transistor MN7Is also a fifth mirror NMOS transistor MN5Mirror image tube of, and a fifth mirror image NMOS tube MN5Has a proportional relationship of 1/1.
The preferred scheme of this embodiment is to use the first switch PMOS transistor SP1Second, secondSwitch PMOS tube SP2And a third switch PMOS tube SP3And a fourth switch PMOS transistor SP4The two parts are made into the same size and are in mirror symmetry with each other; a first switch NMOS tube SN1A second switch NMOS transistor SN2And a third switch NMOS transistor SN3Are made to the same size and are mirror images of each other.
Further as a preferred embodiment, referring to fig. 5 and 6, the enable signal generating module includes:
first inverter submodule IN1The inverted P gate enable signal is output according to the P gate enable signal;
second inverter submodule IN2The inverted N-gate enable signal is output according to the N-gate enable signal;
the inverted P-gate enable signal has a slight delay relative to the P-gate enable signal, and the inverted N-gate enable signal has a slight delay relative to the N-gate enable signal.
Specifically, dead time exists between the high-side power tube and the low-side power tube, and the gate signal feed-through of the switching tube enables the output full-wave inductor current sampling signal to contain a large amount of burrs, and the huge burrs can cause false triggering and even imbalance of the controller. In the embodiment of the invention, the starting time of the conduction process of the high-side power tube and the low-side power tube is covered by the tiny time delay generated by the inverter, so that the glitch of the output signal is reduced.
The P gate enable signal and the N gate enable signal come from the output of the pre-driver, contain dead time, and need to directly control the high-side power tube M respectivelyP1And a low side power transistor MN1(ii) a The P gate enable signal and the N gate enable signal pass through a first inverter IN1And a second inverter IN2Generating inverted P-gate enable signal and inverted N-gate enable signal with small delay for reducing low-side power transistor MN1Turn off to high side power transistor MP1Full-wave inductive current sampling signal I in conduction processLsenThe burr of (1).
Further as a preferred embodiment, referring to fig. 7, the error amplification module includes:
the peak wave differential level conversion submodule is used for outputting a peak wave differential signal according to the peak wave signal;
the valley wave differential level converter module is used for outputting a valley wave differential signal according to the valley wave signal;
and the Gilbert amplifying submodule is used for selectively processing the peak wave differential signal and the valley wave differential signal according to the P gate enable signal, the N gate enable signal and the inverted N gate enable signal and outputting an error amplifying signal.
Specifically, in the prior art, due to insufficient suppression of common-mode signals such as high-side and low-side power tube switching signals, common-mode bias, enable signals and the like, the glitch of the full-wave inductor current sampling signal is increased. In the embodiment, the error amplification signal generated by the error amplification module is used for suppressing common-mode signals such as switching signals, common-mode bias, enable signals and the like of the high-side and low-side power tubes, and the glitch of an output signal is reduced.
The error amplification module has four error signal inputs, including: peak wave error signal in-phase input end VHPPeak wave error signal inverting input end VHMValley wave error signal in-phase input end VLPAnd valley wave error signal inverting input end VLMThe error amplifier has three enable signal inputs, including: a P-gate enable signal input terminal, an N-gate enable signal input terminal, an inverted N-gate enable signal input terminal, and an output terminal Voea。
The signal transmission relationship of each unit of the error amplification module is as follows: peak wave differential level conversion submodule input peak wave error signal in-phase input end VHPPeak wave error signal inverting input end VHMOutput peak wave error signal in-phase output end VP+And peak wave error signal inverting output end VP-(ii) a Input valley wave error signal in-phase input end V of valley wave differential level converter moduleLPAnd valley wave error signal inverting input end VLMOutput valley wave error signal in-phase output end VN+And valley wave error signal inverting output end VN-(ii) a Then peak wave error signal in-phase output end VP+Peak wave error signal inverting output end VP-Valley wave errorSignal in-phase output terminal VN+And valley wave error signal inverting output end VN-Inputting a Gilbert amplifying submodule; the Gilbert amplification submodule generates an output signal V of the error amplifier according to the control of the input enable signal P grid enable signal, the input enable signal N grid enable signal and the inverted input enable signal N grid enable signaloea。
And the peak wave differential level conversion submodule is used for calculating the difference of the input peak wave signals, converting the level and outputting peak wave differential signals.
And the valley wave differential level conversion submodule is used for calculating the difference of the input valley wave signals, converting the level and outputting the valley wave differential signals.
And the Gilbert amplifying sub-module is used for differencing and amplifying the input signal and selectively outputting the input signal according to the enabling signal.
Further as a preferred embodiment, the peak wave difference level conversion module includes:
the first PMOS mirror image unit is used for outputting a peak wave differential signal according to the peak wave signal and matched with the first NMOS mirror image unit;
the first NMOS mirror image unit is used for outputting a peak wave differential signal in cooperation with the first PMOS mirror image unit;
and the first bias current unit is used for biasing the first PMOS mirror image unit.
Specifically, the input end of the peak wave differential level conversion submodule is a peak wave error signal in-phase input end VHPAnd peak wave error signal inverting input terminal VHMThe output end is a peak wave error signal in-phase output end VP+And peak wave error signal inverting output end VP-When realizing level conversion, still realize:
VP+-VP-＝AP(VHP-VHM)
in the formula, APFor the gain of the peak-wave differential level conversion unit, in this embodiment, A is takenPComprises the following steps:
Figure BDA0002562349620000081
in the formula gmp9，10Is a ninth mirror image PMOS tube MP9Or tenth mirror image PMOS transistor MP10Transconductance of gmn8，10Is an eighth mirror NMOS transistor MN8Or the tenth mirror NMOS transistor MN10Transconductance of gmn9，11Is a ninth mirror NMOS transistor MN9Or eleventh mirror NMOS transistor MN11Transconductance of (1).
And the first PMOS mirror unit is used for generating mirror image or symmetry of current by using a PMOS tube.
And the first NMOS mirror image unit is used for generating mirror image or symmetry of current by using an NMOS tube.
And the first bias current unit is used for biasing the connected PMOS tubes.
Further as a preferred embodiment, referring to fig. 2, the first PMOS mirror unit includes an eighth mirror PMOS transistor MP8And a ninth mirror PMOS transistor MP9And a tenth mirror image PMOS transistor MP10And eleventh mirror image PMOS transistor MP11；
The eighth mirror PMOS transistor MP8Source electrode and eighth mirror image PMOS transistor MP8Substrate pole, peak wave error signal inverting input end VHMAnd a tenth mirror image PMOS transistor MP10Source electrode and tenth mirror image PMOS transistor MP10Substrate pole of the eighth mirror PMOS transistor MP8Drain electrode of the PMOS transistor M and the eighth mirror image PMOS transistor MP8Grid and ninth mirror image PMOS transistor MP9And a first bias current source Ibias1The input ends of the two-way valve are connected;
the ninth mirror PMOS tube MP9Source electrode and ninth mirror image PMOS transistor MP9Substrate pole, peak wave error signal in-phase input end VHPEleventh mirror PMOS transistor MP11Source electrode of (1) and eleventh mirror image PMOS transistor MP11Substrate pole of the ninth mirror PMOS transistor MP9The drain electrode of the transistor is connected with the peak wave error signal in-phase output end VP+And the eighth mirror NMOS transistor MN8The drain electrode of the second mirror image PMOS transistor M is connected with the grid electrode of the first mirror image PMOS transistor MP9Grid and eighth mirror image PMOS transistor MP8Grid and eighth mirror image PMOS transistor MP8And a first biasCurrent source Ibias1The input ends of the two-way valve are connected;
the tenth mirror PMOS transistor MP10Source and tenth mirror PMOS transistor MP10Substrate pole, peak wave error signal inverting input end VHMEighth mirror PMOS transistor MP8Source electrode and eighth mirror image PMOS transistor MP8Substrate pole connection of the tenth mirror image PMOS transistor MP10Drain electrode of the transistor and peak wave error signal inverting output end VP-And the tenth mirror NMOS transistor MN10Drain of (1) and tenth mirror NMOS transistor MN10The grid electrode of the PMOS transistor M is connected, and the tenth mirror image PMOS transistor MP10Grid of the PMOS transistor and the eleventh mirror image PMOS transistor MP11Grid and eleventh mirror image PMOS transistor MP11And a second bias current source Ibias2The input ends of the two-way valve are connected;
the eleventh mirror image PMOS tube MP11Source electrode of and eleventh mirror image PMOS transistor MP11Substrate pole, peak wave error signal in-phase input end VHPAnd a ninth mirror PMOS transistor MP9Source electrode and ninth mirror image PMOS transistor MP9The substrate pole of the eleventh mirror image PMOS transistor M is connectedP11Drain of the PMOS transistor M and the eleventh mirror image PMOS transistor MP11Grid and tenth mirror image PMOS transistor MP10And a second bias current source Ibias2The input ends of the two-way valve are connected;
the first NMOS mirror image unit comprises an eighth mirror image NMOS transistor MN8And the ninth mirror NMOS transistor MN9And the tenth mirror NMOS transistor MN10And an eleventh mirror NMOS transistor MN11；
The eighth mirror NMOS transistor MN8Source and ninth mirror NMOS transistor MN9Drain electrode of (1) and ninth mirror NMOS transistor MN9Is connected with the grid electrode of the eighth mirror image NMOS tube MN8Drain of and eighth mirror NMOS transistor MN8Grid, peak wave error signal in-phase output end VP+And a ninth mirror image PMOS transistor MP9Is connected with the drain electrode of the transistor;
the ninth mirror NMOS tube MN9The source of the NMOS transistor is connected with the ground, and the ninth mirror image NMOS transistor MN9Drain of and ninth mirror NMOS transistor MN9Gate of (1) and eighth mirror image NMOS pipe MN8Is connected to the source of (a);
the tenth mirror NMOS transistor MN10Source of and eleventh mirror image NMOS transistor MN11Drain of (1) and eleventh mirror NMOS transistor MN11Is connected with the grid of the NMOS transistor M of the tenth mirror imageN10Drain of and tenth mirror NMOS transistor MN10Grid, peak wave error signal inverting output terminal VP-And a tenth mirror image PMOS transistor MP10Is connected with the drain electrode of the transistor;
the eleventh mirror NMOS tube MN11The source of the eleventh mirror image NMOS transistor M is connected with the groundN11Drain of and eleventh mirror NMOS transistor MN11Gate of (1) and tenth mirror NMOS transistor MN10Is connected to the source of (a);
the eighth mirror NMOS transistor MN8And the ninth mirror NMOS transistor MN9And the tenth mirror NMOS transistor MN10And an eleventh mirror NMOS transistor MN11The substrate poles of the two-way switch are all connected with the ground;
the first bias current unit comprises a first bias current source Ibias1And a second bias current source Ibias2The first bias current source Ibias1Input end and eighth mirror image PMOS tube MP8Drain electrode of (1), eighth mirror image PMOS tube MP8Grid and ninth mirror image PMOS transistor MP9The first bias current source Ibias1The output end of the voltage regulator is connected with the ground;
the second bias current source Ibias2Input end of the PMOS transistor M and the eleventh mirror imageP11Drain electrode of the PMOS transistor M and eleventh mirror imageP11Grid and tenth mirror image PMOS transistor MP10The second bias current source Ibias2The output terminal of which is grounded.
Specifically, the ninth mirror PMOS transistor MP9Is the eighth mirror image PMOS transistor MP8And an eighth mirror PMOS transistor MP8Has a proportional relationship of 1/1; tenth mirror image PMOS tube MP10Also eighth mirror image PMOS transistor MP8And an eighth mirror PMOS transistor MP8Has a proportional relationship of 1/1; eleventh mirror PMOS transistor MP11Is also thatEighth mirror PMOS transistor MP8And an eighth mirror PMOS transistor MP8Has a proportional relationship of 1/1.
Tenth mirror NMOS transistor MN10Is an eighth mirror NMOS transistor MN8And an eighth mirror NMOS transistor MN8Has a proportional relationship of 1/1; eleventh mirror NMOS transistor MN11Is a ninth mirror NMOS transistor MN9And a ninth mirror NMOS transistor MN9Has a proportional relationship of 1/1.
The bias current of the second bias current source is equal to that of the first bias current source.
Further as a preferred embodiment, the gilbert amplifier sub-module comprises:
the second PMOS mirror image unit is used for outputting an error amplification signal in cooperation with the second NMOS mirror image unit;
the second NMOS mirror image unit is used for being matched with the second PMOS mirror image unit and outputting an error amplification signal;
the first NMOS switch unit is used for selectively processing the peak wave differential signal and the valley wave differential signal according to the P gate enabling signal and the inverted N gate enabling signal and controlling the enabling of the Gilbert unit;
the sampling and holding unit is used for keeping the output voltage unchanged during the period that the Gilbert amplification sub-module is not enabled and compensating a closed loop accessed by the error amplification module during the period that the Gilbert amplification sub-module is enabled;
and the bias voltage unit is used for biasing the Gilbert amplification sub-module.
Specifically, the control process of the gilbert amplifier sub-module includes: amplifying only the signal (V) when the P-gate enable signal is lowP+-VP-) For generating a peak wave error; amplifying only the signal (V) when the N gate enable signal is highN+-VN-) For generating a valley wave error; when the P gate enable signal is high and the N gate enable signal is low, the Gilbert unit is powered off without interruption for eliminating VoeaThe glitch on the signal is specifically as follows:
Figure BDA0002562349620000101
when the temperature of the water is higher than the set temperature,
Figure BDA0002562349620000102
and the second PMOS mirror unit is used for generating mirror image or symmetry of current by using a PMOS tube.
And the first NMOS switch unit is used for controlling the enabling of the Gilbert amplifying submodule.
The sampling and holding unit is used for keeping the output voltage unchanged during the period that the Gilbert amplification submodule is not enabled and compensating a closed loop accessed by the error amplifier during the enabled period; a sample-and-hold unit
Figure BDA0002562349620000111
While maintaining VoeaThe twelfth PMOS mirror image tube M of the constant and Gilbert amplifier sub-moduleP12And thirteen mirror image PMOS tube MP13Working in a saturation region; the sample and hold unit has the effect of compensating for the closed loop phase in the DC-DC full wave inductor current sensor.
A bias voltage unit for using a bias voltage source VbiasBiasing the fourteenth mirror NMOS transistor MN14。
Further as a preferred implementation, referring to fig. 3, the second PMOS mirror unit includes a twelfth mirror PMOS transistor MP12And thirteenth mirror PMOS transistor MP13；
The twelfth mirror image PMOS tube MP12The source electrode of the PMOS transistor M is connected with a power supply, and the twelfth mirror image PMOS transistor MP12Drain electrode of the PMOS transistor M and a twelfth mirror imageP12Grid and thirteenth mirror image PMOS transistor MP13Grid and thirteenth mirror NMOS transistor MN13Drain of and fifteenth mirror NMOS transistor MN15Is connected with the drain electrode of the transistor;
the thirteenth mirror PMOS tube MP13The source electrode of the PMOS transistor M is connected with a power supply, and the thirteenth mirror image PMOS transistor MP13Drain of and twelfth mirror NMOS transistor MN12Drain electrode of (1), sixteenth mirror NMOS tube MN16Drain electrode seventh switch NMOSPipe SN7Drain electrode of and a fifth switching PMOS tube SP5Source electrode of the thirteenth mirror PMOS transistor MP13Grid and twelfth mirror image NMOS tube MN12Grid and twelfth mirror image NMOS tube MN12Drain electrode of (1), thirteenth mirror image NMOS tube MN13Drain of and fifteenth mirror NMOS transistor MN15Is connected with the drain electrode of the transistor;
the twelfth mirror image PMOS tube MP12And thirteenth mirror PMOS transistor MP13The substrate poles are all connected with a power supply;
the second NMOS mirror image unit comprises a twelfth mirror image NMOS tube MN12And a thirteenth mirror NMOS transistor MN13And a fourteenth mirror NMOS transistor MN14And a fifteenth mirror NMOS transistor MN15And sixteenth mirror NMOS transistor MN16；
The twelfth mirror NMOS tube MN12Source and fifth switch NMOS transistor SN5Drain electrode of (1) and thirteenth mirror NMOS transistor MN13Source electrode of (1), the twelfth mirror NMOS tube MN12Drain of and sixteenth mirror NMOS transistor MN16Drain electrode of (1), thirteenth mirror image PMOS tube MP13Drain electrode of (1), seventh switch NMOS tube SN7Drain electrode of and a fifth switching PMOS tube SP5Source electrode of (1), the twelfth mirror NMOS tube MN12Grid and peak wave error signal inverting output terminal VP-Connecting;
the thirteenth mirror NMOS tube MN13Source and fifth switch NMOS transistor SN5Drain of (1) and twelfth mirror NMOS transistor MN12Source electrode of (1), the thirteenth mirror NMOS tube MN13Drain of and fifteenth mirror NMOS transistor MN15Drain electrode of the PMOS transistor M and a twelfth mirror imageP12Drain electrode of (1) and twelfth mirror image PMOS transistor MP12Is connected with the grid of the NMOS tube M of the thirteenth mirror imageN13Grid and peak wave error signal in-phase output end VP+Connecting;
the fourteenth mirror NMOS transistor MN14The source of the fourth mirror NMOS transistor M is connected with the groundN14Drain of and the fifth switch NMOS transistor SN5Source electrode and sixth switch NMOS tubeSN6Source electrode of (1) is connected, the fourteenth mirror NMOS tube MN14Gate of and bias voltage source VbiasConnecting;
the fifteenth mirror NMOS tube MN15Source and sixteenth mirror NMOS transistor MN16Source electrode of and the sixth switching NMOS transistor SN6The fifteenth mirror NMOS transistor MN15Drain of the NMOS transistor M and the thirteenth mirror image NMOS transistor MN13Drain electrode of the PMOS transistor M and a twelfth mirror imageP12Drain electrode of (1) and twelfth mirror image PMOS transistor MP12A gate connected to the fifteenth mirror NMOS transistor MN15Grid and valley wave error signal in-phase output end VN+Connecting;
the sixteenth mirror NMOS tube MN16Source and fifteenth mirror NMOS transistor MN15Source electrode of and the sixth switching NMOS transistor SN6Is connected with the drain electrode of the sixteenth mirror NMOS tube MN16Drain electrode twelfth mirror image NMOS tube MN12Drain electrode of (1), thirteenth mirror image PMOS tube MP13Drain electrode of (1), seventh switch NMOS tube SN7Drain electrode of and a fifth switching PMOS tube SP5Source electrode of the NMOS transistor M of the sixteenth mirror imageN16Grid and valley wave error signal inverting output end VN-Connecting;
the twelfth mirror NMOS tube MN12And a thirteenth mirror NMOS transistor MN13And a fourteenth mirror NMOS transistor MN14And a fifteenth mirror NMOS transistor MN15And sixteenth mirror NMOS transistor MN16The substrate poles of the two-way switch are all connected with the ground;
the first NMOS switch unit comprises a fifth switch NMOS tube SN5And a sixth switch NMOS tube SN6And a seventh switch NMOS transistor SN7；
The fifth switch NMOS tube SN5Source and the sixth switch NMOS transistor SN6Source and fourteenth mirror NMOS transistor MN14Is connected with the drain electrode of the fifth switch NMOS tube SN5Drain of and twelfth mirror NMOS transistor MN12Source electrode of (1) and thirteenth mirror NMOS transistor MN13The source electrode of the fifth switch NMOS tube S is connectedN5Gate and enable signal generation moduleInverted N-gate enable signal terminal of block
Figure BDA0002562349620000121
Connecting;
the sixth switch NMOS tube SN6Source and fifth switch NMOS transistor SN5Source and fourteenth mirror NMOS transistor MN14Is connected with the drain electrode of the sixth switch NMOS tube SN6Drain of and fifteenth mirror NMOS transistor MN15Source electrode of and sixteenth mirror image NMOS transistor MN16The source electrode of the sixth switch NMOS tube S is connectedN6Gate and module V ofQPConnecting;
the seventh switch NMOS tube SN7Source and output end V of error amplification moduleoeaThe fifth switch PMOS tube SP5Drain electrode of (1) and sample-and-hold capacitor CSIs connected with the seventh switch NMOS tube SN7Drain of (1) and thirteenth mirror PMOS transistor MP13Drain electrode of (1), twelfth mirror image NMOS tube MN12Drain electrode of (1) and sixteenth mirror NMOS transistor MN16Is connected with the drain electrode of the sixth switch NMOS tube SN6Grid and N grid enable signal generation module VQNConnecting;
the fifth switch NMOS tube SN5And a sixth switch NMOS tube SN6And a seventh switch NMOS transistor SN7The substrate poles of the two-way switch are all connected with the ground;
the sample-and-hold unit comprises a sample-and-hold capacitor CSAnd a fifth switch PMOS transistor SP5；
The fifth switch PMOS tube SP5Source and seventh switch NMOS transistor SN7Drain electrode of (1), thirteenth mirror image PMOS tube MP13Drain electrode of (1), twelfth mirror image NMOS tube MN12Drain electrode of (1) and sixteenth mirror NMOS transistor MN16Is connected with the drain electrode of the fifth switch PMOS tube SP5Drain of and a seventh switch NMOS transistor SN7Source and sample-and-hold capacitor CSIs connected with the fifth switch PMOS tube SP5And a P gate enable signal generation module VQPConnecting;
the sample-and-hold capacitor CSOne end of the NMOS tube S is connected with the seventh switch NMOS tube SN7Source electrode of and fifth switch PMOS tube SP5The drain electrode of the first transistor is connected, and the other end of the first transistor is grounded;
the bias voltage unit comprises a bias voltage source Vbias。
Specifically, the thirteenth mirror PMOS transistor MP13Is a twelfth mirror image PMOS transistor MP12And a twelfth mirror PMOS transistor MP12Has a proportional relationship of 1/1; thirteenth mirror NMOS tube MN12Is a twelfth mirror image NMOS transistor MN12And a twelfth mirror NMOS transistor MN12Has a proportional relationship of 1/1; fifteenth mirror NMOS transistor MN15NMOS transistor M which is also the twelfth mirror imageN12And a twelfth mirror NMOS transistor MN12Has a proportional relationship of 1/1; sixteenth mirror image NMOS tube MN16NMOS transistor M which is also the twelfth mirror imageN12And a twelfth mirror NMOS transistor MN12Has a proportional relationship of 1/1.
The preferred scheme of this embodiment is to use the NMOS transistor S of the fifth switchN5And a sixth switching NMOS transistor SN6Are made to the same size and are mirror images of each other.
Further preferably, the valley wave difference level conversion module includes:
the third PMOS mirror image unit is used for outputting a valley wave differential signal according to the valley wave signal and by matching with the third NMOS mirror image unit;
the third NMOS mirror image unit is used for outputting a valley wave differential signal according to the valley wave signal and by matching with the third PMOS mirror image unit;
and the second bias current unit is used for biasing the third NMOS mirror image unit.
Specifically, the input end of the valley wave differential level conversion unit is a valley wave error signal in-phase input end VLPAnd valley wave error signal inverting input end VLMThe output end is a valley wave error signal in-phase output end VN+And valley wave error signal inverting output end VN-When realizing level conversion, still realize:
VN+-VN-＝AN(VLP-VLM)
in the formula, ANIn the present embodiment, A is taken as the gain of the valley-wave differential level conversion unitNComprises the following steps:
Figure BDA0002562349620000131
in the formula, gmn18，19Is an eighteenth mirror image NMOS tube MN18Or nineteenth mirror NMOS transistor MN19Transconductance of gmp14，16Is a fourteenth mirror PMOS transistor MP14Or sixteenth mirror image PMOS tube MP16Transconductance of gmp15，17Is a fifteenth mirror PMOS transistor MP15Or seventeenth mirror PMOS transistor MP17Transconductance of (1).
And the third PMOS mirror unit is used for generating mirror image or symmetry of current by using a PMOS tube.
And the third NMOS mirror image unit is used for generating mirror image or symmetry of current by using an NMOS tube.
And the second bias current unit is used for biasing the connected NMOS tubes.
Further as a preferred implementation, referring to fig. 4, the third PMOS mirror unit includes a fourteenth mirror PMOS transistor MP14Fifteenth mirror PMOS transistor MP15Sixteenth mirror image PMOS tube MP16And seventeenth mirror PMOS transistor MP17；
The fourteenth mirror PMOS transistor MP14The source electrode of the PMOS transistor M is connected with a power supply, and the fourteenth mirror image PMOS transistor MP14Drain of the PMOS transistor M and the fourteenth mirror image PMOS transistor MP14Grid and fifteenth mirror image PMOS transistor MP15Is connected to the source of (a);
the fifteenth mirror PMOS transistor MP15Source and fourteenth mirror PMOS transistor MP14Drain electrode of (1) and fourteenth mirror image PMOS tube MP14The gate of the PMOS transistor M is connected with the fifteenth mirror image PMOS transistor MP15Drain of the PMOS transistor M and a fifteenth mirror image PMOS transistor MP15Grid and valley wave error signal inverting output end VN-And eighteenth mirror NMOS transistorMN18Is connected with the drain electrode of the transistor;
the sixteenth mirror image PMOS tube MP16The source electrode of the PMOS transistor is connected with a power supply, and the sixteenth mirror image PMOS transistor MP16Drain electrode of the PMOS transistor M and a sixteenth mirror imageP16Grid and seventeenth mirror image PMOS transistor MP17Is connected to the source of (a);
the seventeenth mirror PMOS tube MP17Source electrode and sixteenth mirror image PMOS transistor MP16Drain electrode of (1) and sixteenth mirror image PMOS transistor MP16Is connected with the grid electrode of the seventeenth mirror image PMOS tube MP17Drain electrode of the PMOS transistor M and a seventeenth mirror imageP17Grid and valley wave error signal in-phase output end VN+And nineteenth mirror NMOS transistor MN19Is connected with the drain electrode of the transistor;
the fourteenth mirror PMOS transistor MP14Fifteenth mirror PMOS transistor MP15Sixteenth mirror image PMOS tube MP16And seventeenth mirror PMOS transistor MP17The substrate poles are all connected with a power supply;
the third NMOS mirror image unit comprises a seventeenth mirror image NMOS transistor MN17Eighteenth mirror NMOS transistor MN18Nineteenth mirror image NMOS tube MN19And twentieth mirror NMOS transistor MN20；
The seventeenth mirror NMOS transistor MN17Source and valley wave error signal in-phase input end VLPAnd nineteenth mirror NMOS transistor MN19Source electrode of the seventeenth mirror NMOS transistor MN17Drain electrode of (1) and seventeenth mirror NMOS transistor MN17Gate of (1), third bias current source Ibias3Output terminal of (1) and eighteenth mirror NMOS transistor MN18The gate of (1) is connected;
the eighteenth mirror NMOS tube MN18Source and valley wave error signal inverting input terminal VLMAnd twentieth mirror NMOS transistor MN20Source electrode of (1) is connected, the eighteenth mirror image NMOS tube MN18Drain and valley wave error signal inverting output terminal VN-Fifteenth mirror PMOS transistor MP15Drain electrode of (1) and fifteenth mirror image PMOS transistor MP15Drain electrode grid electrode of the NMOS transistor M is connected, and the eighteenth mirror image NMOS transistor MN18Gate and tenth ofSeven mirror image NMOS tube MN17Grid and seventeenth mirror NMOS transistor MN17And a third bias current source Ibias3The output ends of the two-way valve are connected;
the nineteenth mirror NMOS transistor MN19Source and valley wave error signal in-phase input end VLPAnd a seventeenth mirror NMOS transistor MN17Source electrode of the nineteenth mirror NMOS transistor MN19The drain electrode and the valley wave error signal in-phase output end VN+Seventeenth mirror PMOS transistor MP17Drain electrode of (1) and seventeenth mirror PMOS transistor MP17The grid of the NMOS transistor is connected, and the nineteenth mirror image NMOS transistor MN19Grid and twentieth mirror image NMOS tube MN20Grid and twentieth mirror image NMOS transistor MN20And a fourth bias current source Ibias4An output terminal of (a);
the twentieth mirror image NMOS tube MN20Source and valley wave error signal inverting input terminal VLMAnd eighteenth mirror NMOS transistor MN18Source electrode of (1), the twentieth mirror image NMOS tube MN20Drain of the NMOS transistor M is connected with the twentieth mirror image NMOS transistor MN20Grid and nineteenth mirror image NMOS transistor MN19And a fourth bias current source Ibias4The output ends of the two-way valve are connected;
the seventeenth mirror NMOS transistor MN17Eighteenth mirror NMOS transistor MN18Nineteenth mirror image NMOS tube MN19And twentieth mirror NMOS transistor MN20The substrate poles of the two-way switch are all connected with the ground;
the second bias current unit comprises a third bias current source Ibias3And a fourth bias current source Ibias4；
The third bias current source Ibias3Is connected to a power supply, the third bias current source Ibias3Output end of the NMOS transistor M and the seventeenth mirror image NMOS transistor MN17Drain electrode of (1), seventeenth mirror NMOS tube MN17Grid and eighteenth mirror image NMOS tube MN18The gate of (1) is connected;
the fourth bias current source Ibias4Is connected to a power supply, the fourth bias current source Ibias4And an output terminal ofTwentieth mirror image NMOS tube MN20Drain electrode of the transistor, twentieth mirror image NMOS transistor MN20Gate of and nineteenth mirror NMOS transistor MN19Is connected to the gate of (a).
Specifically, the sixteenth mirror image PMOS transistor MP16Is a fourteenth mirror PMOS transistor MP14And a fourteenth mirror PMOS transistor MP14Has a proportional relationship of 1/1; seventeenth mirror PMOS tube MP17Is a fifteenth mirror PMOS transistor MP15And a fifteenth mirror PMOS transistor MP15Has a proportional relationship of 1/1.
Eighteenth mirror NMOS tube MN18Is a seventeenth mirror NMOS transistor MN17And a seventeenth mirror NMOS transistor MN17Has a proportional relation of 1/1, and the nineteenth mirror image NMOS transistor MN19NMOS transistor M which is also a seventeenth mirror imageN17And a seventeenth mirror NMOS transistor MN17Has a proportional relationship of 1/1; twentieth mirror image NMOS tube MN20NMOS transistor M which is also a seventeenth mirror imageN17And a seventeenth mirror NMOS transistor MN17Has a proportional relationship of 1/1.
The bias currents of the third bias current source and the fourth bias current source are equal to that of the first bias current source.
The embodiment of the invention realizes the mirror ratio of 1/2000 and 1/25 by two-stage mirror image, and realizes the mirror ratio of 1/50000 large-scale inductive current; the common-mode signal rejection capability is enhanced, and burrs of full-wave inductive current sampling signals generated by common-mode signals such as static operating point offset, mode switching and enabling signals can be greatly suppressed.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.

Claims (10)

1. A DC-DC full wave inductor current sensor, comprising:
the PMOS mirror module is used for outputting a first mirror current according to an inductive current and an error amplification signal input by an inductive common end, and comprises a first mirror PMOS tube, a second mirror PMOS tube, a third mirror PMOS tube, a fourth mirror PMOS tube, a fifth mirror PMOS tube, a sixth mirror PMOS tube and a seventh mirror PMOS tube;
the source electrode of the first mirror image PMOS tube is connected with a power supply, the drain electrode of the first mirror image PMOS tube is connected with the common end of an inductor, the drain electrode of the first mirror image NMOS tube and the drain electrode of the second mirror image NMOS tube, and the grid electrode of the first mirror image PMOS tube is connected with a P grid enabling signal generating module;
the source electrode of the second mirror image PMOS tube is connected with a power supply, the drain electrode of the second mirror image PMOS tube is connected with the drain electrode of the fourth mirror image NMOS tube, and the grid electrode of the second mirror image PMOS tube is connected with the ground;
the source electrode of the third mirror image PMOS tube is connected with a power supply, the drain electrode of the third mirror image PMOS tube is connected with the drain electrode of the third mirror image NMOS tube and the source electrode of the fourth switch PMOS tube, and the grid electrode of the third mirror image PMOS tube is connected with the ground;
the source electrode of the fourth mirror image PMOS tube is connected with a power supply, and the drain electrode of the fourth mirror image PMOS tube is connected with the grid electrode of the fourth mirror image PMOS tube, the source electrode of the fifth mirror image PMOS tube and the grid electrode of the sixth mirror image PMOS tube;
the source electrode of the fifth mirror image PMOS tube is connected with the drain electrode and the grid electrode of the fourth mirror image PMOS tube, and the drain electrode of the fifth mirror image PMOS tube is connected with the grid electrode of the fifth mirror image PMOS tube, the grid electrode of the seventh mirror image PMOS tube and the drain electrode of the seventh mirror image NMOS tube;
the source electrode of the sixth mirror image PMOS tube is connected with a power supply, the drain electrode of the sixth mirror image PMOS tube is connected with the source electrode of the seventh mirror image PMOS tube, and the grid electrode of the sixth mirror image PMOS tube is connected with the grid electrode of the fourth mirror image PMOS tube;
the source electrode of the seventh mirror image PMOS tube is connected with the drain electrode of the sixth mirror image PMOS tube, the drain electrode of the seventh mirror image PMOS tube outputs a full-wave inductive current sampling signal, and the grid electrode of the seventh mirror image PMOS tube is connected with the grid electrode of the fifth mirror image PMOS tube, the drain electrode of the fifth mirror image PMOS tube and the drain electrode of the seventh mirror image NMOS tube;
the substrate electrodes of the first mirror image PMOS tube, the second mirror image PMOS tube, the third mirror image PMOS tube, the fourth mirror image PMOS tube, the fifth mirror image PMOS tube, the sixth mirror image PMOS tube and the seventh mirror image PMOS tube are all connected with a power supply;
the NMOS mirror image module is used for outputting a second mirror image current according to an inductive current and an error amplification signal input by the inductive common end, wherein the NMOS mirror image module comprises a first mirror image NMOS tube, a second mirror image NMOS tube, a third mirror image NMOS tube, a fourth mirror image NMOS tube, a fifth mirror image NMOS tube, a sixth mirror image NMOS tube and a seventh mirror image NMOS tube;
the source electrode of the first mirror image NMOS tube is connected with the ground, the drain electrode of the first mirror image NMOS tube is connected with the common end of the inductor, the drain electrode of the first mirror image PMOS tube and the drain electrode of the second mirror image NMOS tube, and the grid electrode of the first mirror image NMOS tube is connected with the N grid enabling signal generating module;
the source electrode of the second mirror image NMOS tube is connected with the source electrode of a sixth mirror image NMOS tube and the drain electrode of a fourth switch NMOS tube of the source electrode of a third switch NMOS tube, the drain electrode of the second mirror image NMOS tube is connected with the common end of the inductor, the drain electrode of the first mirror image PMOS tube and the drain electrode of the first mirror image NMOS tube, and the grid electrode of the second mirror image NMOS tube is connected with the N-grid enabling signal generating module;
the source electrode of the third mirror image NMOS tube is connected with the drain electrode and the grid electrode of the fifth mirror image NMOS tube, the drain electrode of the third mirror image NMOS tube is connected with the drain electrode of the third mirror image PMOS tube and the source electrode of the fourth switch PMOS tube, and the grid electrode of the third mirror image NMOS tube is connected with the output end of the error amplification module and the grid electrode of the fourth mirror image NMOS tube;
the source electrode of the fourth mirror image NMOS tube is connected with the drain electrode and the grid electrode of the sixth mirror image NMOS tube, the drain electrode of the fourth mirror image NMOS tube is connected with the drain electrode of the second mirror image PMOS tube, and the grid electrode of the fourth mirror image NMOS tube is connected with the output end of the error amplification module and the grid electrode of the third mirror image NMOS tube;
the source electrode of the fifth mirror image NMOS tube is connected with the ground, and the drain electrode of the fifth mirror image NMOS tube is connected with the grid electrode of the fifth mirror image NMOS tube, the source electrode of the third mirror image NMOS tube and the grid electrode of the seventh mirror image NMOS tube;
the source electrode of the sixth mirror image NMOS tube is connected with the source electrode of the second mirror image NMOS tube, the source electrode of the third switch NMOS tube and the drain electrode of the fourth switch NMOS tube, and the drain electrode of the sixth mirror image NMOS tube is connected with the grid electrode of the sixth mirror image NMOS tube and the source electrode of the fourth mirror image NMOS tube;
the source electrode of the seventh mirror image NMOS tube is connected with the ground, the drain electrode of the seventh mirror image NMOS tube is connected with the drain electrode and the grid electrode of the fifth mirror image PMOS tube, and the grid electrode of the seventh mirror image NMOS tube is connected with the drain electrode and the grid electrode of the fifth mirror image NMOS tube;
the substrate electrodes of the first mirror image NMOS tube, the second mirror image NMOS tube, the third mirror image NMOS tube, the fourth mirror image NMOS tube, the fifth mirror image NMOS tube, the sixth mirror image NMOS tube and the seventh mirror image NMOS tube are all connected with the ground;
the enabling signal generating module is used for outputting an inverted P gate enabling signal according to the P gate enabling signal and outputting an inverted N gate enabling signal according to the N gate enabling signal;
the PMOS switch module is used for selecting a peak wave signal according to the P gate enable signal and the inverted P gate enable signal;
the NMOS switch module is used for selecting a valley wave signal according to the N gate enable signal and the inverted N gate enable signal;
the error amplification module is used for selectively processing the peak wave signal and the valley wave signal according to the P gate enable signal, the N gate enable signal and the reversed phase N gate enable signal and outputting an error amplification signal;
the PMOS mirror module and the NMOS mirror module are both provided with two stages of mirrors, and the first mirror current and the second mirror current jointly form output current.
2. The DC-DC full-wave inductor current sensor of claim 1, wherein the PMOS switch module comprises a first switch PMOS transistor, a second switch PMOS transistor, a third switch PMOS transistor, and a fourth switch PMOS transistor;
the source electrode of the first switch PMOS tube is connected with the common end of the inductor, the drain electrode of the first switch PMOS tube is connected with the peak wave error signal inverting input end of the error amplification module and the drain electrode of the second switch PMOS tube, and the grid electrode of the first switch PMOS tube is connected with the P grid enabling signal generation module;
the source electrode of the second switch PMOS tube is connected with a power supply, the drain electrode of the second switch PMOS tube is connected with the peak wave error signal inverting input end of the error amplification module and the drain electrode of the first switch PMOS tube, and the grid electrode of the second switch PMOS tube is connected with the inverting P grid enabling signal end of the enabling signal generation module;
the source electrode of the third switch PMOS tube is connected with a power supply, the drain electrode of the third switch PMOS tube is connected with the peak wave error signal in-phase input end of the error amplification module and the drain electrode of the fourth switch PMOS tube, and the grid electrode of the third switch PMOS tube is connected with the inverted P grid enabling signal end of the enabling signal generation module;
the source electrode of the fourth switch PMOS tube is connected with the drain electrode of the third mirror image PMOS tube and the drain electrode of the third mirror image NMOS tube, the drain electrode of the fourth switch PMOS tube is connected with the peak wave error signal in-phase input end of the error amplification module and the drain electrode of the third switch PMOS tube, and the grid electrode of the fourth switch PMOS tube is connected with the P grid enabling signal generation module;
substrate electrodes of the first switch PMOS tube, the second switch PMOS tube, the third switch PMOS tube and the fourth switch PMOS tube are all connected with a power supply;
the NMOS switch module comprises a first switch NMOS tube, a second switch NMOS tube, a third switch NMOS tube and a fourth switch NMOS tube;
the source electrode of the first switch NMOS tube is connected with the ground, the drain electrode of the first switch NMOS tube is connected with the valley wave error signal in-phase input end of the error amplification module, and the grid electrode of the first switch NMOS tube is connected with the power supply;
the source electrode of the second switch NMOS tube is connected with the ground, the drain electrode of the second switch NMOS tube is connected with the valley wave error signal inverting input end of the error signal amplifying module and the drain electrode of the third switch NMOS tube, and the grid electrode of the second switch NMOS tube is connected with the inverting N grid enabling signal end of the enabling signal generating module;
the source electrode of the third switch NMOS tube is connected with the drain electrode of the fourth switch NMOS tube, the source electrode of the sixth mirror image NMOS tube and the source electrode of the second mirror image NMOS tube, the drain electrode of the third switch NMOS tube is connected with the valley wave error signal inverting input end of the error amplification module and the drain electrode of the second switch NMOS tube, and the grid electrode of the third switch NMOS tube is connected with the N grid enabling signal generating module;
the source electrode of the fourth switch NMOS tube is connected with the ground, the drain electrode of the fourth switch NMOS tube is connected with the source electrode of the third switch NMOS tube, the source electrode of the sixth mirror image NMOS tube and the source electrode of the second mirror image NMOS tube, and the grid electrode of the fourth switch NMOS tube is connected with the inverted N grid enabling signal end of the enabling signal generating module;
and the substrate electrodes of the first switch NMOS tube, the second switch NMOS tube, the third switch NMOS tube and the fourth switch NMOS tube are all connected with the ground.
3. The DC-DC full wave inductor current sensor of claim 1, wherein the enable signal generating module comprises:
the first reverser submodule is used for outputting an inverted P grid enabling signal according to the P grid enabling signal;
the second reverser submodule is used for outputting an inverted N-grid enabling signal according to the N-grid enabling signal;
the inverted P-gate enable signal has a slight delay relative to the P-gate enable signal, and the inverted N-gate enable signal has a slight delay relative to the N-gate enable signal.
4. A DC-DC full wave inductor current sensor according to claim 1, wherein said error amplification module comprises:
the peak wave differential level conversion submodule is used for outputting a peak wave differential signal according to the peak wave signal;
the valley wave differential level converter module is used for outputting a valley wave differential signal according to the valley wave signal;
and the Gilbert amplifying submodule is used for selectively processing the peak wave differential signal and the valley wave differential signal according to the P gate enable signal, the N gate enable signal and the inverted N gate enable signal and outputting an error amplifying signal.
5. The DC-DC full wave inductor current sensor according to claim 4, wherein the peak wave differential level conversion module comprises:
the first PMOS mirror image unit is used for outputting a peak wave differential signal according to the peak wave signal and matched with the first NMOS mirror image unit;
the first NMOS mirror image unit is used for outputting a peak wave differential signal in cooperation with the first PMOS mirror image unit;
and the first bias current unit is used for biasing the first PMOS mirror image unit.
6. The DC-DC full-wave inductor current sensor according to claim 5, wherein the first PMOS mirror unit comprises an eighth mirror PMOS transistor, a ninth mirror PMOS transistor, a tenth mirror PMOS transistor and an eleventh mirror PMOS transistor;
the source electrode of the eighth mirror image PMOS tube is connected with the substrate electrode of the eighth mirror image PMOS tube, the inverse input end of the peak wave error signal, the source electrode of the tenth mirror image PMOS tube and the substrate electrode of the tenth mirror image PMOS tube, and the drain electrode of the eighth mirror image PMOS tube is connected with the grid electrode of the eighth mirror image PMOS tube, the grid electrode of the ninth mirror image PMOS tube and the input end of the first bias current source;
the source electrode of the ninth mirror image PMOS tube is connected with the substrate electrode of the ninth mirror image PMOS tube, the peak wave error signal in-phase input end, the source electrode of the eleventh mirror image PMOS tube and the substrate electrode of the eleventh mirror image PMOS tube, the drain electrode of the ninth mirror image PMOS tube is connected with the peak wave error signal in-phase output end, the drain electrode of the eighth mirror image NMOS tube and the grid electrode of the ninth mirror image PMOS tube, and the grid electrode of the ninth mirror image PMOS tube is connected with the grid electrode of the eighth mirror image PMOS tube, the drain electrode of the eighth mirror image PMOS tube and the input end of the first bias current source;
the source electrode of the tenth mirror image PMOS tube is connected with a substrate electrode of the tenth mirror image PMOS tube, a peak wave error signal inverting input end, a source electrode of the eighth mirror image PMOS tube and a substrate electrode of the eighth mirror image PMOS tube, the drain electrode of the tenth mirror image PMOS tube is connected with a peak wave error signal inverting output end, a drain electrode of the tenth mirror image NMOS tube and a grid electrode of the tenth mirror image NMOS tube, and the grid electrode of the tenth mirror image PMOS tube is connected with a grid electrode of the eleventh mirror image PMOS tube, a drain electrode of the eleventh mirror image PMOS tube and an input end of a second bias current source;
the source electrode of the eleventh mirror image PMOS tube is connected with the substrate electrode of the eleventh mirror image PMOS tube, the in-phase input end of the peak wave error signal, the source electrode of the ninth mirror image PMOS tube and the substrate electrode of the ninth mirror image PMOS tube, and the drain electrode of the eleventh mirror image PMOS tube is connected with the grid electrode of the eleventh mirror image PMOS tube, the grid electrode of the tenth mirror image PMOS tube and the input end of the second bias current source;
the first NMOS mirror image unit comprises an eighth mirror image NMOS tube, a ninth mirror image NMOS tube, a tenth mirror image NMOS tube and an eleventh mirror image NMOS tube;
the source electrode of the eighth mirror image NMOS tube is connected with the drain electrode of the ninth mirror image NMOS tube and the grid electrode of the ninth mirror image NMOS tube, and the drain electrode of the eighth mirror image NMOS tube is connected with the grid electrode of the eighth mirror image NMOS tube, the peak wave error signal in-phase output end and the drain electrode of the ninth mirror image PMOS tube;
the source electrode of the ninth mirror image NMOS tube is connected with the ground, and the drain electrode of the ninth mirror image NMOS tube is connected with the grid electrode of the ninth mirror image NMOS tube and the source electrode of the eighth mirror image NMOS tube;
the source electrode of the tenth mirror image NMOS tube is connected with the drain electrode of the eleventh mirror image NMOS tube and the grid electrode of the eleventh mirror image NMOS tube, and the drain electrode of the tenth mirror image NMOS tube is connected with the grid electrode of the tenth mirror image NMOS tube, the peak wave error signal inverted output end and the drain electrode of the tenth mirror image PMOS tube;
the source electrode of the eleventh mirror image NMOS tube is connected with the ground, and the drain electrode of the eleventh mirror image NMOS tube is connected with the grid electrode of the eleventh mirror image NMOS tube and the source electrode of the tenth mirror image NMOS tube;
the substrate electrodes of the eighth mirror image NMOS tube, the ninth mirror image NMOS tube, the tenth mirror image NMOS tube and the eleventh mirror image NMOS tube are all connected with the ground;
the first bias current unit includes a first bias current source and a second bias current source;
the input end of the first bias current source is connected with the drain electrode of the eighth mirror image PMOS tube, the grid electrode of the eighth mirror image PMOS tube and the grid electrode of the ninth mirror image PMOS tube, and the output end of the first bias current source is connected with the ground;
the input end of the second bias current source is connected with the drain electrode of the eleventh mirror image PMOS tube, the grid electrode of the eleventh mirror image PMOS tube and the grid electrode of the tenth mirror image PMOS tube, and the output end of the second bias current source is grounded.
7. The DC-DC full wave inductor current sensor of claim 4, wherein the Gilbert amplifier sub-module comprises:
the second PMOS mirror image unit is used for outputting an error amplification signal in cooperation with the second NMOS mirror image unit;
the second NMOS mirror image unit is used for being matched with the second PMOS mirror image unit and outputting an error amplification signal;
the first NMOS switch unit is used for selectively processing the peak wave differential signal and the valley wave differential signal according to the P gate enabling signal and the inverted N gate enabling signal and controlling the enabling of the Gilbert unit;
the sampling and holding unit is used for keeping the output voltage unchanged during the period that the Gilbert amplification sub-module is not enabled and compensating a closed loop accessed by the error amplification module during the period that the Gilbert amplification sub-module is enabled;
and the bias voltage unit is used for biasing the Gilbert amplification sub-module.
8. The DC-DC full wave inductor current sensor of claim 7, wherein the second PMOS mirror unit comprises a twelfth mirror PMOS transistor and a thirteenth mirror PMOS transistor;
the source electrode of the twelfth mirror image PMOS tube is connected with a power supply, and the drain electrode of the twelfth mirror image PMOS tube is connected with the grid electrode of the twelfth mirror image PMOS tube, the grid electrode of the thirteenth mirror image PMOS tube, the drain electrode of the thirteenth mirror image NMOS tube and the drain electrode of the fifteenth mirror image NMOS tube;
the source electrode of the thirteenth mirror image PMOS tube is connected with a power supply, the drain electrode of the thirteenth mirror image PMOS tube is connected with the drain electrode of the twelfth mirror image NMOS tube, the drain electrode of the sixteenth mirror image NMOS tube, the drain electrode of the seventh switch NMOS tube and the source electrode of the fifth switch PMOS tube, and the grid electrode of the thirteenth mirror image PMOS tube is connected with the grid electrode of the twelfth mirror image NMOS tube, the drain electrode of the thirteenth mirror image NMOS tube and the drain electrode of the fifteenth mirror image NMOS tube;
the substrate electrodes of the twelfth mirror image PMOS tube and the thirteenth mirror image PMOS tube are both connected with a power supply;
the second NMOS mirror image unit comprises a twelfth mirror image NMOS tube, a thirteenth mirror image NMOS tube, a fourteenth mirror image NMOS tube, a fifteenth mirror image NMOS tube and a sixteenth mirror image NMOS tube;
the source electrode of the twelfth mirror image NMOS tube is connected with the drain electrode of the fifth switch NMOS tube and the source electrode of the thirteenth mirror image NMOS tube, the drain electrode of the twelfth mirror image NMOS tube is connected with the drain electrode of the sixteenth mirror image NMOS tube, the drain electrode of the thirteenth mirror image PMOS tube, the drain electrode of the seventh switch NMOS tube and the source electrode of the fifth switch PMOS tube, and the grid electrode of the twelfth mirror image NMOS tube is connected with the peak wave error signal inverting output end;
the source electrode of the thirteenth mirror image NMOS tube is connected with the drain electrode of the fifth switch NMOS tube and the source electrode of the twelfth mirror image NMOS tube, the drain electrode of the thirteenth mirror image NMOS tube is connected with the drain electrode of the fifteenth mirror image NMOS tube, the drain electrode of the twelfth mirror image PMOS tube and the grid electrode of the twelfth mirror image PMOS tube, and the grid electrode of the thirteenth mirror image NMOS tube is connected with the peak wave error signal in-phase output end;
the source electrode of the fourteenth mirror NMOS tube is connected with the ground, the drain electrode of the fourteenth mirror NMOS tube is connected with the source electrode of the fifth switch NMOS tube and the source electrode of the sixth switch NMOS tube, and the grid electrode of the fourteenth mirror NMOS tube is connected with a bias voltage source;
the source electrode of the fifteenth mirror image NMOS tube is connected with the source electrode of the sixteenth mirror image NMOS tube and the drain electrode of the sixth switch NMOS tube, the drain electrode of the fifteenth mirror image NMOS tube is connected with the drain electrode of the thirteenth mirror image NMOS tube, the drain electrode of the twelfth mirror image PMOS tube and the grid electrode of the twelfth mirror image PMOS tube, and the grid electrode of the fifteenth mirror image NMOS tube is connected with the valley wave error signal in-phase output end;
the source electrode of the sixteenth mirror image NMOS tube is connected with the source electrode of the fifteenth mirror image NMOS tube and the drain electrode of the sixth switch NMOS tube, the drain electrode of the sixteenth mirror image NMOS tube is connected with the drain electrode of the twelfth mirror image NMOS tube, the drain electrode of the thirteenth mirror image PMOS tube, the drain electrode of the seventh switch NMOS tube and the source electrode of the fifth switch PMOS tube, and the grid electrode of the sixteenth mirror image NMOS tube is connected with the valley wave error signal inverting output end;
the substrate electrodes of the twelfth mirror image NMOS tube, the thirteenth mirror image NMOS tube, the fourteenth mirror image NMOS tube, the fifteenth mirror image NMOS tube and the sixteenth mirror image NMOS tube are all connected with the ground;
the first NMOS switch unit comprises a fifth switch NMOS tube, a sixth switch NMOS tube and a seventh switch NMOS tube;
the source electrode of the fifth switch NMOS tube is connected with the source electrode of the sixth switch NMOS tube and the drain electrode of the fourteenth mirror NMOS tube, the drain electrode of the fifth switch NMOS tube is connected with the source electrode of the twelfth mirror NMOS tube and the source electrode of the thirteenth mirror NMOS tube, and the grid electrode of the fifth switch NMOS tube is connected with the inverted N-grid enabling signal end of the enabling signal generating module;
the source electrode of the sixth switch NMOS tube is connected with the source electrode of the fifth switch NMOS tube and the drain electrode of the fourteenth mirror NMOS tube, the drain electrode of the sixth switch NMOS tube is connected with the source electrode of the fifteenth mirror NMOS tube and the source electrode of the sixteenth mirror NMOS tube, and the grid electrode of the sixth switch NMOS tube is connected with the P grid enabling signal generating module;
the source electrode of the seventh switch NMOS tube is connected with the output end of the error amplification module, the drain electrode of the fifth switch PMOS tube and one end of the sampling holding capacitor, the drain electrode of the seventh switch NMOS tube is connected with the source electrode of the fifth switch PMOS tube, the drain electrode of the thirteenth mirror image PMOS tube, the drain electrode of the twelfth mirror image NMOS tube and the drain electrode of the sixteenth mirror image NMOS tube, and the grid electrode of the seventh switch NMOS tube is connected with the N-grid enabling signal generation module;
the substrate electrodes of the fifth switch NMOS tube, the sixth switch NMOS tube and the seventh switch NMOS tube are all connected with the ground;
the sampling and holding unit comprises a sampling and holding capacitor and a fifth switch PMOS tube;
the source electrode of the fifth switch PMOS tube is connected with the drain electrode of the seventh switch NMOS tube, the drain electrode of the thirteenth mirror image PMOS tube, the drain electrode of the twelfth mirror image NMOS tube and the drain electrode of the sixteenth mirror image NMOS tube, the drain electrode of the fifth switch PMOS tube is connected with the source electrode of the seventh switch NMOS tube and one end of the sampling holding capacitor, and the grid electrode of the fifth switch PMOS tube is connected with the P grid enabling signal generating module;
one end of the sampling holding capacitor is connected with the source electrode of the seventh switch NMOS tube and the drain electrode of the fifth switch PMOS tube, and the other end of the sampling holding capacitor is grounded;
the bias voltage unit includes a bias voltage source.
9. The DC-DC full-wave inductor current sensor according to claim 4, wherein the valley difference level conversion module comprises:
the third PMOS mirror image unit is used for outputting a valley wave differential signal according to the valley wave signal and by matching with the third NMOS mirror image unit;
the third NMOS mirror image unit is used for outputting a valley wave differential signal according to the valley wave signal and by matching with the third PMOS mirror image unit;
and the second bias current unit is used for biasing the third NMOS mirror image unit.
10. The DC-DC full-wave inductor current sensor of claim 9, wherein the third PMOS mirror unit comprises a fourteenth mirror PMOS transistor, a fifteenth mirror PMOS transistor, a sixteenth mirror PMOS transistor and a seventeenth mirror PMOS transistor;
the source electrode of the fourteenth mirror image PMOS tube is connected with a power supply, and the drain electrode of the fourteenth mirror image PMOS tube is connected with the grid electrode of the fourteenth mirror image PMOS tube and the source electrode of the fifteenth mirror image PMOS tube;
the source electrode of the fifteenth mirror image PMOS tube is connected with the drain electrode of the fourteenth mirror image PMOS tube and the grid electrode of the fourteenth mirror image PMOS tube, and the drain electrode of the fifteenth mirror image PMOS tube is connected with the grid electrode of the fifteenth mirror image PMOS tube, the valley wave error signal inverted output end and the drain electrode of the eighteenth mirror image NMOS tube;
the source electrode of the sixteenth mirror image PMOS tube is connected with a power supply, and the drain electrode of the sixteenth mirror image PMOS tube is connected with the grid electrode of the sixteenth mirror image PMOS tube and the source electrode of the seventeenth mirror image PMOS tube;
the source electrode of the seventeenth mirror image PMOS tube is connected with the drain electrode of the sixteenth mirror image PMOS tube and the grid electrode of the sixteenth mirror image PMOS tube, and the drain electrode of the seventeenth mirror image PMOS tube is connected with the grid electrode of the seventeenth mirror image PMOS tube, the valley wave error signal in-phase output end and the drain electrode of the nineteenth mirror image NMOS tube;
the substrate electrodes of the fourteenth mirror image PMOS tube, the fifteenth mirror image PMOS tube, the sixteenth mirror image PMOS tube and the seventeenth mirror image PMOS tube are all connected with a power supply;
the third NMOS mirror image unit comprises a seventeenth mirror image NMOS tube, an eighteenth mirror image NMOS tube, a nineteenth mirror image NMOS tube and a twentieth mirror image NMOS tube;
the source electrode of the seventeenth mirror image NMOS tube is connected with the valley wave error signal in-phase input end and the source electrode of the nineteenth mirror image NMOS tube, and the drain electrode of the seventeenth mirror image NMOS tube is connected with the grid electrode of the seventeenth mirror image NMOS tube, the output end of the third bias current source and the grid electrode of the eighteenth mirror image NMOS tube;
the source electrode of the eighteenth mirror image NMOS tube is connected with the valley wave error signal inverting input end and the source electrode of the twentieth mirror image NMOS tube, the drain electrode of the eighteenth mirror image NMOS tube is connected with the valley wave error signal inverting output end, the drain electrode of the fifteenth mirror image PMOS tube and the drain electrode grid electrode of the fifteenth mirror image PMOS tube, and the grid electrode of the eighteenth mirror image NMOS tube is connected with the grid electrode of the seventeenth mirror image NMOS tube, the drain electrode of the seventeenth mirror image NMOS tube and the output end of the third bias current source;
the source electrode of the nineteenth mirror image NMOS tube is connected with the valley wave error signal in-phase input end and the source electrode of the seventeenth mirror image NMOS tube, the drain electrode of the nineteenth mirror image NMOS tube is connected with the valley wave error signal in-phase output end, the drain electrode of the seventeenth mirror image PMOS tube and the grid electrode of the seventeenth mirror image PMOS tube, and the grid electrode of the nineteenth mirror image NMOS tube is connected with the grid electrode of the twentieth mirror image NMOS tube, the drain electrode of the twentieth mirror image NMOS tube and the output end of the fourth bias current source;
the source electrode of the twentieth mirror image NMOS tube is connected with the valley wave error signal inverting input end and the source electrode of the eighteenth mirror image NMOS tube, and the drain electrode of the twentieth mirror image NMOS tube is connected with the grid electrode of the twentieth mirror image NMOS tube, the grid electrode of the nineteenth mirror image NMOS tube and the output end of the fourth bias current source;
substrate electrodes of the seventeenth mirror image NMOS tube, the eighteenth mirror image NMOS tube, the nineteenth mirror image NMOS tube and the twentieth mirror image NMOS tube are all connected with the ground;
the second bias current unit includes a third bias current source and a fourth bias current source;
the input end of the third bias current source is connected with a power supply, and the output end of the third bias current source is connected with the drain electrode of the seventeenth mirror NMOS tube, the grid electrode of the seventeenth mirror NMOS tube and the grid electrode of the eighteenth mirror NMOS tube;
the input end of the fourth bias current source is connected with the power supply, and the output end of the fourth bias current source is connected with the drain electrode of the twentieth mirror image NMOS tube, the grid electrode of the twentieth mirror image NMOS tube and the grid electrode of the nineteenth mirror image NMOS tube.
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