CN105762113A - MOS circuit manufacturing method and MOS circuit - Google Patents
MOS circuit manufacturing method and MOS circuit Download PDFInfo
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- CN105762113A CN105762113A CN201410790173.8A CN201410790173A CN105762113A CN 105762113 A CN105762113 A CN 105762113A CN 201410790173 A CN201410790173 A CN 201410790173A CN 105762113 A CN105762113 A CN 105762113A
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Abstract
The invention provides an MOS circuit manufacturing method and an MOS circuit. The method comprises the steps of forming a well region on a substrate, forming an oxide layer on the well region, depositing an undoped polysilicon film layer on the oxide layer, conducting the first doping operation on the polysilicon film layer, conducting the photoetching and etching operation on the polysilicon film layer to form a first polysilicon resistor and a second polysilicon resistor, and conducting the second doping operation on one side of second polysilicon resistor. The second doping concentration is greater than the first doping concentration. The first doping is the n-doping and the second doping is the p-doping. Or, the first doping is the p-doping and the second doping is the n-doping. According to the technical scheme of the MOS circuit manufacturing method and the MOS circuit, the two doping operations are completed only by means of diodes and resistors. Therefore, no photoetching/etching operation on diodes and resistors respectively is required. As a result, the MOS circuit manufacturing efficiency is improved. Meanwhile, the process cost is lowered.
Description
Technical field
The present invention relates to ic manufacturing technology, particularly relate to a kind of MOS circuit fabrication method and MOS circuit.
Background technology
MOS circuit is with Metal-oxide-semicondutor (MetalOxideSemiconductor, MOS) field-effect transistor is the integrated circuit that main element is constituted, have that volume is little, speed is fast, reliability is high, power consumption and the characteristic such as cost is all relatively low, thus be widely used in the fields such as computer, communication, electromechanical instrument, automation appliance, Aero-Space.
In MOS circuit, generally comprise P-channel metal-oxide-semiconductor (P-channelMetalOxideSemiconductor, PMOS), the components and parts such as N-channel metal-oxide semiconductor (MOS) (N-channelMetalOxideSemiconductor, NMOS), diode, resistance, electric capacity.Wherein, resistance mostly is in polysilicon doped with boron, the polysilicon resistance that formed after phosphorus or other impurity, and doping content can affect resistance.The essence of diode is PN junction, is that the side to monocrystal silicon or polysilicon carries out N doping, opposite side is formed after carrying out P doping.
The deficiencies in the prior art part is in that, in MOS circuit fabrication process, it is necessary to be respectively provided with doping process for diode and resistance, and process efficiency is relatively low and relatively costly.
Summary of the invention
The present invention provides a kind of MOS circuit fabrication method and MOS circuit, in order to solve the technical problem that in prior art, MOS circuit manufacturing process is inefficient, relatively costly.
The present invention provides a kind of MOS circuit fabrication method, including:
Substrate is formed well region, described well region is formed oxide layer；
Described oxide layer deposits unadulterated polycrystalline silicon membrane；
Described polycrystalline silicon membrane is carried out the first doping；
Described polycrystalline silicon membrane is carried out photoetching, etching, forms the first polysilicon resistance and the second polysilicon resistance；
The side of described second polysilicon resistance is carried out the second doping；
Wherein, the concentration of described second doping is more than the concentration of described first doping；
Described first is doped to N doping, and second is doped to P doping；Or, described first is doped to P doping, and second is doped to N doping.
Further, the doping content of described first doping is 1E14-1E15 atom/square centimeter；The doping content of described second doping is 2E15-8E15 atom/square centimeter.
Further, described oxide layer includes gate oxide and field oxide；
After described polycrystalline silicon membrane is carried out the first doping, also include:
The polycrystalline silicon membrane on described gate oxide surface is carried out the 3rd doping；
Described described polycrystalline silicon membrane is carried out photoetching, etching, forms the first polysilicon resistance and the second polysilicon resistance, specifically include:
Described polycrystalline silicon membrane is carried out photoetching, etching, described field oxide is formed the first polysilicon resistance and the second polysilicon resistance, described gate oxide is formed polysilicon gate.
Further, described well region includes N trap and p-well；
Described formation oxide layer on described well region, specifically includes:
Described N trap and p-well form gate oxide respectively, between described gate oxide, forms field oxide；
Described formation polysilicon gate on described gate oxide, specifically includes:
The gate oxide of described N trap and p-well forms polysilicon gate respectively.
Further, the described side to described second polysilicon resistance also includes while carrying out the second doping:
The subregion being positioned at polysilicon gate both sides in described p-well is carried out the second doping respectively；
Wherein, described second it is doped to N doping.
Further, also include:
The opposite side of the subregion and the second polysilicon resistance that are positioned at described polysilicon gate both sides in described N trap is carried out the 4th doping；
Wherein, the described 4th it is doped to P doping；In described second polysilicon resistance through second doping part and through the 4th doping part between interval predeterminable range.
Further, the described side to described second polysilicon resistance also includes while carrying out the second doping:
The subregion being positioned at polysilicon gate both sides in described N trap is carried out the second doping respectively；
Wherein, described second it is doped to P doping.
Further, after carrying out the second doping, also include:
The opposite side of the subregion and the second polysilicon resistance that are positioned at described polysilicon gate both sides in described p-well is carried out the 4th doping；
Wherein, the described 4th it is doped to N doping；In described second polysilicon resistance through second doping part and through the 4th doping part between interval predeterminable range.
Further, the concentration of described 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of described 4th doping is 2E15-8E15 atom/square centimeter.
The present invention also provides for a kind of MOS circuit, including: substrate, forms well region over the substrate, the oxide layer formed on described well region and forms the first polysilicon resistance in described oxide layer and diode；
Described first polysilicon resistance is the polysilicon through the first doping；
Described diode is side through first adulterating, opposite side is through the polysilicon of the second doping；
Wherein, the concentration of described second doping is more than the concentration of described first doping；
Described first is doped to N doping, and second is doped to P doping；Or, described first is doped to P doping, and second is doped to N doping.
Further, the doping content of described first doping is 1E14-1E15 atom/square centimeter；The doping content of described second doping is 2E15-8E15 atom/square centimeter.
Further, described MOS circuit also includes: polysilicon gate；
Described oxide layer includes gate oxide and field oxide；
Described first polysilicon resistance and diode are positioned on described field oxide；
Described polysilicon gate is positioned on described gate oxide；
Described polysilicon gate is the polysilicon through the first doping and the 3rd doping.
Further, described well region includes N trap and p-well；
Described N trap and p-well are respectively formed with gate oxide, between described gate oxide, are formed with field oxide；
The gate oxide of described N trap and p-well is respectively formed with polysilicon gate.
Further, described MOS circuit also includes: the first n-type doping district and the second n-type doping district；
Wherein, the subregion being positioned at polysilicon gate both sides in described first n-type doping district and the second n-type doping district respectively described p-well is formed after second adulterates；Described second is doped to N doping.
Further, described MOS circuit also includes: a P type doped region, the 2nd P type doped region and the external district of P type；
Wherein, the subregion being positioned at polysilicon gate both sides in a described P type doped region and the 2nd P type doped region respectively described N trap is formed after the 4th adulterates；
The described external district of P type is formed after the side in the region of the second doping carries out the 4th doping away from described diode in the region of the first doping at described diode；Described diode through second doping region and through the 4th doping region between interval predeterminable range；Described 4th is doped to P doping.
Further, described MOS circuit also includes: a P type doped region and the 2nd P type doped region；
Wherein, the subregion being positioned at polysilicon gate both sides in a described P type doped region and the 2nd P type doped region respectively described N trap is formed after second adulterates；Described second is doped to P doping.
Further, described MOS circuit also includes: the first n-type doping district, the second n-type doping district and the external district of N-type；
Wherein, the subregion being positioned at polysilicon gate both sides in described first n-type doping district and the second n-type doping district respectively described p-well is formed after the 4th adulterates；
The external district of described N-type is formed after the side in the region of the second doping carries out the 4th doping away from described diode in the region of the first doping at described diode；Described diode through second doping region and through the 4th doping region between interval predeterminable range；Described 4th is doped to N doping.
Further, the concentration of described 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of described 4th doping is 2E15-8E15 atom/square centimeter.
In MOS circuit fabrication method provided by the invention and MOS circuit, after oxide layer forms polycrystalline silicon membrane, polycrystalline silicon membrane is carried out the first doping and etching technics, the first polysilicon resistance and the second polysilicon resistance are concurrently formed, second polysilicon resistance is carried out the second doping and can form diode, such diode and the first polysilicon resistance only can be formed with twice doping process, diode and resistance need not be respectively provided with photoetching, doping process, the manufacture efficiency of MOS circuit can be improved, and reduce process costs.
Accompanying drawing explanation
The flow chart of the MOS circuit fabrication method that Fig. 1 provides for the embodiment of the present invention one；
Electrical block diagram after depositing polysilicon rete in the MOS circuit fabrication method that Fig. 2 provides for the embodiment of the present invention one；
The MOS circuit fabrication method that Fig. 3 provides for the embodiment of the present invention one carries out the electrical block diagram after the first doping；
Electrical block diagram after performing etching in the MOS circuit fabrication method that Fig. 4 provides for the embodiment of the present invention one；
The MOS circuit fabrication method that Fig. 5 provides for the embodiment of the present invention one carries out the electrical block diagram after the second doping；
The flow chart of the MOS circuit fabrication method that Fig. 6 provides for the embodiment of the present invention two；
Electrical block diagram after depositing polysilicon rete in the MOS circuit fabrication method that Fig. 7 provides for the embodiment of the present invention two；
The MOS circuit fabrication method that Fig. 8 provides for the embodiment of the present invention two carries out the electrical block diagram after the first doping；
The MOS circuit fabrication method that Fig. 9 provides for the embodiment of the present invention two carries out the electrical block diagram after the 3rd doping；
Electrical block diagram after performing etching in the MOS circuit fabrication method that Figure 10 provides for the embodiment of the present invention two；
The MOS circuit fabrication method that Figure 11 provides for the embodiment of the present invention two carries out the electrical block diagram after the second doping；
The MOS circuit fabrication method that Figure 12 provides for the embodiment of the present invention two carries out the electrical block diagram after the 4th doping；
The flow chart of the MOS circuit fabrication method that Figure 13 provides for the embodiment of the present invention three.
Accompanying drawing labelling:
1-substrate 2-well region 201-N trap
202-P trap 3-oxide layer 301-gate oxide
302-field oxide 4-polycrystalline silicon membrane 5-the first polysilicon resistance
6-the second polysilicon resistance 7-diode 8-polysilicon gate
9-the first n-type doping district 10-the second n-type doping district 11-the oneth P type doped region
The external district of 12-the 2nd P type doped region 13-P type
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Embodiment one
The flow chart of the MOS circuit fabrication method that Fig. 1 provides for the embodiment of the present invention one.As it is shown in figure 1, the MOS circuit fabrication method that the present embodiment provides, including:
Step 101, on substrate 1 formation well region 2, form oxide layer 3 on well region 2.
Wherein, well region 2 can include N trap and/or p-well, p-well and N trap respectively lightly doped P-type semiconductor and N-type semiconductor；Oxide layer 3 is made up of silicon oxide, specifically can including gate oxide and field oxide, the region that field oxide covers is place, and the region outside place is active area, active area is the groundwork region of semiconductor device, and the Main Function of place is in that the isolation between adjacent semiconductor bodies.
Step 102, in oxide layer 3, deposit unadulterated polycrystalline silicon membrane 4.
Wherein, the technical process forming well region 2, oxide layer 3 and polycrystalline silicon membrane 4 on substrate 1 is similar with technical process of the prior art, repeats no more herein.Electrical block diagram after depositing polysilicon rete 4 in the MOS circuit fabrication method that Fig. 2 provides for the present embodiment.
Step 103, polycrystalline silicon membrane 4 is carried out the first doping.
Specifically, it is possible to adopt ion implantation technology that unadulterated polycrystalline silicon membrane 4 carries out the first doping, form the polycrystalline silicon membrane 4 with certain resistance.The MOS circuit fabrication method that Fig. 3 provides for the present embodiment carries out the electrical block diagram after the first doping.
Step 104, polycrystalline silicon membrane 4 is carried out photoetching, etching, form the first polysilicon resistance 5 and the second polysilicon resistance 6.
Adopt photoetching, etching technics, it is possible in the polycrystalline silicon membrane 4 have certain resistance, become the first polysilicon resistance 5 and the second polysilicon resistance 6.First polysilicon resistance 5, is the polysilicon resistance with certain resistance commonly used in MOS circuit, and its resistance is determined by the concentration of the first doping.The resistance of resistance can be adjusted by regulating the concentration of the first doping.Electrical block diagram after performing etching in the MOS circuit fabrication method that Fig. 4 provides for the present embodiment.
Step 105, side to the second polysilicon resistance 6 carry out the second doping.
Wherein, the concentration of the second doping is more than the concentration of the first doping.
First is doped to N doping, and second is doped to P doping；Or, first is doped to P doping, and second is doped to N doping.
Specifically, it is possible to adopt photoetching, ion implanting (or ion diffusion) technique that the side of the second polysilicon resistance 6 is carried out the second doping.The MOS circuit fabrication method that Fig. 5 provides for the present embodiment carries out the electrical block diagram after the second doping.
If first is doped to N doping, then doped chemical can be phosphorus, arsenic or antimony, and correspondingly, second is doped to P doping, and doped chemical can be boron.Second polysilicon resistance 6 passes through N doping in step 103, become N-type semiconductor, in step 105 the side of the second polysilicon resistance 6 is carried out P doping, owing to the concentration of P doping is higher than the N concentration adulterated, therefore, this side becomes P-type semiconductor, N-type semiconductor and P-type semiconductor after P adulterates and namely constitutes PN junction, forms diode 7 conventional in MOS circuit.The burning voltage of diode can be adjusted by regulating the concentration of the first doping and the second doping.
If first is doped to P doping, second is doped to N doping, then without the P pole that side is diode of the second doping in the second polysilicon resistance 6, through the N pole that side is diode of the second doping.
After step 105, in addition it is also necessary to experience annealing process, contact hole processing technology, metal lead wire processing technology etc., these processing steps are all identical with existing method, and are all common process well known in the art, therefore do not repeat.
In the MOS circuit fabrication method that the present embodiment provides, after oxide layer 3 forms polycrystalline silicon membrane 4, polycrystalline silicon membrane 4 is carried out the first doping and etching technics, concurrently form the first polysilicon resistance 5 and the second polysilicon resistance 6, second polysilicon resistance 6 is carried out the second doping and can form diode 7, such diode 7 and the first polysilicon resistance 5 only can be formed with twice doping process, diode 7 and resistance need not be respectively provided with photoetching, doping process, the manufacture efficiency of MOS circuit can be improved, and reduce process costs.
Resistance conventional in MOS circuit and diode are high value resistor and Zener diode.High value resistor refers generally to the square resistance scope resistance more than 500 ohms/square, owing to its temperature characterisitic, voltage characteristic are all better, is therefore widely used in MOS circuit；Zener diode is a kind of semiconductor device that can provide burning voltage, when burning voltage is less than 5 volts, its temperature coefficient is negative, when burning voltage is more than 6 volts, its temperature coefficient is just, so in MOS circuit the most frequently used to be burning voltage at the 5-6 Zener diode lied prostrate, now temperature coefficient is close to zero.
On the basis of the technical scheme of embodiment one offer, preferably, the doping content of the first doping is 1E14-1E15 atom/square centimeter, the doping content of the second doping is 2E15-8E15 atom/square centimeter, the first polysilicon resistance 5 so formed is in the high value resistor between 500-5000 ohms/square for square resistance, and diode 7 is in the Zener diode between 5V-6V for burning voltage.
Embodiment two
The flow chart of the MOS circuit fabrication method that Fig. 6 provides for the embodiment of the present invention two.As shown in Figure 6, the MOS circuit fabrication method that the present embodiment provides, including:
Step 201, form well region on substrate 1, well region is formed oxide layer.
Specifically, well region includes N trap 201 and p-well 202, and oxide layer includes gate oxide 301 and field oxide 302.N trap 201 and p-well 202 are respectively formed with gate oxide 301, between gate oxide 301, form field oxide 302.
Step 202, in oxide layer, deposit unadulterated polycrystalline silicon membrane 4.
Electrical block diagram after depositing polysilicon rete 4 in the MOS circuit fabrication method that Fig. 7 provides for the present embodiment.
Step 203, polycrystalline silicon membrane 4 is carried out the first doping.
Specifically, it is possible to adopt ion implantation technology that unadulterated polycrystalline silicon membrane 4 carries out the first doping, form the polycrystalline silicon membrane 4 with certain resistance.The MOS circuit fabrication method that Fig. 8 provides for the present embodiment carries out the electrical block diagram after the first doping.
Step 204, polycrystalline silicon membrane 4 to gate oxide 301 surface carry out the 3rd doping.
Specifically, it is possible to adopt photoetching, ion implanting (or ion diffusion) technique that the polycrystalline silicon membrane 4 on gate oxide 301 surface is carried out the 3rd doping.The doped dielectric of the 3rd doping can be identical with the first doping, it is also possible to different.This step mainly for forming the polycrystalline silicon membrane 4 that doping content is higher on gate oxide 301, in order to subsequent etching goes out polysilicon gate.The MOS circuit fabrication method that Fig. 9 provides for the present embodiment carries out the electrical block diagram after the 3rd doping.
Step 205, polycrystalline silicon membrane 4 is carried out photoetching, etching, form the first polysilicon resistance the 5, second polysilicon resistance 6 and polysilicon gate 8.
Specifically, it is possible on field oxide 302, etch the first polysilicon resistance 5 and the second polysilicon resistance 6, the gate oxide 301 of N trap 201 and p-well 202 etches polysilicon gate 8 respectively.Electrical block diagram after performing etching in the MOS circuit fabrication method that Figure 10 provides for the present embodiment.
Step 206, the subregion being positioned at polysilicon gate 8 both sides in the side of the second polysilicon resistance 6 and p-well 202 is carried out the second doping respectively.
Wherein, second be doped to N doping, correspondingly, first be doped to P doping, and second doping concentration more than first doping concentration.The side of the second polysilicon resistance 6 is that P adulterates, side is N doping, forms PN junction, namely constitutes diode 7.
The side of the second polysilicon resistance 6 is carried out the second doping at the same time it can also be the subregion being positioned at polysilicon gate 8 both sides in p-well 202 carries out the second doping respectively, form the first n-type doping district 9 and the second n-type doping district 10.Gate oxide 301 in first the 9, second n-type doping district 10 of n-type doping district, p-well 202 and p-well 202 constitutes NMOS together with polysilicon gate 8.The MOS circuit fabrication method that Figure 11 provides for the present embodiment carries out the electrical block diagram after the second doping.
Step 207, opposite side to the subregion and the second polysilicon resistance 6 that are positioned at polysilicon gate 8 both sides in N trap 201 carry out the 4th doping.
Wherein, the 4th be doped to P doping, and, in the second polysilicon resistance 6 through second doping part and through the 4th doping part between interval predeterminable range.
Specifically, after the side of the second polysilicon resistance 6 carries out the second doping, form diode 7, photoetching, ion implantation technology then can be adopted in the side of diode P pole to carry out the 4th doping again, form the external district of P type, facilitate the external metal lead wire of diode 7.Diode 7 is carried out the 4th doping at the same time it can also be the subregion that is positioned at polysilicon gate 8 both sides in N trap 201 carries out the 4th doping respectively, form P type doped region 11 and a 2nd P type doped region 12.Gate oxide 301 on oneth P type doped region the 11, the 2nd P type doped region 12, N trap 201 and N trap 201 constitutes PMOS together with polysilicon gate 8.The MOS circuit fabrication method that Figure 12 provides for the present embodiment carries out the electrical block diagram after the 4th doping.
By above-mentioned steps 201 to step 207, the MOS circuit including NMOS, PMOS, diode and resistance namely can be formed.
In the MOS circuit fabrication method that the present embodiment provides, NMOS, PMOS, diode and high value resistor are by once etching formation, and while forming the N pole of diode 7, form first n-type doping district 9 and the second n-type doping district 10 of NMOS, while forming the external district of P type of diode 7, form P type doped region 11 and a 2nd P type doped region 12 of PMOS, such NMOS, PMOS, diode and resistance only can be formed with once etching and four doping process, all parts need not be respectively provided with photoetching, etching and doping process, the manufacture efficiency of MOS circuit can be improved further, and reduce process costs.
Embodiment three
The flow chart of the MOS circuit fabrication method that Figure 13 provides for the embodiment of the present invention three.As shown in figure 13, the MOS circuit fabrication method that the present embodiment provides, including:
Step 301, on substrate formed well region, on well region formed oxide layer.
Step 302, in oxide layer, deposit unadulterated polycrystalline silicon membrane.
Step 303, polycrystalline silicon membrane is carried out the first doping.
Wherein, first it is doped to N doping.
Step 304, polycrystalline silicon membrane to gate oxide surface carry out the 3rd doping.
Step 305, polycrystalline silicon membrane is carried out photoetching, etching, form the first polysilicon resistance, the second polysilicon resistance and polysilicon gate.
Step 306, the subregion being positioned at polysilicon gate both sides in the side of the second polysilicon resistance and N trap is carried out the second doping respectively.
Wherein, second is doped to P doping, and the concentration of the second doping is more than the concentration of the first doping.The side of the second polysilicon resistance is that P adulterates, side is N doping, forms PN junction, namely constitutes diode.The side of the second polysilicon resistance is carried out the second doping at the same time it can also be the subregion being positioned at polysilicon gate both sides in N trap carries out the second doping respectively, form a P type doped region and the 2nd P type doped region.Gate oxide on oneth P type doped region, the 2nd P type doped region, N trap and N trap constitutes PMOS together with polysilicon gate.
Step 307, opposite side to the subregion and the second polysilicon resistance that are positioned at polysilicon gate both sides in p-well carry out the 4th doping.
Wherein, the 4th it is doped to N doping；In second polysilicon resistance through second doping part and through the 4th doping part between interval predeterminable range.
After the side of the second polysilicon resistance carries out the second doping, form diode, carry out the 4th doping in the side of diode N pole again, form the external district of N-type, facilitate the external metal lead wire of diode.
Diode is carried out the 4th doping at the same time it can also be the subregion being positioned at polysilicon gate both sides in p-well carries out the 4th doping respectively, form the first n-type doping district and the second n-type doping district.Gate oxide in first n-type doping district, the second n-type doping district, p-well and p-well constitutes NMOS together with polysilicon gate.
In the MOS circuit fabrication method that the present embodiment provides, the concrete methods of realizing of each step is similar with each step in embodiment two, the difference is that only: in the present embodiment, first is doped to N doping, second doping and the 4th is doped to P doping, the external district formed on diode is the external district of N-type, all the other each steps are all identical with embodiment two with function, repeat no more herein.
On the basis of above-described embodiment two and the technical scheme of embodiment three offer, it is preferred that the concentration of the 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of the 4th doping is 2E15-8E15 atom/square centimeter, it is possible to meet PMOS, NOMS and the conduction needs in the external district of diode.
Embodiment four
The embodiment of the present invention four provides a kind of MOS circuit, including:
Substrate, form well region on substrate, the oxide layer formed on well region and form the first polysilicon resistance in oxide layer and diode；
First polysilicon resistance is the polysilicon through the first doping；
Diode is side through first adulterating, opposite side is through the polysilicon of the second doping；
Wherein, the concentration of the second doping is more than the concentration of the first doping；
First is doped to N doping, and second is doped to P doping；Or, first is doped to P doping, and second is doped to N doping.
The MOS circuit that the present embodiment provides, it is possible to use the method for embodiment one is formed, and its concrete structure is referred to structure shown in Fig. 5.
The MOS circuit that the present embodiment provides, first polysilicon resistance is that polysilicon is formed after first adulterates, diode is that polysilicon side is formed after second adulterates through the first doping, opposite side, therefore diode and the first polysilicon resistance only can be formed with twice doping process, diode and resistance need not be respectively provided with photoetching, doping process, manufacture efficiency higher, and process costs is relatively low.
On the basis of the technical scheme of above-described embodiment offer, it is preferred that the doping content of the first doping is 1E14-1E15 atom/square centimeter；The doping content of the second doping is 2E15-8E15 atom/square centimeter.
On the basis of the technical scheme of above-described embodiment offer, it is preferred that described MOS circuit also includes: polysilicon gate；
Oxide layer includes gate oxide and field oxide；
First polysilicon resistance and diode are positioned on field oxide；
Polysilicon gate is positioned on gate oxide；
Polysilicon gate is the polysilicon through the first doping and the 3rd doping.
On the basis of the technical scheme of above-described embodiment offer, it is preferred that well region includes N trap and p-well；
N trap and p-well are respectively formed with gate oxide, between gate oxide, are formed with field oxide；
The gate oxide of N trap and p-well is respectively formed with polysilicon gate.
On the basis of the technical scheme of above-described embodiment offer, it is preferred that described MOS circuit also includes:
First n-type doping district, the second n-type doping district, a P type doped region, the 2nd P type doped region and the external district of P type；Wherein, the subregion being positioned at polysilicon gate both sides in the first n-type doping district and the second n-type doping district respectively p-well is formed after second adulterates；Second is doped to N doping.The subregion being positioned at polysilicon gate both sides in oneth P type doped region and the 2nd P type doped region respectively N trap is formed after the 4th adulterates；The external district of P type is formed after the side in the region of the second doping carries out the 4th doping away from diode in the region of the first doping at diode；Diode through second doping region and through the 4th doping region between interval predeterminable range；4th is doped to P doping.
Or,
Described MOS circuit also includes: the first n-type doping district, the second n-type doping district, a P type doped region, the 2nd P type doped region and the external district of N-type；Wherein, the subregion being positioned at polysilicon gate both sides in a P type doped region and the 2nd P type doped region respectively N trap is formed after second adulterates；Second is doped to P doping.The subregion being positioned at polysilicon gate both sides in first n-type doping district and the second n-type doping district respectively p-well is formed after the 4th adulterates；The external district of N-type is formed after the side in the region of the second doping carries out the 4th doping away from diode in the region of the first doping at diode；Diode through second doping region and through the 4th doping region between interval predeterminable range；4th is doped to N doping.
On the basis of the technical scheme of above-described embodiment offer, it is preferred that the concentration of the 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of the 4th doping is 2E15-8E15 atom/square centimeter.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein some or all of technical characteristic is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (18)
1. a MOS circuit fabrication method, it is characterised in that including:
Substrate is formed well region, described well region is formed oxide layer；
Described oxide layer deposits unadulterated polycrystalline silicon membrane；
Described polycrystalline silicon membrane is carried out the first doping；
Described polycrystalline silicon membrane is carried out photoetching, etching, forms the first polysilicon resistance and the second polysilicon resistance；
The side of described second polysilicon resistance is carried out the second doping；
Wherein, the concentration of described second doping is more than the concentration of described first doping；
Described first is doped to N doping, and second is doped to P doping；Or, described first is doped to P doping, and second is doped to N doping.
2. method according to claim 1, it is characterised in that the doping content of described first doping is 1E14-1E15 atom/square centimeter；The doping content of described second doping is 2E15-8E15 atom/square centimeter.
3. method according to claim 1, it is characterised in that described oxide layer includes gate oxide and field oxide；
After described polycrystalline silicon membrane is carried out the first doping, also include:
The polycrystalline silicon membrane on described gate oxide surface is carried out the 3rd doping；
Described described polycrystalline silicon membrane is carried out photoetching, etching, forms the first polysilicon resistance and the second polysilicon resistance, specifically include:
Described polycrystalline silicon membrane is carried out photoetching, etching, described field oxide is formed the first polysilicon resistance and the second polysilicon resistance, described gate oxide is formed polysilicon gate.
4. method according to claim 3, it is characterised in that described well region includes N trap and p-well；
Described formation oxide layer on described well region, specifically includes:
Described N trap and p-well form gate oxide respectively, between described gate oxide, forms field oxide；
Described formation polysilicon gate on described gate oxide, specifically includes:
The gate oxide of described N trap and p-well forms polysilicon gate respectively.
5. method according to claim 4, it is characterised in that the described side to described second polysilicon resistance also includes while carrying out the second doping:
The subregion being positioned at polysilicon gate both sides in described p-well is carried out the second doping respectively；
Wherein, described second it is doped to N doping.
6. method according to claim 5, it is characterised in that after carrying out the second doping, also include:
The opposite side of the subregion and the second polysilicon resistance that are positioned at described polysilicon gate both sides in described N trap is carried out the 4th doping；
Wherein, the described 4th it is doped to P doping；In described second polysilicon resistance through second doping part and through the 4th doping part between interval predeterminable range.
7. method according to claim 4, it is characterised in that the described side to described second polysilicon resistance also includes while carrying out the second doping:
The subregion being positioned at polysilicon gate both sides in described N trap is carried out the second doping respectively；
Wherein, described second it is doped to P doping.
8. method according to claim 7, it is characterised in that after carrying out the second doping, also include:
The opposite side of the subregion and the second polysilicon resistance that are positioned at described polysilicon gate both sides in described p-well is carried out the 4th doping；
Wherein, the described 4th it is doped to N doping；In described second polysilicon resistance through second doping part and through the 4th doping part between interval predeterminable range.
9. the method according to claim 6 or 8, it is characterised in that the concentration of described 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of described 4th doping is 2E15-8E15 atom/square centimeter.
10. a MOS circuit, it is characterised in that including: substrate, form well region over the substrate, the oxide layer formed on described well region and form the first polysilicon resistance in described oxide layer and diode；
Described first polysilicon resistance is the polysilicon through the first doping；
Described diode is side through first adulterating, opposite side is through the polysilicon of the second doping；
Wherein, the concentration of described second doping is more than the concentration of described first doping；
Described first is doped to N doping, and second is doped to P doping；Or, described first is doped to P doping, and second is doped to N doping.
11. circuit according to claim 10, it is characterised in that the doping content of described first doping is 1E14-1E15 atom/square centimeter；The doping content of described second doping is 2E15-8E15 atom/square centimeter.
12. circuit according to claim 10, it is characterised in that also include: polysilicon gate；
Described oxide layer includes gate oxide and field oxide；
Described first polysilicon resistance and diode are positioned on described field oxide；
Described polysilicon gate is positioned on described gate oxide；
Described polysilicon gate is the polysilicon through the first doping and the 3rd doping.
13. circuit according to claim 12, it is characterised in that described well region includes N trap and p-well；
Described N trap and p-well are respectively formed with gate oxide, between described gate oxide, are formed with field oxide；
The gate oxide of described N trap and p-well is respectively formed with polysilicon gate.
14. circuit according to claim 13, it is characterised in that also include: the first n-type doping district and the second n-type doping district；
Wherein, the subregion being positioned at polysilicon gate both sides in described first n-type doping district and the second n-type doping district respectively described p-well is formed after second adulterates；Described second is doped to N doping.
15. circuit according to claim 14, it is characterised in that also include: a P type doped region, the 2nd P type doped region and the external district of P type；
Wherein, the subregion being positioned at polysilicon gate both sides in a described P type doped region and the 2nd P type doped region respectively described N trap is formed after the 4th adulterates；
The described external district of P type is formed after the side in the region of the second doping carries out the 4th doping away from described diode in the region of the first doping at described diode；Described diode through second doping region and through the 4th doping region between interval predeterminable range；Described 4th is doped to P doping.
16. circuit according to claim 13, it is characterised in that also include: a P type doped region and the 2nd P type doped region；
Wherein, the subregion being positioned at polysilicon gate both sides in a described P type doped region and the 2nd P type doped region respectively described N trap is formed after second adulterates；Described second is doped to P doping.
17. circuit according to claim 16, it is characterised in that also include: the first n-type doping district, the second n-type doping district and the external district of N-type；
Wherein, the subregion being positioned at polysilicon gate both sides in described first n-type doping district and the second n-type doping district respectively described p-well is formed after the 4th adulterates；
The external district of described N-type is formed after the side in the region of the second doping carries out the 4th doping away from described diode in the region of the first doping at described diode；Described diode through second doping region and through the 4th doping region between interval predeterminable range；Described 4th is doped to N doping.
18. the circuit according to claim 15 or 17, it is characterised in that the concentration of described 3rd doping is 5E15-1.5E16 atom/square centimeter；The concentration of described 4th doping is 2E15-8E15 atom/square centimeter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018040563A1 (en) * | 2016-08-31 | 2018-03-08 | 佛山芯光半导体有限公司 | Novel polycrystalline silicon thin-film zener diode and fabrication method therefor |
| CN113643982A (en) * | 2021-08-12 | 2021-11-12 | 深圳市芯电元科技有限公司 | MOSFET chip manufacturing method for improving grid characteristics |
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| US5589415A (en) * | 1995-06-07 | 1996-12-31 | Sgs-Thomson Microelectronics, Inc. | Method for forming a semiconductor structure with self-aligned contacts |
| CN101710579A (en) * | 2009-10-16 | 2010-05-19 | 上海广电光电子有限公司 | Manufacturing method of thin film transistor array substrate |
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| JPH07202191A (en) * | 1993-12-29 | 1995-08-04 | Ricoh Co Ltd | Vertical power mos semiconductor and manufacture thereof |
| US5589415A (en) * | 1995-06-07 | 1996-12-31 | Sgs-Thomson Microelectronics, Inc. | Method for forming a semiconductor structure with self-aligned contacts |
| CN101710579A (en) * | 2009-10-16 | 2010-05-19 | 上海广电光电子有限公司 | Manufacturing method of thin film transistor array substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018040563A1 (en) * | 2016-08-31 | 2018-03-08 | 佛山芯光半导体有限公司 | Novel polycrystalline silicon thin-film zener diode and fabrication method therefor |
| CN113643982A (en) * | 2021-08-12 | 2021-11-12 | 深圳市芯电元科技有限公司 | MOSFET chip manufacturing method for improving grid characteristics |
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