CN105743536A - Radio frequency controller and radio frequency timing control method - Google Patents
Radio frequency controller and radio frequency timing control method Download PDFInfo
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- CN105743536A CN105743536A CN201410756605.3A CN201410756605A CN105743536A CN 105743536 A CN105743536 A CN 105743536A CN 201410756605 A CN201410756605 A CN 201410756605A CN 105743536 A CN105743536 A CN 105743536A
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Abstract
The invention relates to the field of mobile communication and discloses a radio frequency controller and a radio frequency timing control method. The radio frequency controller comprises a time generation module, a public timing module and a sequential processing module. A fast clock generation unit of the clock generation module generates fast clock signals, wherein the clock frequency of the fast clock signals is no less than the clock frequency of any time clock signal of multiple kinds of clock signals; a first timing unit of the public timing module generates fast clock timing information according to the fast clock signals; the sequential processing module executes current radio frequency transceiving events according to the fast clock timing information and current instruction information stored inside the sequential processing module. The current instruction information comprises multiple fast clock waiting durations which are obtained by converting multiple current communication mode waiting durations corresponding to the current radio frequency transceiving events according to a fast clock conversion ratio corresponding to the current communication mode. Thereby, the hardware complexity of multi-mode communication systems is simplified and the extensibility of the multi-mode communication systems is enhanced.
Description
Technical field
The present invention relates to moving communicating field, particularly to a kind of rf control unit being applied to multi-mode communication system and radio frequency time control method.
Background technology
In current 4G mobile communication system, there is various wireless communication pattern and deposit, for instance GSM, TD-SCDMA, WCDMA, LTE and CDMA2000 etc..There is the timing information that two classes are basic in physical layer software, a class is a set of distinctive timing of each pattern, another kind of measures for anomalous mode formula, the transmitting-receiving events conflict of multi-mode and multi-standby detects and the common timing of scene of sequence etc..This two classes timing all can be used when radio frequency chip (RFIC) is controlled, and two class timings also need to be mutually in step.
In baseband chip, it will usually have the unit of a hardware to generate these timing informations, and the information of these timings all can be used for radio frequency timing controlled.For GSM, TD-SCDMA and LTE three modular system, the structure of the rf control unit in baseband chip is as shown in Figure 1.RF timing control unit is segmented into four ingredients, 10, four time block 11a～11d of clock generating module, sequential processing module 12 and peripheral control interface module 13.Clock generating module 10 produces multiple clock source, is 4.33M, 10.24M, 30.72M and 26M respectively, and is separately input into four time blocks: GSM time block 11a, TDS time block 11b, LTE time block 11c, common timing module 11d.Time block 11a～11c belongs to the peculiar timing of access module, a set of distinctive timing that namely each pattern has.The timing information of common timing module 11d is used to synchronize each access module timing, and its precision is low relative to the requirement of access module.
As it has been described above, although existing method can meet the needs of the RF timing of each access module very well, the problem also simultaneously being able between solution pattern the synchronization of timing, but, clock generating module relative complex, it is desirable to have multiple clock type.If several clock frequencies do not have multiple proportion, then be accomplished by multiple PLL (frequency phase lock ring) and realize, thus can increase the area (cost) of baseband chip, add the power consumption of time block simultaneously.Furthermore, add the kind of time block, it is achieved the complexity of logic is consequently increased；Accordingly, it is contemplated that the problem that the chip that between different clocks bus, synchronization etc. are actual realizes, the difficulty of the clock network design of baseband chip is too increased.The autgmentability of system, if increasing a kind of wireless-access mode, and the timing base of this pattern is different with existing pattern, so will in clock generating module, time block increases corresponding unit, need to redesign chip and corresponding drive software, thus limit the autgmentability of chip platform.
Furthermore, it is contemplated that the needs of the power saving of communication system, when not having radio-frequency receiving-transmitting operation, transceiver being allowed to enter the state of low-power consumption, power supply and the fast clock of remaining major part module of system can be closed.In order to ensure that Wireless Telecom Equipment (such as handheld terminal) synchronizes on base station time, need a timing means and guarantee that (sleep state) remains able to continue timing when system enters low-power consumption, but itself is then very low with the power consumption on corresponding link.Therefore, each there is the slow clock calibration circuit of correspondence to calibrate slow clock signal inside four time blocks.But, owing to four time blocks are each independent so that realizing of four time block calibrations is incomplete same, the form of calibration output result is also inconsistent.
Summary of the invention
It is an object of the invention to provide a kind of rf control unit and radio frequency time control method, not only simplify hard-wired complexity in multi-mode communication system, and strengthen the autgmentability of multi-mode communication system.
For solving above-mentioned technical problem, embodiments of the present invention provide a kind of rf control unit, it is applied to multi-mode communication system, plurality of communication schemes corresponds respectively to multiple clock signal, comprise: clock generating module, comprising fast clock generating unit, described fast clock generating unit is used for producing fast clock signal, and the clock frequency of described fast clock signal is not less than in described multiple clock signal the clock frequency of any one clock signal；Common timing module, comprises the first timing unit, and described first timing unit is connected to described fast clock generating unit to produce fast clock timing information according to described fast clock signal；Sequential processing module, it is connected to described first timing unit, the present instruction information and executing current radio frequency transmitting-receiving event that described sequential processing module stores according to described fast clock timing information and this sequential processing inside modules, wherein, described present instruction information comprises multiple fast clock waiting time, each communication pattern has the fast clock conversion ratio of correspondence, described current radio frequency transmitting-receiving event is corresponding to current communication mode, the plurality of fast clock waiting time receives and dispatches conversion of multiple current communication mode waiting times corresponding to event according to the fast clock conversion ratio that described current communication mode is corresponding with described current radio frequency and obtains..
Embodiments of the present invention additionally provide a kind of radio frequency time control method, it is applied to comprise the multi-mode communication system of rf control unit, described rf control unit comprises the clock generation module being sequentially connected with, common timing module and sequential processing module, described clock generation module is used for producing fast clock signal, described common timing module is for producing fast clock timing information according to described fast clock signal, comprise the steps of described central processing unit current communication mode belonging to current radio frequency transmitting-receiving event and described current radio frequency transmitting-receiving event is resolved to present instruction information, described present instruction information comprises multiple current communication mode waiting time；Described central processing unit obtains the fast clock conversion ratio that this current communication mode of its internal reservoir is corresponding；The plurality of current communication mode waiting time is converted into multiple fast clock waiting time according to described fast clock conversion ratio by described central processing unit；Described present instruction information is downloaded to described sequential processing module by described central processing unit, and wherein, described sequential processing module is according to described fast clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing.
Embodiment of the present invention is in terms of existing technologies, the clock generating module provided in the present invention comprises fast clock generating unit, the clock frequency of fast clock signal that described fast clock generating unit produces is not less than in the multiple clock signal that plurality of communication schemes is corresponding the clock frequency of any one clock signal, and the present instruction information that sequential processing inside modules stores comprises multiple fast clock waiting time, each communication pattern has the fast clock conversion ratio of correspondence, described current radio frequency transmitting-receiving event is corresponding to current communication mode, the plurality of fast clock waiting time receives and dispatches conversion of multiple current communication mode waiting times corresponding to event according to the fast clock conversion ratio that described current communication mode is corresponding with described current radio frequency and obtains.Thus, a common timing module is used to replace the multiple time blocks corresponding respectively to plurality of communication schemes in prior art, and be implemented under different communication modes perform radio-frequency receiving-transmitting event by being converted into multiple fast clock waiting time multiple current communication mode waiting times, not only simplify hard-wired complexity in multi-mode communication system, and strengthen the autgmentability of multi-mode communication system, namely, when system needs to newly increase a kind of communication pattern, without redesigning the circuit structure of the rf control unit of system, and the conversion of corresponding timing information only need to be done by the central processing unit of system.
Additionally, described clock generation module also comprises slow clock generating unit, described slow clock generating unit is used for producing slow clock signal, described common timing module also comprises slow clock calibration unit, described slow clock calibration unit is connected to described fast clock generating unit and described slow clock generating unit, and described slow clock calibration unit is in order to produce slow clock alignment ratio according to described fast clock signal and described slow clock signal.Owing to only using a common timing module, therefore only need to be arranged in correspondence with a slow clock calibration unit, and export a kind of calibration form, and avoid multiple time blocks in prior art and need to be arranged in correspondence with multiple slow clock calibration unit, export multiple calibration form.Thus, not only further simplify the hardware of system and realize, and make the calibration time of system obtain unification.
Additionally, described common timing module also comprises the second timing unit, it is connected to described slow clock generating unit and described sequential processing module, described second timing unit produces slow clock timing information according to described slow clock signal, and described sequential processing module is according to described slow clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing.Present embodiment adopts the reference mode of second order timing, when sequential processing module to perform that between the operation of two continuous print, interval time is longer, switch to the timing information receiving slow clock timing information as sequencing contro, thus adding the flexibility ratio of radio frequency sequencing contro.
Accompanying drawing explanation
Fig. 1 is the block diagram of timing control unit rf control unit of the prior art；
Fig. 2 is the block diagram of rf control unit according to the first embodiment of the invention；
Fig. 3 is the block diagram of rf control unit second embodiment of the invention；
Fig. 4 is the flow chart of the radio frequency time control method of the 3rd embodiment according to the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the embodiments of the present invention are explained in detail.But, it will be understood by those skilled in the art that in each embodiment of the present invention, propose many ins and outs in order to make reader be more fully understood that the application.But, even without these ins and outs with based on the many variations of following embodiment and amendment, it is also possible to realize the application each claim technical scheme required for protection.
First embodiment of the present invention relates to a kind of rf control unit, is applied to multi-mode communication system.As in figure 2 it is shown, rf control unit 1 comprises clock generating module 10, common timing module 11, sequential processing module 12 and peripheral interface module 13.Common timing module 11 is connected to clock generating module 10 and sequential processing module 12, and peripheral interface module 13 is connected to sequential processing module 12.
In present embodiment, clock generating module 10 comprises fast clock generating unit 101, slow clock generating unit 102, fast signal source of clock A and slow clock signal source B.Fast clock generating unit 101 is connected to fast signal source of clock A to produce fast clock signal clk 1.Wherein, fast signal source of clock A is such as the clock signal of conventional 26M.Specifically, multi-mode communication system can compatible plurality of communication schemes, and each communication pattern is corresponding to the clock signal of characteristic frequency, such as, gsm communication pattern corresponding to the clock signal of 4.33M, TD-SCDMA communication pattern corresponding to the clock signal of 10.24M, LTE communication pattern corresponding to the clock signal of 30.72M；The requirement of the time precision of sequencing contro is different by namely different communication patterns.Therefore, the fast clock signal clk 1 that fast clock generating unit 101 produces should disclosure satisfy that the requirement to the time precision of sequencing contro of each communication pattern of this multi-mode communication system compatibility.In present embodiment, this multi-mode communication system with compatible tri-kinds of communication patterns of GSM, TD-SCDMA, LTE for example, the clock signal selecting fast clock signal clk 1 to be 30.72M.That is, the signal source of clock of the 26M received is carried out the process of frequency multiplication and frequency dividing by fast clock generating unit 101, to produce the fast clock signal of 30.72M.But, this is not intended to be limited in any by present embodiment, those skilled in the art can select suitable fast clock signal clk 1 according to the different communication pattern that this communication system is compatible, as long as meeting the time precision time precision higher than the clock signal corresponding to each communication pattern of this fast clock signal clk 1.
Slow clock generating unit 102 is connected to slow clock signal source B to produce slow clock signal CLK2.Wherein, slow clock signal source B is such as the clock signal of conventional 32K.In present embodiment, slow clock signal CLK2 is set as the clock signal of 32K.But, this is not intended to be limited in any by present embodiment, and those skilled in the art can select suitable slow clock signal according to actual needs.
In present embodiment, common timing module 11 comprises the first timing unit 111 and slow clock calibration unit 112.First timing unit 111 is connected to fast clock generating unit 101, to produce fast clock timing information T1 according to fast clock signal clk 1.Specifically, the first timing unit 111 comprises an enumerator and multiple latch, and the fast clock signal clk 1 received is counted and passes through multiple latch and exports fast clock timing information T1 by enumerator.
Slow clock calibration unit 112 is connected to fast clock generating unit 101 and slow clock generating unit 102, to utilize fast clock signal clk 1 that slow clock signal CLK2 is verified.Specifically, slow clock calibration unit 112 is including at least fast clock counter, slow clock counter, multiple depositor and a computing unit.In multi-mode communication system normal operation time (namely in fast clock generating unit 101 works time), fast clock counter and slow clock counter are respectively used to fast clock signal clk 1 be counted with slow clock signal CLK2 and fast clock count value and slow clock count value is separately stored in depositor.Computing unit periodically uses fast clock signal clk 1 to measure slow clock signal CLK2, namely computing unit periodically calculates the interior fast clock count value of the same time period multiple relative to slow clock count value, and in this same time period, fast clock count value is slow clock alignment ratio relative to the multiple of slow clock count value.Slow clock calibration unit 112 is stored in the depositor that it is internal by slow clock calibration unit 112, using as the fast clock signal clk 1 calibration result to slow clock signal CLK2.When fast clock generating unit 101 is closed, after this slow clock alignment ratio can be used directly the state to enter low-power consumption as system, the slow clock counter of slow clock calibration unit 112 continues the reference of counting.Compared to existing technologies, owing to adopting a common timing module to instead of multiple time block in present embodiment, so it is only necessary that with a slow clock calibration unit 112, and export a kind of calibration form, not only simplify the hardware configuration of rf control unit, and the calibration time of system is obtained.
In present embodiment, sequential processing module 12 comprises multiple serial device 1～N, and each serial device is connected to the first timing unit 111.Each serial device present instruction information and executing current radio frequency transmitting-receiving event according to fast clock timing information T1 with its internal reservoir.Wherein, each serial device in sequential processing module 12 is also attached to fast clock generating unit 101, and each serial device receives fast clock signal clk 1 using as internal reference clock.Peripheral interface module 13 performs the multiple control signals produced in current radio frequency transmitting-receiving event procedure for output timing processing module 12.Peripheral interface module 13 such as comprises control DigRF interface, GPO/RFFE interface (RFFrontEndInterface), GPO (GeneralPurposeOutputPorts) interface, interruption (Interrupt) interface etc..It will be understood by those skilled in the art that about the concrete structure of sequential processing module 12 with peripheral interface module 13 and repeat no more herein.
Second embodiment of the invention relates to a kind of rf control unit, as shown in Figure 3, second embodiment and the first embodiment are roughly the same, main distinction part is in that: in second embodiment of the invention, common timing module 11 also comprises the second timing unit 113, is connected to each serial device of slow clock generating unit 102 and sequential processing module 12.Second timing unit 113 produces slow clock timing information according to slow clock signal CLK2.Wherein, each serial device in sequential processing module 12 is also attached to slow clock generating unit 102, and each serial device receives slow clock signal CLK2 using as internal reference clock.
In present embodiment, second timing unit 113 comprises an enumerator and multiple latch, the slow clock signal CLK2 received is carried out timing and exports the slow clock timing information T2 each serial device to sequential processing module 12 by multiple latch by enumerator, each serial device present instruction information and executing current radio frequency transmitting-receiving event according to fast clock timing information T1 with its internal reservoir, or the present instruction information and executing current radio frequency transmitting-receiving event according to slow clock timing information T2 with its internal reservoir.Specifically, it is separated by between two the continuous print operations performed when serial device M fast clock signal clk 1, when M is relatively larger time, the bit wide of serial device instruction Counter is likely to restricted and can not realize, M can be divided into P each CLK1 of CLK2 and Q, i.e. M=N*P+Q, wherein, N is the slow clock alignment ratio of slow clock calibration unit 112 internal reservoir, and namely interior fast clock count value of same time period is relative to the multiple of slow clock count value.Thus, serial device can operate by easier two continuous print realizing having long period interval by the individual fast clock count value of time delay P slow clock count value and Q.Compared to existing technologies, present embodiment adopts the reference mode of second order timing, and namely the timing information of common timing module 11 output is divided into two step-lengths: fast clock timing information T1 and slow clock timing information T2.Thus, when serial device to perform that between the operation of two continuous print, interval time is longer, switch to and receive the slow clock timing information T2 timing information as sequencing contro, to increase the flexibility ratio of radio frequency sequencing contro.But, to the number of the timing information that common timing module 11 exports, this is not intended to be limited in any present embodiment.In other embodiment, according to actual needs, the reference mode of multi-mode communication system other multistage timing all right, for instance three rank timings, quadravalence timing etc..
It is worth mentioning that, each module involved in above-mentioned two embodiment is logic module, and in actual applications, a logical block can be a physical location, can also be a part for a physical location, it is also possible to realize with the combination of multiple physical locations.Additionally, for the innovative part highlighting the present invention, do not introduced by the unit less close with solving technical problem relation proposed by the invention in above-mentioned two embodiment, but this is not intended that in present embodiment to be absent from other unit.
3rd embodiment of the present invention relates to a kind of radio frequency time control method, is applied to comprise the multi-mode communication system of rf control unit, and rf control unit is including at least the clock generation module being sequentially connected with, common timing module, sequential processing module.Clock generation module is used for producing fast clock signal and changes and slow clock signal.Common timing module for producing fast clock timing information and slow clock timing information respectively according to fast clock signal and slow clock signal, and exports fast clock timing information and slow clock timing information to sequential processing module.As shown in Figure 4, the radio frequency time control method that present embodiment provides comprises step S1 to step S7.
Step S1: this current radio-frequency receiving-transmitting event is resolved to present instruction information by central processing unit current communication mode belonging to current radio frequency transmitting-receiving event, comprises multiple current communication mode waiting time in present instruction information.
Specifically, central processing unit can process multiple radio-frequency receiving-transmitting event sequentially in time successively, and wherein, multiple radio-frequency receiving-transmitting events are likely to need to perform under multiple different communication pattern.Owing to various communication patterns have a set of distinctive timing mode, namely various communication patterns correspond respectively to the clock signal of multi-frequency, when central processing unit processes current radio frequency transmitting-receiving event, need the current communication mode belonging to this current radio-frequency receiving-transmitting event that this current radio-frequency receiving-transmitting event is resolved to present instruction information, present instruction information comprises multiple current communication mode waiting time.Wherein, this current communication mode waiting time refers to the clocking value that the clock signal corresponding to this current communication mode is calculated.Such as, the clock signal of gsm communication pattern correspondence 4.33M, then, and the waiting time calculated under gsm communication pattern be the clock signal adopting 4.33M as timing signal time corresponding clocking value.The specific number of current communication mode waiting time is received and dispatched the concrete operations content to perform of event according to current radio frequency and is determined.Such as, the current communication mode waiting time in current radio frequency transmitting-receiving event always has 6, respectively T1=31, T2=69, T3=58, T4=102, T5=100, T6=324.But this is not intended to be limited in any by present embodiment.
Step S2: central processing unit obtains the fast clock conversion ratio that this current communication mode of its internal reservoir is corresponding.
Specifically, central processing unit internal reservoir has communication pattern-fast clock conversion ratio table, represents the ratio of the frequency of the frequency of the fast clock signal clock signal corresponding with each communication pattern.In present embodiment, the frequency of fast clock signal is such as 30.72M, and the frequency of the clock signal that gsm communication system is corresponding is 4.33M, then the fast clock conversion ratio that gsm communication system is corresponding is 30.72M/4.33M=7.0947.As shown in table 1, for for the communication pattern of tri-communication systems of GSM, TD-SCDMA, LTE-fast clock conversion ratio table, wherein, the frequency of the clock signal that TD-SCDMA, LTE communication system are corresponding respectively 10.24M, 30.72M.
Table 1
| GSM | TD-SCDMA | LTE |
| Fast clock conversion ratio | 7.0947 | 3 | 1 |
Central processing unit inquires about, according to current communication mode, the fast clock conversion ratio that the communication pattern of its internal reservoir-fast clock conversion ratio watch is corresponding to obtain this current communication mode.
Step S3: multiple current communication mode waiting times are converted into multiple fast clock waiting time according to fast clock conversion ratio by central processing unit.That is, fast clock waiting time=fast clock conversion ratio * current communication mode waiting time.Such as, the waiting time T of 6 the gsm communication patterns enumerated in step S11～T6It is converted into 6 fast clock waiting time T of correspondence1'～T6' it is respectively as follows: T1'=220, T2'=490, T3'=411, T4'=724, T5'=709, T6'=2299.
Step S4: central processing unit judges whether have at least a fast clock waiting time in multiple fast clock waiting time more than preset duration, if so, then enters step S5, if it is not, then enter step S7.
Specifically, sequential processing module comprises multiple serial device, and the enumerator in each serial device instruction has certain bit wide, and namely enumerator has default maximum count value.Namely this preset duration may be set to this maximum count value, but the setting means of preset duration is not limited in any way by present embodiment.When fast clock waiting time exceedes preset duration, the enumerator in serial device instruction will correctly count, thus causing the instruction of serial device to perform mistake.For avoiding above-mentioned situation, central processing unit needs in the multiple fast clock waiting time judging present instruction information, if having at least a fast clock waiting time more than preset duration；If so, step S4 is then entered.Such as, when the maximum count value of the enumerator in serial device instruction is 899, namely when preset duration is 899, due to T6'=2299 > 899, then enter step S5.In other situation, namely when each fast clock waiting time is respectively less than or equal to preset duration, then it is directly entered step S7.
Step S5: central processing unit obtains slow clock alignment ratio from common timing module.
Specifically, the fast clock signal that common timing module is additionally operable to according to clock generation module produces periodically produces slow clock alignment ratio with slow clock signal and is stored in inside it by this slow clock alignment ratio.Wherein, the frequency of the frequency/slow clock signal of slow clock alignment ratio=fast clock signal.Such as, when the frequency of fast clock signal is 30.72M, when the frequency of slow clock signal is 32.768K, slow clock alignment ratio is 30.72M/32.768K=937.5.Central processing unit obtains this slow clock alignment ratio from common timing module.
Step S6: this fast clock waiting time is resolved into the combination of slow clock waiting time and fast clock waiting time by central processing unit according to slow clock alignment ratio.That is, being combined as of slow clock waiting time and fast clock waiting time: slow clock alignment ratio * slow clock waiting time+fast clock waiting time.According to step S4, it is possible to by fast clock waiting time T6'=2299 are decomposed into: T6'=937.5*2+424, i.e. be decomposed into the combination of 2 slow clock waiting times and 424 fast clock waiting times.
Step S7: present instruction information is downloaded to sequential processing module by central processing unit.Step S7 comprises sub-step S71 to sub-step S72.
Sub-step S71: central processing unit inquires about whether each serial device is in idle condition successively, if it is not, then repeat this step, if so, then enters sub-step S72.
Specifically, each serial device has idle condition identifier, when serial device performs radio-frequency receiving-transmitting event, idle condition identifier is such as 0 (or 1), represent that this serial device is in busy state, when serial device has performed a radio-frequency receiving-transmitting event, this idle condition identifier can be revised as 1 (or 0) by this serial device, represents that this serial device is in idle condition.Central processing unit inquires about the idle condition identifier of each serial device successively to determine whether that serial device is in idle condition, if each serial device is in busy state, then central processing unit repeats sub-step S71；If inquiring at least one of which serial device is idle condition, then enter sub-step S72.
Sub-step S72: present instruction information is downloaded to the serial device being currently at idle condition by central processing unit.That is, the present instruction information parsed is downloaded in this serial device being currently at idle condition checked out in sub-step S71 by central processing unit.
Thus, this serial device performs current radio frequency transmitting-receiving event according to this current command information.Specifically, the fast clock timing information that receives timing information by default is performed current radio frequency transmitting-receiving event by this serial device.When going to the combination that certain waiting time is slow clock waiting time and fast clock waiting time, then automatically switch to and receive slow clock timing information as the timing information performing this slow clock waiting time, after having performed this slow clock waiting time, again switch to and receive fast clock timing information as the timing information continuing operation.
The step of various methods divides above, is intended merely to description clear, it is achieved time can be merged into a step or some step is split, and is decomposed into multiple step, as long as comprising identical logical relation, all in the protection domain of this patent；To adding inessential amendment in algorithm or in flow process or introducing inessential design, but do not change the core design of its algorithm and flow process all in the protection domain of this patent.
It is seen that, present embodiment is the embodiment of the method corresponding with first, second embodiment, and present embodiment can be worked in coordination enforcement with first, second embodiment.The relevant technical details mentioned in first, second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the relevant technical details mentioned in present embodiment is also applicable in first, second embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiments of the invention, and in actual applications, it is possible in the form and details it is done various change, without departing from the spirit and scope of the present invention.
Claims (8)
1. a rf control unit, is applied to multi-mode communication system, and plurality of communication schemes corresponds respectively to multiple clock signal, it is characterised in that comprise:
Clock generating module, comprises fast clock generating unit, and described fast clock generating unit is used for producing fast clock signal, and the clock frequency of described fast clock signal is not less than in described multiple clock signal the clock frequency of any one clock signal；
Common timing module, comprises the first timing unit, and described first timing unit is connected to described fast clock generating unit to produce fast clock timing information according to described fast clock signal；
Sequential processing module, is connected to described first timing unit, the present instruction information and executing current radio frequency transmitting-receiving event that described sequential processing module stores according to described fast clock timing information and this sequential processing inside modules,
Wherein, described present instruction information comprises multiple fast clock waiting time, each communication pattern has the fast clock conversion ratio of correspondence, described current radio frequency transmitting-receiving event is corresponding to current communication mode, and the plurality of fast clock waiting time receives and dispatches conversion of multiple current communication mode waiting times corresponding to event according to the fast clock conversion ratio that described current communication mode is corresponding with described current radio frequency and obtains.
2. rf control unit according to claim 1, it is characterized in that, described clock generation module also comprises slow clock generating unit, described slow clock generating unit is used for producing slow clock signal, described common timing module also comprises slow clock calibration unit, described slow clock calibration unit is connected to described fast clock generating unit and described slow clock generating unit, and described slow clock calibration unit is in order to produce slow clock alignment ratio according to described fast clock signal and described slow clock signal.
3. rf control unit according to claim 2, it is characterized in that, described common timing module also comprises the second timing unit, it is connected to described slow clock generating unit and described sequential processing module, described second timing unit produces slow clock timing information according to described slow clock signal, and described sequential processing module is according to described slow clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing.
4. rf control unit according to claim 3, it is characterized in that, described sequential processing module comprises multiple serial device, it is connected to described first timing unit and described second timing unit, each serial device is according to described fast clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing, or receives and dispatches event according to described slow clock timing information with current radio frequency described in described present instruction information and executing.
5. rf control unit according to claim 1, it is characterized in that, described rf control unit also comprises peripheral interface module, it is connected to described sequential processing module, multiple control signals that described peripheral interface module produces in described current radio frequency transmitting-receiving event procedure for exporting described sequential processing module to perform.
6. a radio frequency time control method, it is applied to comprise the multi-mode communication system of rf control unit, described rf control unit comprises the clock generation module being sequentially connected with, common timing module and sequential processing module, described clock generation module is used for producing fast clock signal, described common timing module is for producing fast clock timing information according to described fast clock signal, it is characterised in that comprise the steps of
Described current radio frequency is received and dispatched event and is resolved to present instruction information by described central processing unit current communication mode belonging to current radio frequency transmitting-receiving event, comprises multiple current communication mode waiting time in described present instruction information；
Described central processing unit obtains the fast clock conversion ratio that this current communication mode of its internal reservoir is corresponding；
The plurality of current communication mode waiting time is converted into multiple fast clock waiting time according to described fast clock conversion ratio by described central processing unit；
Described present instruction information is downloaded to described sequential processing module by described central processing unit,
Wherein, described sequential processing module is according to described fast clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing.
7. radio frequency time control method according to claim 6, it is characterized in that, described clock generation module is additionally operable to produce slow clock signal, described common timing module is additionally operable to produce slow clock timing information according to described slow clock signal, described common timing module is additionally operable to produce slow clock alignment ratio according to described fast clock signal with described slow clock signal, after the plurality of current communication mode waiting time is converted into the step of multiple fast clock waiting time by described central processing unit according to described fast clock conversion ratio, also comprise:
Described central processing unit judges whether have at least a fast clock waiting time in the plurality of fast clock waiting time more than preset duration, if it is not, then enter described central processing unit described present instruction information downloads to the step of described sequential processing module；
If so, described central processing unit obtains described slow clock alignment ratio from described common timing module；
Described fast clock waiting time is resolved into the combination of slow clock waiting time and described fast clock waiting time by described central processing unit according to described slow clock alignment ratio, subsequently into described central processing unit, described present instruction information is downloaded to the step of described sequential processing module
Wherein, described sequential processing module is according to described slow clock timing information and current radio frequency transmitting-receiving event described in described present instruction information and executing.
8. radio frequency time control method according to claim 6, it is characterised in that described sequential processing module comprises multiple serial device, the step that described present instruction information downloads to described sequential processing module is comprised by described central processing unit:
Described central processing unit inquires about whether each serial device is in idle condition successively, if it is not, then repeat this step；
If so, described present instruction information is downloaded to the serial device being currently at idle condition by described central processing unit.
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| CN112422147A (en) * | 2020-10-27 | 2021-02-26 | 上海擎昆信息科技有限公司 | Timing control method and device for 5G multimode communication and storage medium |
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