CN106488515B - A kind of timer, baseband chip and its sleep state switching method - Google Patents
A kind of timer, baseband chip and its sleep state switching method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W36/00—Hand-off or reselection arrangements
- H04W36/0005—Control or signalling for completing the hand-off
- H04W36/0011—Control or signalling for completing the hand-off for data sessions of end-to-end connection
- H04W36/0027—Control or signalling for completing the hand-off for data sessions of end-to-end connection for a plurality of data sessions of end-to-end connections, e.g. multi-call or multi-bearer end-to-end data connections
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The present invention relates to multi-mode communication technical field, a kind of timer, baseband chip and its sleep state switching method are disclosed.Baseband chip in the present invention is applied to multi-mode communication system, includes: the timing module of sleep control module, CPU and each mode；CPU configures pre-switch state for timing module after detecting that timing module meets the condition for exiting working condition；Wherein timing module is counted under pre-switch state using fast clock；Sleep control module generates Sleep Request signal when the non-timed module of each mode is in sleep state or idle state, and exports to the timing module of each mode；Timing module switches to sleep state when receiving Sleep Request signal under pre-switch state；System is switched to deep sleep state when the timing module of all modes enters sleep state by sleep control module.The precision of the Timing Synchronization of the non-traffic mode of multimode system can be improved in this way, reduce system standby power consumption, and reduce the hardware cost of system.
Description
Technical field
The present invention relates to multi-mode communication technical field, in particular to a kind of timer, baseband chip and its sleep state are cut
Change method.
Background technique
In 4G mobile communication system, there are many wireless-access mode and deposit, such as GSM (global system for mobile communications),
TD-SCDMA (TD SDMA), WCDMA (wideband code division multiple access) and LTE (evolution when long) etc..Each mode has one
Distinctive time set is covered, RAT-Timer (Radio Access Technology Timer, wireless access technology timing are denoted as
Device).In view of the power saving of mobile terminal needs, the RAT-Timer of a mode need to be in the access module idle period
It is inside switched to low power consumpting state (sleep pattern), operating mode (normal count status) can be also switched to from sleep pattern.
For there are many access module and depositing, usually thering is a timer to mention under each mode in multi-mode communication system
For required timing information.Communication terminal can be when system be idle, the fast clock (phase of the closing system of times more as far as possible
For clock slow for RTC (real-time clock)) and most of module power supply, system is entered into low power consumpting state, to increase
The cruise duration of battery.Usually increase the function of sleep in timer, i.e. timer can be switched to low power consumpting state.Such as figure
Shown in 1, timer includes three functional modules: clock module, timing module and CPU (central processing unit).Below with LTE mould
The working principle of timer is introduced for formula.Due to the requirement of LTE mode timing, the clock essence of minimum 30.72MHz is needed
Degree, this clock signal are generated by timing module.It include two clock sources in system: when 32K (RTC:Real Time Clock) is slow
Clock and fast clock (such as 26MHz).LTE timing module can be supplied to the following information of CPU: the timing information of LTE mode needs is determined
When device state and Interruption；CPU can also configure the parameter of LTE timer.
The timing module of LTE is introduced below.It is mainly made of counter (not shown) in timing module, and by phase
The comparator (not shown) and latch (not shown) answered generate Interruption and provide timing information.The work shape of counter
State is divided into normal count status (using 30.72M clock count), and sleep state (using 32K clock count) and switching state are (fast
Slow clock is all working, and is a transition state).When counter is in working condition, the input of a fast clock, counter adds
1, when working in a sleep mode, counter will use 32K clock source to count, and counter can be according to RTC clock and 30.72M
The frequency proportions of clock increase count value.In order to reduce system cost, the DCXO (Digital without calibration is generallyd use
Control Oscillator, numerical digit control oscillator) RTC clock source, the precision of RTC is lower, and is influenced by temperature
It is larger.In order to guarantee wireless system timing precision requirement, even if when using slow clock timing, it is also desirable to timing
Device is capable of providing higher timing accuracy.To solve this problem, the slow clock of fast clock alignment is used usually inside timing module
Calibration unit, to improve timing accuracy when slow clock count.In the presence of fast clock, timing module is surveyed using fast clock
Slow clock is measured, that is, slow clock is calibrated with fast clock.The process of calibration is automatically performed by hardware module, the knot of calibration
Fruit represents the duration that a RTC clock duration is equal to how many fast clocks, includes fractional part in this result.Fractional part into
Position can use certain method, such as using the fractional part reprocessing of the final result after accumulative, can be according to rounding up
Or the method directly given up, in this way, can still have calculating here certainly by the precision controlling of counting in a certain range
The loss of precision.
Whether baseband chip can enter according to the state (whether entering sleep state) of each mode timers, each CPU
Sleep pattern, and other module (such as DMA (Direct Memory Access, direct memory access), HWA (Hardware
Accelerator, hardware accelerator) etc.) whether enter idle state, to judge baseband chip and other module (such as power supply moulds
Block, radio-frequency module, audio-frequency module etc.), if enter low power consumpting state (being denoted as deep sleep).Under deep sleep, entirely
System, which is closed, inputs fast clock, and will with it is electric under fast clock related function module, to achieve the purpose that deep power-saving.
As described above, have whether each mode timers enter sleep state in the necessary condition of baseband chip sound sleep,
Namely judge whether timer is counted using RTC clock.When a kind of access module does not have task within a certain period of time, example
Such as standby mode, CPU is needed to configure timer, to be switched to sleep pattern, until at the time of that contemplates that task point, timer
Working condition is automatically switched to after counting expires.Timer in a sleep mode, is counted using RTC clock, although slow clock
It has passed through fast clock alignment, but there are problems that two here, influence whether the timing accuracy of timer under sleep state.
First is that calibrating slow counter due to fast counter has certain calibration accuracy, the realization of general calibration circuit is using fixed point
It calculates, certainly exists the loss of significance of certain calculating.In addition, timer in a calibration process in sleep procedure RTC when
Clock can change, this variation is especially sensitive to temperature change.To guarantee high RTC precision, must just have at two aspects
Higher requirement will increase hard-wired complexity first is that improving RTC calibrates circuit counting precision in this way；In addition, improving school
Quasi- frequency increases the frequency of RTC calibration especially when temperature change is very fast, this way can to temperature detection,
Software controlling strategies and the power consumption of baseband chip have bigger influence.
It is analyzed below for above-mentioned Second Problem.Influence due to temperature to RTC clock is maximum, therefore to reach
Effect is calibrated to preferable RTC, increases temperature sensing circuit, real-time detection board (especially around RTC) temperature in usual board
Degree variation just starts RTC calibration when rate of temperature change reaches certain thresholding.It certainly will need additionally to increase temperature in this way
Degree calibration circuit, and detection temperature bring power consumption.In addition, the work since the strategy of RTC calibration is relative complex, with terminal
State, the process of protocol stack sofeware and the physical characteristic of terminal are related, especially in the system of multi-mode and multi-standby (standby), this
Calibration will be more complicated.Rely solely on software starting calibration circuit to eliminate the unstability of RTC, in actual application
It is very difficult.Again, RTC calibration module needs fast clock at work, when system reaches sleep condition,
System originally can enter deep sleep modes, but since calibration circuit is working, whole system be caused to cannot be introduced into sound sleep.The school RTC
Quasi-mode block primary calibration duration is about in hundred ms (millisecond) magnitude, so being to have a great impact to the consumption of the power of system.
If this calibration circuit (non-deep sleep) during system worked well, then additional power consumption is exactly to calibrate the expense of circuit,
It can so ignore substantially.If but all meet in the other conditions of system sound sleep process alignment or system sound sleep, only
Calibration circuit work cause system can not sound sleep, then just will increase additional power consumption, such as when system standby, mostly
System enters the power consumption of sound sleep about at 5~8mw or so (by taking current LTE multimode smart phone as an example), if being in number situations
System can not sound sleep, then lowest power consumption is also in 60mw or more.The work frequency for calibrating circuit is related with software calibration strategy, simultaneously
Also and network environment and system-operating environment are related.Clock after calibration is set to reach higher timing accuracy and require phase
To more frequent starting calibration circuit, then the power consumption additionally introduced is also larger on the influence of the stand-by power consumption of system, according to reality
Border test as a result, under certain network environment, will increase 2~5% or so stand-by power consumption.
When having an access module in system in working condition, corresponding timer is work in normal count status,
Even if the timer of so other modes is switched to sleep state, whole system still not can enter deep sleep.When fast at this time
Clock is existing, and with network be it is synchronous, precision is guaranteed.Using not calibrated RTC clock timing accuracy most
Large deviation substantially in +/- 20ppm (parts per million, hundred a ten thousandths), timer after too fast clock alignment
Accuracy of timekeeping uses fast clock as the clock source of timer in 1~4ppm (hundred a ten thousandths) left and right, and precision usually can be with
Reach 0.1ppm.The timer of non-operating mode is switched to sleep pattern, uses slow clock as counting clock source, then at that time
Between precision just determined by the RTC clock precision after calibrating, compared with fast clock count, then certainly existing in foregoing description
The loss of the accuracy of timekeeping of analysis.
Summary of the invention
It, can be with present invention solves the problem in that provide a kind of timer, baseband chip and its sleep state switching method
Improve the precision of the Timing Synchronization of the non-traffic mode of multimode system；The frequency of RTC calibration can be effectively reduced, to make system most
Entering under deep sleep more than possible, reduce system standby power consumption；The software of multimode system RTC clock calibration function can be reduced
Implementation complexity；More inexpensive RTC clock source can also be selected, to drop in the range of Timing Synchronization required precision
The hardware cost of low system.
In order to solve the above technical problems, embodiments of the present invention provide a kind of baseband chip, it is applied to multi-mode communication
System includes: the timing module of sleep control module, central processing unit CPU and each mode；
The CPU, for when detecting that timing module satisfaction exits the condition of working condition by the timing mould
Block is configured to pre-switch state；Wherein, the timing module is counted under pre-switch state using fast clock；
The sleep control module is in sleep state or idle state for the non-timed module in each mode
When, the Sleep Request signal is generated, and export to the timing module of each mode；Wherein, the non-timed module includes except fixed
When module other than all modules；
The timing module switches to sleep shape when for receiving the Sleep Request signal under pre-switch state
State；
The sleep control module is when the timing module of all modes enters sleep state by the multi-mode communication system
System switches to deep sleep state.
Embodiments of the present invention additionally provide a kind of sleep state switching method of baseband chip, are applied to multi-mode communication
System, the baseband chip includes: the timing module of sleep control module, central processing unit CPU and each mode；
The sleep state switching method of the baseband chip comprises the steps of:
The CPU configures the timing module when detecting that the timing module satisfaction exits the condition of working condition
For pre-switch state；Wherein, the timing module is counted under pre-switch state using fast clock；
The sleep control module is produced when the non-timed module of each mode is in sleep state or idle state
The raw Sleep Request signal, and export to the timing module of each mode；Wherein, the non-timed module includes to remove timing module
All modules in addition；
The timing module switches to sleep state when receiving the Sleep Request signal under pre-switch state；
The sleep control module is when the timing module of all modes enters sleep state by the multi-mode communication system
System switches to deep sleep state.
Embodiments of the present invention additionally provide a kind of timer, are applied to multi-mode communication system, the timer is full
Foot enters pre-switch state when exiting the condition of working condition, and switching when receiving under pre-switch state Sleep Request signal
To sleep state；Wherein, the timer is counted under the pre-switch state using fast clock.
Embodiment of the present invention in terms of existing technologies, CPU detect timing module satisfaction exit working condition
Condition when by timing module configure pre-switch state, and timing module is counted under pre-switch state using fast clock
Number, in this way, and then ensure that the precision of timing, while also without increase volume it is ensured that use fast clock count as much as possible
Outer power consumption；Moreover, entering deep sleep shape after the timing module of each mode exits working condition and in multi-mode communication system
It before state, is counted using fast clock, the frequency of RTC calibration can be effectively reduced, to allow system is as much as possible to be in
Under deep sleep, system standby power consumption is reduced；Sleep control module is only in the non-timed module of each mode all in sleep
When state or idle state, i.e., when system does not need to be run at working condition, Sleep Request signal is just generated, and pass through sleep
The timing module that request signal controls all modes enters sleep state, and then multi-mode communication system is promoted to enter deep sleep shape
State utmostly reduces system power dissipation；Further, since timing module (is included in pre-switch state to cutting as far as possible for a long time
In a period of changing state) fast clock count is used, that is, counted in short time using slow clock (real-time clock) as far as possible, that
In the case where system timing requirements are constant, so that it may reduce the requirement of slow clock source, and the calibration low using complexity
Software algorithm, it can reduce the software realization complexity of multimode system RTC clock calibration function, and wanted in Timing Synchronization precision
In the range of asking, more inexpensive RTC clock source is selected, to reduce the hardware cost of system.
In addition, the sleep control module is to include the logic circuit with door；The free time of the non-timed module of all modes
Signal is by generating the Sleep Request signal after described and Men Xiangyu.It can guarantee only have by the logic circuit realized with door
Sleep Request signal is just generated when the non-timed module of all modes all enters idle state.
In addition, the sleep control module also includes output port；The output port is connected with the logic circuit；Institute
Output port is stated, for exporting the timing module of the Sleep Request signal to each mode.One is added for sleep control module
For exporting the output port of Sleep Request signal, the feasibility of originally invention embodiment ensure that.
Detailed description of the invention
Fig. 1 is the structural schematic diagram according to timer in the prior art；
Fig. 2 is the functional block diagram of the baseband chip in first embodiment according to the present invention；
Fig. 3 is the state switching schematic diagram of the timing module of first embodiment according to the present invention；
Fig. 4 is to switch schematic diagram according to the state of timer in the prior art；
Fig. 5 is the logic circuit schematic diagram of the sleep control module in first embodiment according to the present invention；
Fig. 6 is the logic circuit schematic diagram of the CPU in first embodiment according to the present invention；
Fig. 7 is the sleep state switching method flow chart of the baseband chip of third embodiment according to the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to each reality of the invention
The mode of applying is explained in detail.However, it will be understood by those skilled in the art that in each embodiment of the present invention,
In order to make the reader understand this application better, many technical details are proposed.But even if without these technical details and base
In the various changes and modifications of following embodiment, each claim of the application technical side claimed also may be implemented
Case.
The first embodiment of the present invention is related to a kind of baseband chips, are applied to multi-mode communication system, specifically such as Fig. 2 institute
Show, include: sleep control module, each mode central processing unit (CPU) and each mode timing module.
The CPU of each mode is when detecting that corresponding timing module satisfaction exits the condition of working condition by timing module elder generation
It is configured to pre-switch state, specifically as shown in figure 3, timing module receives Sleep Request signal Shi Zaijing under pre-switch state
Switching state switches to sleep state；Wherein, timing module is counted under pre-switch state using fast clock；301 are positive
Normal count status is switched to pre-switch state, and 302 switch to switching state for pre-switch state, and 303 switch to for switching state
Sleep state, 304 to wake up timer when timer switching state switched to by sleep state, 305 is are switched by switching state
To normal count status.
With the prior art (as shown in figure 4, timing module when exiting working condition, is directly switched to through switching state and slept
Dormancy state；Wherein, 401 switching state is first switched to by normal count status for timing module, 303 be to be switched to by switching state
Sleep state) it compares, it is ensured that fast clock count is used as much as possible, also ensures that the communication pattern using the timer
Timing precision, while also without increasing additional power consumption.Moreover, in the timing mould of the communication pattern using the timing module
Block exits after working condition and before multi-mode communication system enters deep sleep state, is counted only with fast clock, can
To effectively reduce the frequency of RTC calibration, to make system as much as possible under deep sleep, system standby power consumption is reduced.
Specifically, the timing module of each mode includes a register；The CPU of each mode is detecting corresponding timing
Corresponding timing module is configured pre-switch state by trigger register when module satisfaction exits the condition of working condition.Wherein,
Register memory contains the configuration information of timing module pre-switch state.
Sleep control module generates sleep and asks when the non-timed module of each mode is in sleep state or idle state
Signal is sought, and is exported to the timing module of each mode；Wherein, non-timed module includes all modules in addition to timing module,
For example, CPU, DMA and HWA etc..
Specifically, sleep control module is also to be additionally arranged one in sleep control module comprising the logic circuit with door
Output port, the output port are connected with logic circuit.For by the non-timed, module only includes CPU, DMA and HWA below into
Row illustrates.Specifically as shown in figure 5, the logic circuit in present embodiment includes 6 and door 501~506.
Wherein, it is used to input the status signal of each mode timing module, the state letter of timing module with the input terminal of door 501
Number include sleep state and non-sleep state, wherein sleep state can be defined as state 1, and non-sleep state can be defined as
State 0, by with behind the door, when the state of the timing module of only all modes is all sleep state, with 501 ability output state of door
1, that is, the timing module for representing all modes enters sleep state.
It is used to input the status signal of the CPU of each mode with the input terminal of door 502, the status signal of CPU includes idle shape
State and busy state, wherein idle state can be defined as state 1, and busy state can be defined as state 0, by with
Behind the door, when the state of the CPU of only all modes is all idle state, with 502 ability output state 1 of door, that is, all modes are represented
CPU enter idle state.For example, multi-mode communication system in present embodiment includes 3 kinds of communication patterns, then this embodiment party
In formula with door 502 as shown in fig. 6, each input terminal inputs a kind of CPU state signal of communication pattern comprising 3 input terminals,
Wherein, the idle state corresponding states 1 of CPU, busy state corresponding states 0, only with 601~603 equal output state 1 of door when
With 502 ability output state 1 of door.To sum up, only just being exported when the CPU of all modes is in idle state with door 502
State 1.
Similarly, it is used to input the status signal of the DMA of each mode with the input terminal of door 503, the status signal of DMA includes sky
Not busy state and busy state, wherein idle state can be defined as state 1, and busy state can be defined as state 0, warp
It crosses with behind the door, when the state of the DMA of only all modes is all idle state, with 503 ability output state 1 of door, that is, represents all
The DMA of mode enters idle state.
Similarly, it is used to input the status signal of the HWA of each mode with the input terminal of door 504, the status signal of HWA includes sky
Not busy state and busy state, wherein idle state can be defined as state 1, and busy state can be defined as state 0, warp
It crosses with behind the door, when the state of the HWA of only all modes is all idle state, with 504 ability output state 1 of door, that is, represents all
The HWA of mode enters idle state.
As shown in Figure 5, only connect with the output end of door 502~504 with the input terminal of door 506, and only with door 502
When~504 output end output is state 1, with 506 ability output state 1 of door, wherein the representative of state 1 exported with door 506 is slept
Dormancy request signal, i.e., only when non-timed module enters sleep state or idle state, just output sleep is asked with door 506
Signal is sought, it is, the idle signal of the non-timed module of all modes with 506 phase of door and the rear Sleep Request that generates by believing
Number.
The output port increased newly in sleep control module exports the timing module of above-mentioned Sleep Request signal to each mode.Respectively
It is switched to when the timing module of mode receives Sleep Request signal under pre-switch state from pre-switch state through switching state
Sleep state.
Fig. 5 is returned, as shown in Figure 5, is connect with the input terminal of door 505 with the output end of door 501~504, only
When output state 1 equal with the output end of door 501~504, with 505 ability output state 1 of door, wherein the state 1 exported with door 505
Representative can make system enter the system sleep enable signal of deep sleep state that is, the timing module of only each mode is equal
Into sleep state, and non-timed module also all enters idle state, sleeps enable signal with 505 ability generation system of door, also
It is to say, the sleep control module of baseband chip is when the timing module of all modes enters sleep state just by multi-mode communication system
System switches to deep sleep state.
It should be noted that can only include a CPU in baseband chip, for controlling the timing mould of multiple modes
Block is also possible to multiple CPU to control each timing module respectively, in embodiments of the present invention with no restrictions.
Compared with prior art, CPU is when detecting that timing module satisfaction exits the condition of working condition by timing module
It is configured to pre-switch state, and timing module is counted under pre-switch state using fast clock, in this way, it is ensured that the greatest extent may be used
Energy ground uses fast clock count, and then ensure that the precision of timing, while also without increasing additional power consumption；Moreover, in each mould
The timing module of formula exits after working condition and before multi-mode communication system enters deep sleep state, is carried out using fast clock
It counts, the frequency of RTC calibration can be effectively reduced, to make system as much as possible under deep sleep, reduction system is waited for
Machine power consumption；Sleep control module is only when the non-timed module of each mode is all in sleep state or idle state, i.e.,
When system does not need to be run at working condition, Sleep Request signal is just generated, and all modes are controlled by Sleep Request signal
Timing module enter sleep state, and then multi-mode communication system is promoted to enter deep sleep state, by system power dissipation maximum journey
Degree reduces；Further, since (in a period of being included in pre-switch state to switching state) uses timing module for a long time as far as possible
Fast clock count, that is, as far as possible in short time using slow clock (real-time clock) count, then system timing requirements not
In the case where change, so that it may reduce the requirement of slow clock source, and the calibration software algorithm low using complexity, it can reduce
The software realization complexity of multimode system RTC clock calibration function, and in the range of Timing Synchronization required precision, selection is more
The RTC clock source of low cost, to reduce the hardware cost of system.
Second embodiment of the present invention is related to a kind of timer, is applied to multi-mode communication system, which is meeting
Enter pre-switch state when exiting the condition of working condition (normal count status), and receives sleep under pre-switch state and ask
Sleep state is switched to again when seeking signal；Wherein, timer is counted under pre-switch state using fast clock.
Compared with prior art, it is ensured that use fast clock count as much as possible, also ensure that using the timer
Communication pattern timing precision, while also without increasing additional power consumption.Moreover, in the communication pattern using the timer
Timing module exit after working condition and before multi-mode communication system enters deep sleep state, carried out only with fast clock
It counts, the frequency of RTC calibration can be effectively reduced, to make system as much as possible under deep sleep, reduction system is waited for
Machine power consumption.
It should be noted that the configuration of timer and current existing device is compatible, it, can be effective without additional modification
Promote the performance of Timing Synchronization.
Third embodiment of the invention is related to a kind of sleep state switching method of baseband chip, as shown in fig. 7, comprising with
Lower step:
Step 701, CPU detects whether timing module meets the condition for exiting working condition.If so, 702 are thened follow the steps,
Otherwise, step 701 is continued to execute.
Step 702, timing module is configured pre-switch state by CPU.Wherein, timing module uses under pre-switch state
Fast clock is counted.Specifically, CPU triggers timing mould when detecting that timing module satisfaction exits the condition of working condition
Timing module is configured pre-switch state by register in block.Wherein, register memory contains timing module pre-switch state
Configuration information.
Step 703, sleep control module is produced when the non-timed module of each mode is in sleep state or idle state
Raw Sleep Request signal, and export to the timing module of each mode；Wherein, non-timed module includes the institute in addition to timing module
There is module.In this step, the idle signal of the non-timed module of mode by sleep control module with produced after Men Xiangyu
Raw Sleep Request signal.
Step 704, sleep state is switched to when timing module receives Sleep Request signal under pre-switch state.At this
In step, the timing module of Sleep Request signal to each mode is exported by the output port of sleep control module.
Step 705, sleep control module is when the timing module of all modes enters sleep state by multi-mode communication system
System switches to deep sleep state.
The step of various methods divide above, be intended merely to describe it is clear, when realization can be merged into a step or
Certain steps are split, multiple steps are decomposed into, as long as comprising identical logical relation, all in the protection scope of this patent
It is interior；To adding inessential modification in algorithm or in process or introducing inessential design, but its algorithm is not changed
Core design with process is all in the protection scope of the patent.
It is not difficult to find that present embodiment is embodiment of the method corresponding with first embodiment, present embodiment can be with
First embodiment is worked in coordination implementation.The relevant technical details mentioned in first embodiment still have in the present embodiment
Effect, in order to reduce repetition, which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in
In first embodiment.
It will be understood by those skilled in the art that the respective embodiments described above are to realize specific embodiments of the present invention,
And in practical applications, can to it, various changes can be made in the form and details, without departing from the spirit and scope of the present invention.
Claims (7)
1. a kind of baseband chip is applied to multi-mode communication system, characterized by comprising: sleep control module, central processing list
The timing module of first CPU and each mode；
The CPU, for matching the timing module when detecting that the timing module satisfaction exits the condition of working condition
It is set to pre-switch state；Wherein, the timing module is counted under pre-switch state using fast clock；
The sleep control module, for when the non-timed module of each mode is in sleep state or idle state,
The Sleep Request signal is generated, and is exported to the timing module of each mode；Wherein, the non-timed module includes to remove timing mould
All modules other than block；
The timing module switches to sleep state when for receiving the Sleep Request signal under pre-switch state；
The sleep control module cuts the multi-mode communication system when the timing module of all modes enters sleep state
Shift to deep sleep state.
2. baseband chip according to claim 1, which is characterized in that the sleep control module is to include the logic with door
Circuit；
The idle signal of the non-timed module of all modes is by generating the Sleep Request signal after described and Men Xiangyu.
3. baseband chip according to claim 2, which is characterized in that the sleep control module also includes output port；
The output port is connected with the logic circuit；
The output port, for exporting the timing module of the Sleep Request signal to each mode.
4. a kind of sleep state switching method of baseband chip is applied to multi-mode communication system, which is characterized in that the base band core
Piece includes: the timing module of sleep control module, central processing unit CPU and each mode；
The sleep state switching method of the baseband chip comprises the steps of:
The CPU configures the timing module to when detecting that the timing module satisfaction exits the condition of working condition pre-
Switching state；Wherein, the timing module is counted under pre-switch state using fast clock；
The sleep control module generates institute when the non-timed module of each mode is in sleep state or idle state
Sleep Request signal is stated, and is exported to the timing module of each mode；Wherein, the non-timed module includes in addition to timing module
All modules；
The timing module switches to sleep state when receiving the Sleep Request signal under pre-switch state；
The sleep control module cuts the multi-mode communication system when the timing module of all modes enters sleep state
Shift to deep sleep state.
5. the sleep state switching method of baseband chip according to claim 4, which is characterized in that described in the generation
In the step of Sleep Request signal,
The idle signal of the non-timed module of all modes by the sleep control module with generated after Men Xiangyu described in
Sleep Request signal.
6. the sleep state switching method of baseband chip according to claim 4, which is characterized in that asked by the sleep
In the step of asking signal to export to the timing module of each mode,
The timing module of the Sleep Request signal to each mode is exported by the output port of the sleep control module.
7. a kind of timer is applied to multi-mode communication system, which is characterized in that the timer exits working condition in satisfaction
Sleep state is switched to when entering pre-switch state when condition, and receiving under pre-switch state Sleep Request signal；Wherein,
The timer is counted under the pre-switch state using fast clock, and the Sleep Request signal is sleep control module
The generated signal when the non-timed module of each mode is in sleep state or idle state.
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